e286869b24
- Why I did it 1. Update Mellanox HW-MGMT package to newer version V.7.0030.1011 2. Replace the SONiC PMON Thermal control algorithm with the one inside the HW-MGMT package on all Nvidia platforms 3. Support Spectrum-4 systems - How I did it 1. Update the HW-MGMT package version number and submodule pointer 2. Remove the thermal control algorithm implementation from Mellanox platform API 3. Revise the patch to HW-MGMT package which will disable HW-MGMT from running on SIMX 4. Update the downstream kernel patch list Signed-off-by: Kebo Liu <kebol@nvidia.com>
100 lines
4.3 KiB
Diff
100 lines
4.3 KiB
Diff
From e1d377039ba9a364f4e7f9816f5f0b7a3b165b43 Mon Sep 17 00:00:00 2001
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From: Vadim Pasternak <vadimp@nvidia.com>
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Date: Wed, 18 Jan 2023 15:08:46 +0200
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Subject: [PATCH backport 5.10 07/10] platform: mellanox: mlx-platform: Add mux
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selection register to regmap
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Extend writeable, readable, volatile registers of the 'regmap' object
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with for I2C mux selector registers.
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The motivation is to pass this object extended with selector registers
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to I2C mux driver working over ‘regmap’.
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Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
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---
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drivers/platform/x86/mlx-platform.c | 28 ++++++++++++++++++++--------
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1 file changed, 20 insertions(+), 8 deletions(-)
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diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
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index e8c656d6e..03c744f37 100644
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--- a/drivers/platform/x86/mlx-platform.c
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+++ b/drivers/platform/x86/mlx-platform.c
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@@ -140,6 +140,10 @@
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#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
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#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
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#define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9
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+#define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb
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+#define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda
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+#define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc
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+#define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd
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#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde
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#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf
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#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0
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@@ -173,23 +177,19 @@
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#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc
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#define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd
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#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
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-#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
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-#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
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-#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc
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-#define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd
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#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
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#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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- MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \
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+ MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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- MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \
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+ MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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- MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \
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+ MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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#define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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- MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \
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+ MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
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@@ -5307,6 +5307,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
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@@ -5434,6 +5438,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
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@@ -5581,6 +5589,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
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--
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2.20.1
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