2f97faaf7c
Issue: Port with AOC cable does not come up when "sfputil reset <port_name>" is executed. Modified the incorrect mask used in reset API to resolve the issue.
290 lines
7.6 KiB
Python
290 lines
7.6 KiB
Python
# sfputil.py
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#
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# Platform-specific SFP transceiver interface for SONiC
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#
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# For S5248F-ON, hardware version X01
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try:
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import struct
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import sys
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import getopt
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import time
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from sonic_sfp.sfputilbase import SfpUtilBase
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from os import *
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from mmap import *
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except ImportError as e:
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raise ImportError("%s - required module not found" % str(e))
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class SfpUtil(SfpUtilBase):
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"""Platform-specific SfpUtil class"""
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PORT_START = 1
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PORT_END = 56
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PORTS_IN_BLOCK = 56
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BASE_RES_PATH = "/sys/bus/pci/devices/0000:04:00.0/resource0"
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_port_to_i2c_mapping = {
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1: 2,
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2: 3,
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3: 4,
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4: 5,
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5: 6,
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6: 7,
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7: 8,
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8: 9,
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9: 10,
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10: 11,
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11: 12,
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12: 13,
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13: 14,
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14: 15,
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15: 16,
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16: 17,
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17: 18,
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18: 19,
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19: 20,
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20: 21,
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21: 22,
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22: 23,
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23: 24,
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24: 25,
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25: 26,
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26: 27,
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27: 28,
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28: 29,
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29: 30,
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30: 31,
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31: 32,
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32: 33,
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33: 34,
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34: 35,
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35: 36,
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36: 37,
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37: 38,
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38: 39,
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39: 40,
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40: 41,
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41: 42,
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42: 43,
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43: 44,
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44: 45,
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45: 46,
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46: 47,
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47: 48,
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48: 49,
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# DD + QSFP28
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49: 50,
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50: 50,
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51: 51,
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52: 51,
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53: 52,
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54: 53,
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55: 54,
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56: 55,
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}
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_port_to_eeprom_mapping = {}
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_global_port_pres_dict = {}
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@property
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def port_start(self):
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return self.PORT_START
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@property
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def port_end(self):
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return self.PORT_END
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@property
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def qsfp_ports(self):
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return range(49, self.PORTS_IN_BLOCK + 1)
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@property
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def port_to_eeprom_mapping(self):
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return self._port_to_eeprom_mapping
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def pci_mem_read(self, mm, offset):
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mm.seek(offset)
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read_data_stream=mm.read(4)
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reg_val=struct.unpack('I',read_data_stream)
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mem_val = str(reg_val)[1:-2]
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# print "reg_val read:%x"%reg_val
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return mem_val
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def pci_mem_write(self, mm, offset, data):
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mm.seek(offset)
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# print "data to write:%x"%data
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mm.write(struct.pack('I',data))
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def pci_set_value(self, resource, val, offset):
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fd = open(resource, O_RDWR)
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mm = mmap(fd, 0)
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val = self.pci_mem_write(mm, offset, val)
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mm.close()
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close(fd)
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return val
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def pci_get_value(self, resource, offset):
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fd = open(resource, O_RDWR)
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mm = mmap(fd, 0)
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val = self.pci_mem_read(mm, offset)
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mm.close()
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close(fd)
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return val
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def init_global_port_presence(self):
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for port_num in range(self.port_start, (self.port_end + 1)):
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presence = self.get_presence(port_num)
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if(presence):
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self._global_port_pres_dict[port_num] = '1'
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else:
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self._global_port_pres_dict[port_num] = '0'
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def __init__(self):
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eeprom_path = "/sys/class/i2c-adapter/i2c-{0}/{0}-0050/eeprom"
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for x in range(self.port_start, self.port_end + 1):
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self.port_to_eeprom_mapping[x] = eeprom_path.format(
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self._port_to_i2c_mapping[x])
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self.init_global_port_presence()
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SfpUtilBase.__init__(self)
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def get_presence(self, port_num):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# Port offset starts with 0x4004
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port_offset = 16388 + ((port_num-1) * 16)
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status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
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reg_value = int(status)
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# Absence of status throws error
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if (reg_value == "" ):
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return False
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# Mask off bit for presence
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mask = (1 << 1)
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if (port_num > 48):
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mask = (1 << 4)
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# ModPrsL is active low
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if reg_value & mask == 0:
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return True
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return False
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def get_low_power_mode(self, port_num):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# Port offset starts with 0x4000
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port_offset = 16384 + ((port_num-1) * 16)
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status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
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reg_value = int(status)
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# Absence of status throws error
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if (reg_value == "" ):
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return False
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# Mask off 4th bit for presence
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mask = (1 << 6)
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# LPMode is active high
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if reg_value & mask == 0:
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return False
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return True
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def set_low_power_mode(self, port_num, lpmode):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# Port offset starts with 0x4000
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port_offset = 16384 + ((port_num-1) * 16)
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status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
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reg_value = int(status)
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# Absence of status throws error
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if (reg_value == "" ):
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return False
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# Mask off 6th bit for lpmode
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mask = (1 << 6)
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# LPMode is active high; set or clear the bit accordingly
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if lpmode is True:
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reg_value = reg_value | mask
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else:
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reg_value = reg_value & ~mask
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# Convert our register value back to a hex string and write back
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status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
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return True
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def reset(self, port_num):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# Port offset starts with 0x4000
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port_offset = 16384 + ((port_num-1) * 16)
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status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
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reg_value = int(status)
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# Absence of status throws error
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if (reg_value == "" ):
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return False
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# Mask off 4th bit for presence
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mask = (1 << 4)
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# ResetL is active low
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reg_value = reg_value & ~mask
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# Convert our register value back to a hex string and write back
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status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
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# Sleep 1 second to allow it to settle
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time.sleep(1)
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reg_value = reg_value | mask
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# Convert our register value back to a hex string and write back
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status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
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return True
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def get_transceiver_change_event(self, timeout=0):
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port_dict = {}
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while True:
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for port_num in range(self.port_start, (self.port_end + 1)):
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presence = self.get_presence(port_num)
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if(presence and self._global_port_pres_dict[port_num] == '0'):
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self._global_port_pres_dict[port_num] = '1'
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port_dict[port_num] = '1'
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elif(not presence and
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self._global_port_pres_dict[port_num] == '1'):
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self._global_port_pres_dict[port_num] = '0'
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port_dict[port_num] = '0'
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if(len(port_dict) > 0):
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return True, port_dict
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time.sleep(0.5)
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