e286869b24
- Why I did it 1. Update Mellanox HW-MGMT package to newer version V.7.0030.1011 2. Replace the SONiC PMON Thermal control algorithm with the one inside the HW-MGMT package on all Nvidia platforms 3. Support Spectrum-4 systems - How I did it 1. Update the HW-MGMT package version number and submodule pointer 2. Remove the thermal control algorithm implementation from Mellanox platform API 3. Revise the patch to HW-MGMT package which will disable HW-MGMT from running on SIMX 4. Update the downstream kernel patch list Signed-off-by: Kebo Liu <kebol@nvidia.com>
139 lines
5.0 KiB
Diff
139 lines
5.0 KiB
Diff
From a556177a2359c784e063f0914049ffd7f8d8852d Mon Sep 17 00:00:00 2001
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From: Vadim Pasternak <vadimp@nvidia.com>
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Date: Tue, 22 Nov 2022 21:20:49 +0200
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Subject: [PATCH backport 5.10 087/150] platform: mellanox: mlx-platform: Add
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reset and extend poweroff callbacks
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On ARM based systems reset and poweroff flow should include special
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actions against CPLD device for performing graceful operations.
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For reset it is necessary to toggle special PLATFORM_RESET# signal, for
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poweroff special HALT# signal.
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In order to support such flows relevant actions are provided.
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Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
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---
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drivers/platform/mellanox/mlx-platform.c | 35 ++++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
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index b1c8632d6..849fdf5de 100644
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--- a/drivers/platform/mellanox/mlx-platform.c
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+++ b/drivers/platform/mellanox/mlx-platform.c
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@@ -43,6 +43,7 @@
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#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
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#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
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#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
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+#define MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET 0x19
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#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
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#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
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#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
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@@ -263,6 +264,7 @@
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#define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0)
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#define MLXPLAT_CPLD_HALT_MASK BIT(3)
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+#define MLXPLAT_CPLD_RESET_MASK 0xfe
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/* Default I2C parent bus number */
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#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
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@@ -483,6 +485,7 @@ static int mlxplat_mux_num;
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static int mlxplat_mux_hotplug_num;
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static struct i2c_mux_reg_platform_data *mlxplat_mux_data;
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static struct i2c_mux_regmap_platform_data *mlxplat_mux_regmap_data;
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+static struct notifier_block *mlxplat_reboot_nb;
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/* Platform extended mux data */
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static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = {
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@@ -5280,6 +5283,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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switch (reg) {
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case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
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@@ -5387,6 +5391,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
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@@ -5546,6 +5551,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
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@@ -5928,12 +5934,31 @@ static const struct regmap_config *mlxplat_regmap_config;
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static struct spi_board_info *mlxplat_spi;
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static struct pci_dev *fpga_dev;
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+/* Platform default reset function */
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+static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused)
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+{
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+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
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+
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+ if (action == SYS_RESTART)
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+ regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET,
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+ MLXPLAT_CPLD_RESET_MASK);
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+
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+ return NOTIFY_DONE;
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+}
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+
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+static struct notifier_block mlxplat_reboot_default_nb = {
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+ .notifier_call = mlxplat_reboot_notifier,
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+};
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+
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/* Platform default poweroff function */
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static void mlxplat_poweroff(void)
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{
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struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
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+ if (mlxplat_reboot_nb)
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+ unregister_reboot_notifier(mlxplat_reboot_nb);
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regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK);
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+ kernel_halt();
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}
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static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
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@@ -6305,6 +6330,7 @@ static int __init mlxplat_dmi_bf3_comex_default_matched(const struct dmi_system_
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mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
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mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
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mlxplat_regmap_config = &mlxplat_fpga_regmap_config_bf3_comex_default;
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+ mlxplat_reboot_nb = &mlxplat_reboot_default_nb;
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pm_power_off = mlxplat_poweroff;
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return 1;
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@@ -7012,8 +7038,15 @@ static int __init mlxplat_init(void)
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if (err)
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goto fail_regcache_sync;
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+ if (mlxplat_reboot_nb) {
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+ err = register_reboot_notifier(mlxplat_reboot_nb);
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+ if (err)
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+ goto fail_register_reboot_notifier;
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+ }
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+
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return 0;
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+fail_register_reboot_notifier:
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fail_regcache_sync:
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mlxplat_pre_exit(priv);
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fail_mlxplat_i2c_main_init:
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@@ -7031,6 +7064,8 @@ static void __exit mlxplat_exit(void)
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if (pm_power_off)
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pm_power_off = NULL;
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+ if (mlxplat_reboot_nb)
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+ unregister_reboot_notifier(mlxplat_reboot_nb);
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mlxplat_pre_exit(priv);
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mlxplat_i2c_main_exit(priv);
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}
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--
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2.20.1
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