Stephen Sun 646a886a11 [Mellanox] Adjust buffer parameters with 2km cable supported for 4600C non-generic SKUs (#9215) ... - Why I did it Also recalculated all parameters with the latest algorithm with per-speed peer response time taken into account - How I did it Detailed information of each SKU: C64: t0: 32 100G downlinks and 32 100G uplinks t1: 56 100G downlinks and 8 100G uplinks with 2km-cable supported D112C8: 112 50G downlinks and 8 100G uplinks. D48C40: 48 50G downlinks, 32 100G downlinks, and 8 100G uplinks D100C12S2: 4 100G downlinks, 2 10G downlinks, 100 50G downlinks, and 8 100G uplinks 2km cable is supported for C64 on t1 only - How to verify it Run regression test (QoS) Signed-off-by: Stephen Sun <stephens@nvidia.com>		2021-12-26 20:58:16 -08:00
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buffers_defaults_objects.j2	[Reclaim buffer] Reclaim unused buffers by applying zero buffer profiles (#8768)	2021-11-29 08:04:01 -08:00
buffers_defaults_t0.j2	[Mellanox] Adjust buffer parameters with 2km cable supported for 4600C non-generic SKUs (#9215)	2021-12-26 20:58:16 -08:00
buffers_defaults_t1.j2	[Mellanox] Adjust buffer parameters with 2km cable supported for 4600C non-generic SKUs (#9215)	2021-12-26 20:58:16 -08:00
buffers_dynamic.json.j2	Adding new SKU Mellanox-SN4600C-C4 (#7815)	2021-06-17 10:04:38 -07:00
buffers.json.j2	Adding new SKU Mellanox-SN4600C-C4 (#7815)	2021-06-17 10:04:38 -07:00
hwsku.json	[Mellanox][master][SKU] sonic interface names are aligned to 4 instead of 8 for 4600/4600C platforms (#8155)	2021-07-13 18:59:48 -07:00
pg_profile_lookup.ini	Adding new SKU Mellanox-SN4600C-C4 (#7815)	2021-06-17 10:04:38 -07:00
port_config.ini	Adding new SKU Mellanox-SN4600C-C4 (#7815)	2021-06-17 10:04:38 -07:00
qos.json.j2	Adding new SKU Mellanox-SN4600C-C4 (#7815)	2021-06-17 10:04:38 -07:00
sai_4600C.xml	Adding new SKU Mellanox-SN4600C-C4 (#7815)	2021-06-17 10:04:38 -07:00
sai.profile	[Mellanox] Update SKUs to enable SDK dumps (#7708)	2021-06-21 16:41:18 +03:00