187 lines
3.7 KiB
C
187 lines
3.7 KiB
C
/* register offset define */
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#define QSFP_FRONT_LOW_POWER_REG 0x60
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#define QSFP_REAR_LOW_POWER_REG 0x61
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#define QSFP_FRONT_RESET_REG 0x70
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#define QSFP_REAR_RESET_REG 0x71
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#define QSFP_FRONT_PRESENT_REG 0x80
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#define QSFP_REAR_PRESENT_REG 0x81
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#define QSFP_FRONT_INT_REG 0x90
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#define QSFP_REAR_INT_REG 0x91
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#define QSFP_RESET 1
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unsigned char qsfp_low_power_regs[33][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0x60, 0x01},
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{0x60, 0x02},
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{0x60, 0x04},
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{0x60, 0x08},
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{0x60, 0x10},
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{0x60, 0x20},
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{0x60, 0x40},
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{0x60, 0x80},
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{0x61, 0x01},
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{0x61, 0x02},
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{0x61, 0x04},
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{0x61, 0x08},
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{0x61, 0x10},
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{0x61, 0x20},
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{0x61, 0x40},
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{0x61, 0x80},
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{0x60, 0x01},
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{0x60, 0x02},
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{0x60, 0x04},
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{0x60, 0x08},
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{0x60, 0x10},
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{0x60, 0x20},
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{0x60, 0x40},
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{0x60, 0x80},
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{0x61, 0x01},
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{0x61, 0x02},
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{0x61, 0x04},
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{0x61, 0x08},
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{0x61, 0x10},
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{0x61, 0x20},
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{0x61, 0x40},
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{0x61, 0x80}
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};
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unsigned char qsfp_reset_regs[33][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0x70, 0x01},
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{0x70, 0x02},
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{0x70, 0x04},
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{0x70, 0x08},
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{0x70, 0x10},
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{0x70, 0x20},
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{0x70, 0x40},
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{0x70, 0x80},
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{0x71, 0x01},
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{0x71, 0x02},
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{0x71, 0x04},
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{0x71, 0x08},
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{0x71, 0x10},
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{0x71, 0x20},
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{0x71, 0x40},
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{0x71, 0x80},
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{0x70, 0x01},
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{0x70, 0x02},
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{0x70, 0x04},
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{0x70, 0x08},
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{0x70, 0x10},
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{0x70, 0x20},
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{0x70, 0x40},
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{0x70, 0x80},
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{0x71, 0x01},
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{0x71, 0x02},
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{0x71, 0x04},
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{0x71, 0x08},
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{0x71, 0x10},
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{0x71, 0x20},
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{0x71, 0x40},
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{0x71, 0x80}
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};
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unsigned char qsfp_present_regs[33][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0x80, 0x01},
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{0x80, 0x02},
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{0x80, 0x04},
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{0x80, 0x08},
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{0x80, 0x10},
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{0x80, 0x20},
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{0x80, 0x40},
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{0x80, 0x80},
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{0x81, 0x01},
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{0x81, 0x02},
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{0x81, 0x04},
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{0x81, 0x08},
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{0x81, 0x10},
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{0x81, 0x20},
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{0x81, 0x40},
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{0x81, 0x80},
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{0x80, 0x01},
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{0x80, 0x02},
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{0x80, 0x04},
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{0x80, 0x08},
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{0x80, 0x10},
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{0x80, 0x20},
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{0x80, 0x40},
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{0x80, 0x80},
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{0x81, 0x01},
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{0x81, 0x02},
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{0x81, 0x04},
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{0x81, 0x08},
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{0x81, 0x10},
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{0x81, 0x20},
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{0x81, 0x40},
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{0x81, 0x80}
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};
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unsigned char qsfp_int_regs[33][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0x90, 0x01},
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{0x90, 0x02},
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{0x90, 0x04},
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{0x90, 0x08},
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{0x90, 0x10},
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{0x90, 0x20},
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{0x90, 0x40},
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{0x90, 0x80},
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{0x91, 0x01},
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{0x91, 0x02},
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{0x91, 0x04},
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{0x91, 0x08},
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{0x91, 0x10},
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{0x91, 0x20},
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{0x91, 0x40},
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{0x91, 0x80},
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{0x90, 0x01},
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{0x90, 0x02},
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{0x90, 0x04},
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{0x90, 0x08},
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{0x90, 0x10},
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{0x90, 0x20},
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{0x90, 0x40},
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{0x90, 0x80},
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{0x91, 0x01},
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{0x91, 0x02},
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{0x91, 0x04},
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{0x91, 0x08},
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{0x91, 0x10},
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{0x91, 0x20},
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{0x91, 0x40},
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{0x91, 0x80}
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};
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unsigned char qsfp_quter_int_regs[5][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd0, 0x04},
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{0xd0, 0x08},
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{0xd0, 0x04},
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{0xd0, 0x08}
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};
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unsigned char qsfp_quter_int_mask_regs[5][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd1, 0x04},
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{0xd1, 0x08},
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{0xd1, 0x04},
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{0xd1, 0x08}
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};
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unsigned char qsfp_modprs_int_regs[5][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd0, 0x01},
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{0xd0, 0x02},
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{0xd0, 0x01},
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{0xd0, 0x02}
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};
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unsigned char qsfp_modprs_int_mask_regs[5][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd1, 0x01},
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{0xd1, 0x02},
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{0xd1, 0x01},
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{0xd1, 0x02}
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};
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/* end of register offset define */ |