148 lines
3.3 KiB
C
148 lines
3.3 KiB
C
/* register offset define */
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#define PSU_STAT_REG 0xa0
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#define BMC_PSU_STAT_REG 0xe8
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#define PSU_1_VIN_REG 0xb0
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#define PSU_1_IIN_REG 0xb1
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#define PSU_1_VOUT_REG 0xb2
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#define PSU_1_IOUT_REG 0xb3
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#define PSU_1_TEMP_1_REG 0xb4
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#define PSU_1_FAN_SPEED_REG 0xb5
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#define PSU_1_POUT_REG 0xb6
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#define PSU_1_PIN_REG 0xb7
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#define PSU_1_MFR_MODEL_REG 0xfa
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#define PSU_1_MFR_IOUT_MAX_REG 0xb9
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#define PSU_1_VMODE_REG 0xd8
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#define PSU_2_VIN_REG 0xba
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#define PSU_2_IIN_REG 0xbb
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#define PSU_2_VOUT_REG 0xbc
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#define PSU_2_IOUT_REG 0xbd
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#define PSU_2_TEMP_1_REG 0xbe
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#define PSU_2_FAN_SPEED_REG 0xbf
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#define PSU_2_POUT_REG 0xc0
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#define PSU_2_PIN_REG 0xc1
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#define PSU_2_MFR_MODEL_REG 0x9a
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#define PSU_2_MFR_IOUT_MAX_REG 0xc3
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#define PSU_2_VMODE_REG 0xd9
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#define PSU_3_VIN_REG 0xc4
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#define PSU_3_IIN_REG 0xc5
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#define PSU_3_VOUT_REG 0xc6
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#define PSU_3_IOUT_REG 0xc7
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#define PSU_3_TEMP_1_REG 0xc8
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#define PSU_3_FAN_SPEED_REG 0xc9
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#define PSU_3_POUT_REG 0xca
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#define PSU_3_PIN_REG 0xcb
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#define PSU_3_MFR_MODEL_REG 0x9d
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#define PSU_3_MFR_IOUT_MAX_REG 0xcd
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#define PSU_3_VMODE_REG 0xda
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#define PSU_4_VIN_REG 0xce
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#define PSU_4_IIN_REG 0xcf
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#define PSU_4_VOUT_REG 0xd0
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#define PSU_4_IOUT_REG 0xd1
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#define PSU_4_TEMP_1_REG 0xd2
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#define PSU_4_FAN_SPEED_REG 0xd3
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#define PSU_4_POUT_REG 0xd4
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#define PSU_4_PIN_REG 0xd5
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#define PSU_4_MFR_MODEL_REG 0xd6
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#define PSU_4_MFR_IOUT_MAX_REG 0xd7
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#define PSU_4_VMODE_REG 0xdb
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#define DC_6E_P0_VOUT_REG 0x18
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#define DC_70_P0_VOUT_REG 0x1b
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#define DC_70_P1_VOUT_REG 0xf1
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#define DC_6E_P0_IOUT_REG 0x19
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#define DC_70_P0_IOUT_REG 0x1c
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#define DC_70_P1_IOUT_REG 0xf2
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#define DC_6E_P0_POUT_REG 0x1a
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#define DC_70_P0_POUT_REG 0x1d
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#define DC_70_P1_POUT_REG 0xf3
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u8 dc_11_vout_table [9][2] =
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{
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/* Page0 Page1*/
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{0x00, 0x00},
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{0x30, 0x33},
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{0x40, 0x43},
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{0x50, 0x53},
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{0x60, 0x63},
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{0x70, 0x73},
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{0x80, 0x83},
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{0x90, 0x93},
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{0xa0, 0xa3},
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};
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u8 dc_12_vout_table [9][2] =
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{
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/* Page0 Page1*/
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{0x00, 0x00},
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{0x36, 0x3f},
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{0x46, 0x5f},
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{0x56, 0x7f},
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{0x66, 0x9f},
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{0x76, 0xdd},
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{0x86, 0x0d},
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{0x96, 0xf8},
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{0xa6, 0xfc},
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};
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u8 dc_13_vout_table [9][2] =
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{
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/* Page0 Page1*/
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{0x00, 0x00},
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{0x38, 0x3b},
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{0x48, 0x4b},
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{0x58, 0x5b},
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{0x68, 0x6b},
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{0x78, 0x7b},
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{0x88, 0x8b},
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{0x98, 0x9b},
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{0xa8, 0xab},
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};
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u8 dc_11_iout_table [9][2] =
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{
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/* Page0 Page1*/
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{0x00, 0x00},
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{0x31, 0x34},
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{0x41, 0x44},
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{0x51, 0x54},
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{0x61, 0x64},
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{0x71, 0x74},
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{0x81, 0x84},
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{0x91, 0x94},
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{0xa1, 0xa4},
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};
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u8 dc_12_iout_table [9][2] =
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{
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/* Page0 Page1*/
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{0x00, 0x00},
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{0x37, 0x4e},
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{0x47, 0x6e},
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{0x57, 0x8e},
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{0x67, 0xae},
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{0x77, 0xde},
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{0x87, 0x0e},
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{0x97, 0xf9},
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{0xa7, 0xfd},
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};
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u8 dc_13_iout_table [9][2] =
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{
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/* Page0 Page1*/
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{0x00, 0x00},
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{0x39, 0x3c},
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{0x49, 0x4c},
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{0x59, 0x5c},
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{0x69, 0x6c},
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{0x79, 0x7c},
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{0x89, 0x8c},
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{0x99, 0x9c},
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{0xa9, 0xac},
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};
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/* end of register offset define */ |