63de341dd6
* Add switch ASIC vendor and platforms for Nephos - What I did Add switch ASIC vendor: Nephos Add Nephos platforms: Ingrasys S9130-32X, Ingrasys S9230-64X - How I did it Add platform/nephos files Add platform/nephos/sonic-platform-modules-ingrasys submodule Add device/ingrasys/x86_64-ingrasys_s9130_32x-r0 files Add device/ingrasys/x86_64-ingrasys_s9230_64x-r0 files Add SONiC to support Nephos platform - How to verify it To build SONiC installer image and docker images, run the following commands: make configure PLATFORM=nephos make target/sonic-nephos.bin Check system and network feature is worked as well - Description for the changelog Add switch ASIC vendor and platforms for Nephos - A picture of a cute animal (not mandatory but encouraged) Signed-off-by: Sam Yang <yang.kaiyu@gmail.com> * Advance sonic-sairedis submodule to include #271 (Add Nephos ASIC)
294 lines
8.0 KiB
Python
294 lines
8.0 KiB
Python
# sfputil.py
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#
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# Platform-specific SFP transceiver interface for SONiC
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#
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try:
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import time
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from sonic_sfp.sfputilbase import SfpUtilBase
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except ImportError as e:
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raise ImportError("%s - required module not found" % str(e))
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class SfpUtil(SfpUtilBase):
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"""Platform-specific SfpUtil class"""
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PORT_START = 0
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PORT_END = 63
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PORTS_IN_BLOCK = 64
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#TODO: modify according to port map
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EEPROM_OFFSET = 33
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CPLD1_PORTS = 12
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CPLDx_PORTS = 13
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CPLD_OFFSET = 1
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CPLD_PRES_BIT = 1
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CPLD_RESET_BIT = 0
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CPLD_LPMOD_BIT = 2
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CPLDx_I2C_ADDR = "33"
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CPLD_PORT_STATUS_KEY = "cpld_qsfp_port_status"
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CPLD_PORT_CONFIG_KEY = "cpld_qsfp_port_config"
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CPLD_REG_PATH = "/sys/bus/i2c/devices/{0}-00{1}/{2}_{3}"
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_port_to_eeprom_mapping = {}
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_logic_to_phy_port_mapping = {
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0: 0,
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1: 1,
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2: 4,
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3: 5,
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4: 8,
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5: 9,
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6: 12,
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7: 13,
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8: 16,
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9: 17,
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10: 20,
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11: 21,
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12: 24,
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13: 25,
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14: 28,
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15: 29,
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16: 32,
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17: 33,
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18: 36,
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19: 37,
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20: 40,
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21: 41,
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22: 44,
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23: 45,
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24: 48,
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25: 49,
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26: 52,
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27: 53,
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28: 56,
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29: 57,
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30: 60,
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31: 61,
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32: 2,
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33: 3,
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34: 6,
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35: 7,
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36: 10,
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37: 11,
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38: 14,
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39: 15,
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40: 18,
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41: 19,
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42: 22,
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43: 23,
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44: 26,
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45: 27,
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46: 30,
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47: 31,
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48: 34,
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49: 35,
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50: 38,
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51: 39,
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52: 42,
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53: 43,
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54: 46,
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55: 47,
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56: 50,
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57: 51,
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58: 54,
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59: 55,
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60: 58,
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61: 59,
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62: 62,
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63: 63
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}
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@property
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def port_start(self):
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return self.PORT_START
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@property
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def port_end(self):
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return self.PORT_END
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@property
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def qsfp_ports(self):
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return range(0, self.PORTS_IN_BLOCK + 1)
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@property
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def port_to_eeprom_mapping(self):
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return self._port_to_eeprom_mapping
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def __init__(self):
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# Override port_to_eeprom_mapping for class initialization
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eeprom_path = "/sys/class/i2c-adapter/i2c-{0}/{0}-0050/eeprom"
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for x in range(self.port_start, self.port_end + 1):
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phy_port = self._logic_to_phy_port_mapping[x]
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port_eeprom_path = eeprom_path.format(phy_port + self.EEPROM_OFFSET)
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self.port_to_eeprom_mapping[x] = port_eeprom_path
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SfpUtilBase.__init__(self)
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def qsfp_to_cpld_index(self, port_num):
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if port_num < self.CPLD1_PORTS:
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cpld_id = 0
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cpld_port_index = port_num + 1
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else:
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cpld_id = 1 + (port_num - self.CPLD1_PORTS) / self.CPLDx_PORTS
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cpld_port_index = ((port_num - self.CPLD1_PORTS) % self.CPLDx_PORTS) + 1
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return cpld_id, cpld_port_index
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def get_presence(self, port_num):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# logic port to physical port mapping
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port_num = self._logic_to_phy_port_mapping[port_num]
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cpld_id, cpld_port_index = self.qsfp_to_cpld_index(port_num)
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i2c_id = self.CPLD_OFFSET + cpld_id
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reg_path = self.CPLD_REG_PATH.format(i2c_id, self.CPLDx_I2C_ADDR, \
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self.CPLD_PORT_STATUS_KEY, cpld_port_index)
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try:
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reg_file = open(reg_path)
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except IOError as e:
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print "Error: unable to open file: %s" % str(e)
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return False
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# content is a string containing the status register value
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content = reg_file.readline().rstrip()
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reg_file.close()
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reg_value = int(content, 16)
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# mask for presence bit (bit 1)
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mask = (1 << self.CPLD_PRES_BIT)
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# 0 - presence, 1 - absence
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if reg_value & mask == 0:
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return True
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return False
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def get_low_power_mode(self, port_num):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# logic port to physical port mapping
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port_num = self._logic_to_phy_port_mapping[port_num]
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cpld_id, cpld_port_index = self.qsfp_to_cpld_index(port_num)
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i2c_id = self.CPLD_OFFSET + cpld_id
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reg_path = self.CPLD_REG_PATH.format(i2c_id, self.CPLDx_I2C_ADDR, \
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self.CPLD_PORT_CONFIG_KEY, cpld_port_index)
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try:
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reg_file = open(reg_path)
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except IOError as e:
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print "Error: unable to open file: %s" % str(e)
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return False
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# content is a string containing the status register value
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content = reg_file.readline().rstrip()
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reg_file.close()
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reg_value = int(content, 16)
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# mask for lp_mod bit (bit 2)
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mask = (1 << self.CPLD_LPMOD_BIT)
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# 0 - disable, 1 - low power mode
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if reg_value & mask == 0:
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return False
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return True
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def set_low_power_mode(self, port_num, lpmode):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# logic port to physical port mapping
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port_num = self._logic_to_phy_port_mapping[port_num]
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cpld_id, cpld_port_index = self.qsfp_to_cpld_index(port_num)
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i2c_id = self.CPLD_OFFSET + cpld_id
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reg_path = self.CPLD_REG_PATH.format(i2c_id, self.CPLDx_I2C_ADDR, \
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self.CPLD_PORT_CONFIG_KEY, cpld_port_index)
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try:
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reg_file = open(reg_path, "r+")
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except IOError as e:
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print "Error: unable to open file: %s" % str(e)
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return False
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# content is a string containing the status register value
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content = reg_file.readline().rstrip()
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reg_value = int(content, 16)
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# mask for lp_mod bit (bit 2)
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mask = (1 << self.CPLD_LPMOD_BIT)
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# 1 - low power mode, 0 - high power mode
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if lpmode is True:
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reg_value = reg_value | mask
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else:
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reg_value = reg_value & ~mask
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# convert value to hex string
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content = hex(reg_value)
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reg_file.seek(0)
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reg_file.write(content)
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reg_file.close()
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return True
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def reset(self, port_num):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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# logic port to physical port mapping
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port_num = self._logic_to_phy_port_mapping[port_num]
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cpld_id, cpld_port_index = self.qsfp_to_cpld_index(port_num)
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i2c_id = self.CPLD_OFFSET + cpld_id
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reg_path = self.CPLD_REG_PATH.format(i2c_id, self.CPLDx_I2C_ADDR, \
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self.CPLD_PORT_CONFIG_KEY, cpld_port_index)
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# reset the port
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try:
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reg_file = open(reg_path, "r+")
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except IOError as e:
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print "Error: unable to open file: %s" % str(e)
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return False
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# content is a string containing the status register value
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content = reg_file.readline().rstrip()
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reg_value = int(content, 16)
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# mask for reset bit (bit 0)
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mask = (1 << self.CPLD_RESET_BIT)
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# 1 - out of reset, 0 - reset
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reg_value = reg_value & ~mask
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reg_file.seek(0)
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reg_file.write(hex(reg_value))
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reg_file.close()
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# Sleep 1 second to reset done
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time.sleep(1)
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# take the port out of reset
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try:
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reg_file = open(reg_path, "w")
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except IOError as e:
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print "Error: unable to open file: %s" % str(e)
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return False
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reg_value = reg_value | mask
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reg_file.seek(0)
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reg_file.write(hex(reg_value))
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reg_file.close()
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return True
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