218 lines
4.6 KiB
C
218 lines
4.6 KiB
C
/* register offset define */
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#define SFP_1_8_TX_ENABLE_REG 0x70
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#define SFP_9_16_TX_ENABLE_REG 0x71
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#define SFP_17_24_TX_ENABLE_REG 0x72
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#define SFP_25_32_TX_ENABLE_REG 0x73
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#define SFP_33_40_TX_ENABLE_REG 0x70
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#define SFP_41_48_TX_ENABLE_REG 0x71
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#define SFP_1_8_RX_LOSS_REG 0x90
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#define SFP_9_16_RX_LOSS_REG 0x91
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#define SFP_17_24_RX_LOSS_REG 0x92
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#define SFP_25_32_RX_LOSS_REG 0x93
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#define SFP_33_40_RX_LOSS_REG 0x90
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#define SFP_41_48_RX_LOSS_REG 0x91
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#define SFP_1_8_PRESENT_REG 0x80
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#define SFP_9_16_PRESENT_REG 0x81
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#define SFP_17_24_PRESENT_REG 0x82
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#define SFP_25_32_PRESENT_REG 0x83
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#define SFP_33_40_PRESENT_REG 0x80
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#define SFP_41_48_PRESENT_REG 0x81
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unsigned char sfp_tx_enable_regs[49][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0x70, 0x01},
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{0x70, 0x02},
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{0x70, 0x04},
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{0x70, 0x08},
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{0x70, 0x10},
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{0x70, 0x20},
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{0x70, 0x40},
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{0x70, 0x80},
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{0x71, 0x01},
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{0x71, 0x02},
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{0x71, 0x04},
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{0x71, 0x08},
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{0x71, 0x10},
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{0x71, 0x20},
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{0x71, 0x40},
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{0x71, 0x80},
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{0x72, 0x01},
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{0x72, 0x02},
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{0x72, 0x04},
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{0x72, 0x08},
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{0x72, 0x10},
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{0x72, 0x20},
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{0x72, 0x40},
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{0x72, 0x80},
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{0x73, 0x01},
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{0x73, 0x02},
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{0x73, 0x04},
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{0x73, 0x08},
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{0x73, 0x10},
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{0x73, 0x20},
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{0x73, 0x40},
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{0x73, 0x80},
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{0x70, 0x01},
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{0x70, 0x02},
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{0x70, 0x04},
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{0x70, 0x08},
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{0x70, 0x10},
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{0x70, 0x20},
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{0x70, 0x40},
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{0x70, 0x80},
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{0x71, 0x01},
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{0x71, 0x02},
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{0x71, 0x04},
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{0x71, 0x08},
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{0x71, 0x10},
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{0x71, 0x20},
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{0x71, 0x40},
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{0x71, 0x80}
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};
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unsigned char sfp_rx_loss[49][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0x90, 0x01},
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{0x90, 0x02},
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{0x90, 0x04},
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{0x90, 0x08},
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{0x90, 0x10},
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{0x90, 0x20},
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{0x90, 0x40},
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{0x90, 0x80},
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{0x91, 0x01},
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{0x91, 0x02},
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{0x91, 0x04},
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{0x91, 0x08},
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{0x91, 0x10},
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{0x91, 0x20},
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{0x91, 0x40},
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{0x91, 0x80},
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{0x92, 0x01},
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{0x92, 0x02},
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{0x92, 0x04},
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{0x92, 0x08},
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{0x92, 0x10},
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{0x92, 0x20},
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{0x92, 0x40},
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{0x92, 0x80},
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{0x93, 0x01},
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{0x93, 0x02},
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{0x93, 0x04},
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{0x93, 0x08},
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{0x93, 0x10},
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{0x93, 0x20},
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{0x93, 0x40},
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{0x93, 0x80},
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{0x90, 0x01},
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{0x90, 0x02},
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{0x90, 0x04},
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{0x90, 0x08},
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{0x90, 0x10},
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{0x90, 0x20},
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{0x90, 0x40},
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{0x90, 0x80},
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{0x91, 0x01},
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{0x91, 0x02},
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{0x91, 0x04},
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{0x91, 0x08},
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{0x91, 0x10},
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{0x91, 0x20},
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{0x91, 0x40},
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{0x91, 0x80}
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};
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unsigned char sfp_present_regs[49][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0x80, 0x01},
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{0x80, 0x02},
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{0x80, 0x04},
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{0x80, 0x08},
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{0x80, 0x10},
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{0x80, 0x20},
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{0x80, 0x40},
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{0x80, 0x80},
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{0x81, 0x01},
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{0x81, 0x02},
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{0x81, 0x04},
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{0x81, 0x08},
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{0x81, 0x10},
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{0x81, 0x20},
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{0x81, 0x40},
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{0x81, 0x80},
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{0x82, 0x01},
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{0x82, 0x02},
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{0x82, 0x04},
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{0x82, 0x08},
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{0x82, 0x10},
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{0x82, 0x20},
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{0x82, 0x40},
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{0x82, 0x80},
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{0x83, 0x01},
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{0x83, 0x02},
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{0x83, 0x04},
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{0x83, 0x08},
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{0x83, 0x10},
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{0x83, 0x20},
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{0x83, 0x40},
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{0x83, 0x80},
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{0x80, 0x01},
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{0x80, 0x02},
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{0x80, 0x04},
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{0x80, 0x08},
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{0x80, 0x10},
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{0x80, 0x20},
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{0x80, 0x40},
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{0x80, 0x80},
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{0x81, 0x01},
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{0x81, 0x02},
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{0x81, 0x04},
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{0x81, 0x08},
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{0x81, 0x10},
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{0x81, 0x20},
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{0x81, 0x40},
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{0x81, 0x80}
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};
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unsigned char sfp_rx_loss_int_regs[7][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd0, 0x10}, //1-8
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{0xd0, 0x20}, //9-16
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{0xd0, 0x40}, //17-24
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{0xd0, 0x80}, //25-32
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{0xd0, 0x08}, //33-40
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{0xd0, 0x10} //41-48
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};
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unsigned char sfp_present_int_regs[7][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd0, 0x01}, //1-8
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{0xd0, 0x02}, //9-16
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{0xd0, 0x04}, //17-24
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{0xd0, 0x08}, //25-32
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{0xd0, 0x01}, //33-40
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{0xd0, 0x02} //41-48
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};
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unsigned char sfp_rx_loss_int_mask_regs[7][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd1, 0x10}, //1-8
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{0xd1, 0x20}, //9-16
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{0xd1, 0x40}, //17-24
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{0xd1, 0x80}, //25-32
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{0xd1, 0x08}, //33-40
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{0xd1, 0x10} //41-48
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};
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unsigned char sfp_present_int_mask_regs[7][2] = {
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{0x00, 0x00}, //cpld offset, bit mask
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{0xd1, 0x01}, //1-8
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{0xd1, 0x02}, //9-16
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{0xd1, 0x04}, //17-24
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{0xd1, 0x08}, //25-32
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{0xd1, 0x01}, //33-40
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{0xd1, 0x02} //41-48
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};
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/* end of register offset define */ |