04b9ce8e32
Manual verification on switch (TH3 device) admin@str2-xxxxx-01:~$ bcmcmd bsv bsv BRCM SAI ver: [6.0.0.10], OCP SAI ver: [1.9.1], SDK ver: [sdk-6.5.23] drivshell> admin@str2-xxxxx-01:~$ bcmcmd version version Broadcom Command Monitor: Copyright (c) 1998-2021 Broadcom Release: sdk-6.5.23 built 20211020 (Wed Oct 20 06:52:58 2021) From root@fedbbfdbee81:/__w/2/s/output/x86-xgsall-deb/hsdk Platform: X86 OS: Unix (Posix) Chips: BCM56640_A0, BCM56850_A0, BCM56340_A0, BCM56960_A0, BCM56860_A0, BCM56970_A0, BCM56870_A0, BCM56980_A0, BCM56980_B0, BCM56370_A0, BCM56275_A0, BCM56770_A0, Chips: BCM56780_A0, BCM56782_A0, BCM56784_A0, BCM56785_A0, BCM56786_A0, BCM56787_A0, BCM56788_A0, BCM56789_A0, BCM56880_A0, BCM56880_B0, BCM56881_A0, BCM56881_B0, BCM56883_A0, BCM56883_B0, BCM56990_A0, BCM56990_B0, BCM56991_B0, BCM56992_B0, BCM56996_A0, BCM56996_B0, BCM56997_A0, BCM56997_B0 Variant drivers: BCM56780_A0_CNA_1_2_10, BCM56780_A0_DNA_2_7_6_0, BCM56880_A0_CNA_1_2_9, BCM56880_A0_DNA_4_9_5_0 PHYs: BCM5400, BCM54182, BCM54185, BCM54180, BCM54140, BCM54192, BCM54195, BCM54190, BCM54194, BCM54210, BCM54220, BCM54280, BCM54282, BCM54240, BCM54285, BCM5428X, BCM54290, BCM54292, BCM54294, BCM54295, BCM54296, BCM56160-GPHY, BCM53540-GPHY, BCM56275-GPHY, BCM8750, BCM8752, BCM8754, BCM84740, BCM84164, BCM84758, BCM84780, BCM84784, BCM84318, BCM84328, Sesto, BCM82780, copper sfp drivshell>
301 lines
7.8 KiB
C
301 lines
7.8 KiB
C
/*! \file ngbde_main.c
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*
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* NGBDE module entry.
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*
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*/
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/*
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* $Copyright: Copyright 2018-2021 Broadcom. All rights reserved.
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* The term 'Broadcom' refers to Broadcom Inc. and/or its subsidiaries.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* A copy of the GNU General Public License version 2 (GPLv2) can
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* be found in the LICENSES folder.$
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*/
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#include <ngbde.h>
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/*! \cond */
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MODULE_AUTHOR("Broadcom Corporation");
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MODULE_DESCRIPTION("NG BDE Module");
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MODULE_LICENSE("GPL");
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/*! \endcond */
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/*! \cond */
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static int mmap_debug = 0;
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module_param(mmap_debug, int, 0);
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MODULE_PARM_DESC(mmap_debug,
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"MMAP debug output enable (default 0).");
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/*! \endcond */
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/*!
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* \brief Remap user space DMA memory to non-cached area.
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*
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* Since we cannot flush and invalidate DMA memory from user space,
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* the DMA memory pools need to be cache-coherent, even if this means
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* that we need to remap the DMA memory as non-cached.
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*
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* If undefined, we set this value according to kernel configuration.
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*/
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#ifndef REMAP_DMA_NONCACHED
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# ifdef CONFIG_DMA_NONCOHERENT
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# define REMAP_DMA_NONCACHED 1
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# else
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# define REMAP_DMA_NONCACHED 0
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# endif
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#endif
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static int
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ngbde_open(struct inode *inode, struct file *filp)
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{
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return 0;
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}
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static int
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ngbde_release(struct inode *inode, struct file *filp)
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{
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return 0;
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}
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/*!
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* \brief Check if memory range is within existing DMA memory pools.
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*
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* \param [in] paddr Physical start address of memory range.
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* \param [in] size Size of memory range.
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*
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* \retval true Range is valid.
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* \retval false Range is not valid.
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*/
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static bool
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ngbde_dma_range_valid(unsigned long paddr, unsigned long size)
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{
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struct ngbde_dev_s *swdev;
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unsigned int num_swdev, idx;
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struct ngbde_dmamem_s *dmamem;
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unsigned int pool;
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ngbde_swdev_get_all(&swdev, &num_swdev);
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for (idx = 0; idx < num_swdev; idx++) {
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for (pool = 0; pool < NGBDE_NUM_DMAPOOL_MAX; pool++) {
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dmamem = &swdev[idx].dmapool[pool].dmamem;
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if (paddr >= dmamem->paddr &&
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(paddr + size) <= (dmamem->paddr + dmamem->size)) {
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return true;
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}
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}
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}
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return false;
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}
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/*!
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* \brief Check if memory range is within device I/O ranges.
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*
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* \param [in] paddr Physical start address of I/O memory range.
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* \param [in] size Size of memory range.
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*
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* \retval true Range is valid.
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* \retval false Range is not valid.
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*/
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static bool
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ngbde_pio_range_valid(unsigned long paddr, unsigned long size)
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{
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struct ngbde_dev_s *swdev;
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unsigned int num_swdev, idx;
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struct ngbde_memwin_s *iowin;
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unsigned long iowin_size;
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unsigned int wdx;
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ngbde_swdev_get_all(&swdev, &num_swdev);
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for (idx = 0; idx < num_swdev; idx++) {
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for (wdx = 0; wdx < NGBDE_NUM_IOWIN_MAX; wdx++) {
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iowin = &swdev[idx].iowin[wdx];
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iowin_size = iowin->size;
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if (iowin_size < PAGE_SIZE) {
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iowin_size = PAGE_SIZE;
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}
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if (mmap_debug) {
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printk("MMAP: Check 0x%08lx/0x%08lx against "
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"0x%08lx/0x%08lx(0x%08lx)\n",
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paddr, size,
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(unsigned long)iowin->addr,
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(unsigned long)iowin->size, iowin_size);
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}
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if (paddr >= iowin->addr &&
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(paddr + size) <= (iowin->addr + iowin_size)) {
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return true;
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}
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}
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}
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return false;
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}
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/*!
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* \brief Match incomplete address with device base addresses.
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*
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* Use for physical addresses larger than 44 bits.
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*
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* \param [in] paddr Physical address from user space.
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*
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* \return Matched device base addess or 0 if no match.
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*/
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static unsigned long
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ngbde_pio_base_match(unsigned long paddr)
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{
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struct ngbde_dev_s *swdev;
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unsigned int num_swdev, idx;
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struct ngbde_memwin_s *iowin;
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unsigned int wdx;
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ngbde_swdev_get_all(&swdev, &num_swdev);
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for (idx = 0; idx < num_swdev; idx++) {
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for (wdx = 0; wdx < NGBDE_NUM_IOWIN_MAX; wdx++) {
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iowin = &swdev[idx].iowin[wdx];
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if (((paddr ^ iowin->addr) & 0xfffffffffffULL) == 0) {
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if (mmap_debug) {
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printk("MMAP: Matched 0x%08lx to 0x%08lx\n",
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(unsigned long)paddr,
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(unsigned long)iowin->addr);
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}
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return iowin->addr;
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}
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}
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}
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return 0;
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}
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/*
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* Some kernels are configured to prevent mapping of kernel RAM memory
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* into user space via the /dev/mem device.
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*
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* The function below provides a backdoor to mapping the DMA pool to
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* user space via the BDE device file.
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*/
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static int
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ngbde_mmap(struct file *filp, struct vm_area_struct *vma)
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{
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unsigned long paddr = vma->vm_pgoff << PAGE_SHIFT;
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unsigned long size = vma->vm_end - vma->vm_start;
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int map_noncached = REMAP_DMA_NONCACHED;
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int range_valid = 0;
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if (mmap_debug) {
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printk("MMAP: Mapping %lu Kbytes at 0x%08lx (0x%lx)\n",
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size / 1024, paddr, vma->vm_pgoff);
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}
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if (ngbde_dma_range_valid(paddr, size)) {
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range_valid = 1;
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} else {
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map_noncached = 1;
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if (ngbde_pio_range_valid(paddr, size)) {
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range_valid = 1;
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} else {
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paddr = ngbde_pio_base_match(paddr);
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if (ngbde_pio_range_valid(paddr, size)) {
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range_valid = 1;
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}
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}
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}
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if (!range_valid) {
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printk("BDE: Invalid mmap range 0x%08lx/0x%lx\n", paddr, size);
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return -EINVAL;
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}
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if (map_noncached) {
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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}
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if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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size, vma->vm_page_prot)) {
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printk("BDE: Failed to mmap phys range 0x%lx-0x%lx to 0x%lx-0x%lx\n",
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paddr, paddr + size, vma->vm_start, vma->vm_end);
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return -EAGAIN;
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}
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return 0;
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}
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static struct file_operations fops = {
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.open = ngbde_open,
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.release = ngbde_release,
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.unlocked_ioctl = ngbde_ioctl,
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.compat_ioctl = ngbde_ioctl,
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.mmap = ngbde_mmap,
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};
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/*!
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* \brief Standard module cleanup.
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*
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* \return Nothing.
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*/
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void __exit
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ngbde_exit_module(void)
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{
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ngbde_intr_cleanup();
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ngbde_iio_cleanup();
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ngbde_paxb_cleanup();
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ngbde_pio_cleanup();
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ngbde_dma_cleanup();
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ngbde_procfs_cleanup();
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unregister_chrdev(MOD_MAJOR, MOD_NAME);
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ngbde_pci_cleanup();
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ngbde_iproc_cleanup();
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printk(KERN_INFO "Broadcom NGBDE unloaded successfully\n");
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}
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/*!
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* \brief Standard module initialization.
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*
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* \return Nothing.
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*/
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int __init
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ngbde_init_module(void)
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{
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int rv;
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rv = register_chrdev(MOD_MAJOR, MOD_NAME, &fops);
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if (rv < 0) {
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printk(KERN_WARNING "%s: can't get major %d\n",
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MOD_NAME, MOD_MAJOR);
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return rv;
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}
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rv = ngbde_iproc_probe();
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if (rv < 0) {
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printk(KERN_WARNING "%s: Error probing for AXI bus devices.\n",
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MOD_NAME);
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return rv;
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}
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rv = ngbde_pci_probe();
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if (rv < 0) {
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printk(KERN_WARNING "%s: Error probing for PCI bus devices.\n",
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MOD_NAME);
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return rv;
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}
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rv = ngbde_procfs_init();
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if (rv < 0) {
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printk(KERN_WARNING "%s: Unable to initialize proc files\n",
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MOD_NAME);
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return rv;
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}
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printk(KERN_INFO "Broadcom NGBDE loaded successfully\n");
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return 0;
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}
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module_exit(ngbde_exit_module);
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module_init(ngbde_init_module);
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