7b33538686
The sai profile itself can support 32x50G+16x100G/40G while the initial port_config.ini uses 40G speeds for port 17-32. Signed-off-by: Zhenggen Xu <zxu@linkedin.com>
500 lines
9.5 KiB
Plaintext
500 lines
9.5 KiB
Plaintext
# Define default OS / SAL
|
|
os=unix
|
|
|
|
# all XPORTs to XE ports
|
|
#pbmp_xport_xe=0x1fffffffe
|
|
pbmp_xport_xe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
|
|
pbmp_oversubscribe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
|
|
|
|
# Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or
|
|
# L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification.
|
|
l2xmsg_mode=1
|
|
|
|
# Memory table size configs, enable ALPM
|
|
l2_mem_entries=8192
|
|
l3_mem_entries=8192
|
|
l3_alpm_enable=2
|
|
ipv6_lpm_128b_enable=1
|
|
|
|
#Use MMU lossy configuration
|
|
mmu_lossless=0
|
|
|
|
###################################################################################
|
|
# SeaStone customized configuration
|
|
###################################################################################
|
|
|
|
#ext mdio frequency to 495/0x80/2(1.933Mhz) or 415/0x80/2(1.62MHz)
|
|
# default is 40
|
|
# Set external MDIO freq to 6.19MHz (495MHz) or 5.19MHz (415MHz)
|
|
#* target_freq is core_clock_freq * DIVIDEND / DIVISOR / 2
|
|
#
|
|
rate_ext_mdio_divisor=0x80
|
|
|
|
# use internal rom boot
|
|
phy_ext_rom_boot=0
|
|
|
|
oversubscribe_mode=1
|
|
|
|
# Map the physical ports to logical ports
|
|
dport_map_enable=1
|
|
|
|
dport_map_port_68=1
|
|
dport_map_port_69=2
|
|
|
|
dport_map_port_72=5
|
|
dport_map_port_73=6
|
|
|
|
dport_map_port_76=9
|
|
dport_map_port_77=10
|
|
|
|
dport_map_port_80=13
|
|
dport_map_port_81=14
|
|
|
|
dport_map_port_34=17
|
|
dport_map_port_35=18
|
|
|
|
dport_map_port_38=21
|
|
dport_map_port_39=22
|
|
|
|
dport_map_port_42=25
|
|
dport_map_port_43=26
|
|
|
|
dport_map_port_46=29
|
|
dport_map_port_47=30
|
|
|
|
dport_map_port_50=33
|
|
dport_map_port_51=34
|
|
|
|
dport_map_port_54=37
|
|
dport_map_port_55=38
|
|
|
|
dport_map_port_58=41
|
|
dport_map_port_59=42
|
|
|
|
dport_map_port_62=45
|
|
dport_map_port_63=46
|
|
|
|
dport_map_port_84=49
|
|
dport_map_port_85=50
|
|
|
|
dport_map_port_88=53
|
|
dport_map_port_89=54
|
|
|
|
dport_map_port_92=57
|
|
dport_map_port_93=58
|
|
|
|
dport_map_port_96=61
|
|
dport_map_port_97=62
|
|
|
|
# 100G/40G ports
|
|
dport_map_port_102=65
|
|
dport_map_port_106=69
|
|
dport_map_port_110=73
|
|
dport_map_port_114=77
|
|
dport_map_port_1=81
|
|
dport_map_port_5=85
|
|
dport_map_port_9=89
|
|
dport_map_port_13=93
|
|
dport_map_port_17=97
|
|
dport_map_port_21=101
|
|
dport_map_port_25=105
|
|
dport_map_port_29=109
|
|
dport_map_port_118=113
|
|
dport_map_port_122=117
|
|
dport_map_port_126=121
|
|
dport_map_port_130=125
|
|
|
|
|
|
# port/lane mapping, 32x50G + 16x100G
|
|
portmap_68=65:50:2
|
|
portmap_69=67:50:2
|
|
|
|
portmap_72=69:50:2
|
|
portmap_73=71:50:2
|
|
|
|
portmap_76=73:50:2
|
|
portmap_77=75:50:2
|
|
|
|
portmap_80=77:50:2
|
|
portmap_81=79:50:2
|
|
|
|
portmap_34=33:50:2
|
|
portmap_35=35:50:2
|
|
|
|
portmap_38=37:50:2
|
|
portmap_39=39:50:2
|
|
|
|
portmap_42=41:50:2
|
|
portmap_43=43:50:2
|
|
|
|
portmap_46=45:50:2
|
|
portmap_47=47:50:2
|
|
|
|
portmap_50=49:50:2
|
|
portmap_51=51:50:2
|
|
|
|
portmap_54=53:50:2
|
|
portmap_55=55:50:2
|
|
|
|
portmap_58=57:50:2
|
|
portmap_59=59:50:2
|
|
|
|
portmap_62=61:50:2
|
|
portmap_63=63:50:2
|
|
|
|
portmap_84=81:50:2
|
|
portmap_85=83:50:2
|
|
|
|
portmap_88=85:50:2
|
|
portmap_89=87:50:2
|
|
|
|
portmap_92=89:50:2
|
|
portmap_93=91:50:2
|
|
|
|
portmap_96=93:50:2
|
|
portmap_97=95:50:2
|
|
|
|
portmap_102=97:100:4
|
|
portmap_106=101:100:4
|
|
portmap_110=105:100:4
|
|
portmap_114=109:100:4
|
|
portmap_1=1:100:4
|
|
portmap_5=5:100:4
|
|
portmap_9=9:100:4
|
|
portmap_13=13:100:4
|
|
portmap_17=17:100:4
|
|
portmap_21=21:100:4
|
|
portmap_25=25:100:4
|
|
portmap_29=29:100:4
|
|
portmap_118=113:100:4
|
|
portmap_122=117:100:4
|
|
portmap_126=121:100:4
|
|
portmap_130=125:100:4
|
|
|
|
|
|
#WC16
|
|
xgxs_tx_lane_map_68=0x3201
|
|
xgxs_rx_lane_map_68=0x2310
|
|
xgxs_tx_lane_map_69=0x3201
|
|
xgxs_rx_lane_map_69=0x2310
|
|
|
|
|
|
#WC17
|
|
xgxs_tx_lane_map_72=0x3201
|
|
xgxs_rx_lane_map_72=0x2301
|
|
xgxs_tx_lane_map_73=0x3201
|
|
xgxs_rx_lane_map_73=0x2301
|
|
|
|
#WC18
|
|
xgxs_tx_lane_map_76=0x0132
|
|
xgxs_rx_lane_map_76=0x0123
|
|
xgxs_tx_lane_map_77=0x0132
|
|
xgxs_rx_lane_map_77=0x0123
|
|
|
|
#WC19
|
|
xgxs_tx_lane_map_80=0x2031
|
|
xgxs_rx_lane_map_80=0x1320
|
|
xgxs_tx_lane_map_81=0x2031
|
|
xgxs_rx_lane_map_81=0x1320
|
|
|
|
#WC8
|
|
xgxs_tx_lane_map_34=0x3021
|
|
xgxs_rx_lane_map_34=0x0213
|
|
xgxs_tx_lane_map_35=0x3021
|
|
xgxs_rx_lane_map_35=0x0213
|
|
|
|
#WC9
|
|
xgxs_tx_lane_map_38=0x3210
|
|
xgxs_rx_lane_map_38=0x1023
|
|
xgxs_tx_lane_map_39=0x3210
|
|
xgxs_rx_lane_map_39=0x1023
|
|
|
|
#WC10
|
|
xgxs_tx_lane_map_42=0x2310
|
|
xgxs_rx_lane_map_42=0x3210
|
|
xgxs_tx_lane_map_43=0x2310
|
|
xgxs_rx_lane_map_43=0x3210
|
|
|
|
#WC11
|
|
xgxs_tx_lane_map_46=0x1032
|
|
xgxs_rx_lane_map_46=0x1302
|
|
xgxs_tx_lane_map_47=0x1032
|
|
xgxs_rx_lane_map_47=0x1302
|
|
|
|
#WC12
|
|
xgxs_tx_lane_map_50=0x3201
|
|
xgxs_rx_lane_map_50=0x0213
|
|
xgxs_tx_lane_map_51=0x3201
|
|
xgxs_rx_lane_map_51=0x0213
|
|
|
|
|
|
#WC13
|
|
xgxs_tx_lane_map_54=0x2301
|
|
xgxs_rx_lane_map_54=0x2310
|
|
xgxs_tx_lane_map_55=0x2301
|
|
xgxs_rx_lane_map_55=0x2310
|
|
|
|
#WC14
|
|
xgxs_tx_lane_map_58=0x3201
|
|
xgxs_rx_lane_map_58=0x0213
|
|
xgxs_tx_lane_map_59=0x3201
|
|
xgxs_rx_lane_map_59=0x0213
|
|
|
|
#WC15
|
|
xgxs_tx_lane_map_62=0x1302
|
|
xgxs_rx_lane_map_62=0x2310
|
|
xgxs_tx_lane_map_63=0x1302
|
|
xgxs_rx_lane_map_63=0x2310
|
|
|
|
#WC20
|
|
xgxs_tx_lane_map_84=0x0213
|
|
xgxs_rx_lane_map_84=0x2301
|
|
xgxs_tx_lane_map_85=0x0213
|
|
xgxs_rx_lane_map_85=0x2301
|
|
|
|
#WC21
|
|
xgxs_tx_lane_map_88=0x0132
|
|
xgxs_rx_lane_map_88=0x3210
|
|
xgxs_tx_lane_map_89=0x0132
|
|
xgxs_rx_lane_map_89=0x3210
|
|
|
|
#WC22
|
|
xgxs_tx_lane_map_92=0x0132
|
|
xgxs_rx_lane_map_92=0x2031
|
|
xgxs_tx_lane_map_93=0x0132
|
|
xgxs_rx_lane_map_93=0x2031
|
|
|
|
#WC23
|
|
xgxs_tx_lane_map_96=0x2031
|
|
xgxs_rx_lane_map_96=0x3201
|
|
xgxs_tx_lane_map_97=0x2031
|
|
xgxs_rx_lane_map_97=0x3201
|
|
|
|
|
|
#WC24
|
|
xgxs_tx_lane_map_102=0x0132
|
|
xgxs_rx_lane_map_102=0x2301
|
|
|
|
#WC25
|
|
xgxs_tx_lane_map_106=0x0132
|
|
xgxs_rx_lane_map_106=0x3201
|
|
|
|
#WC26
|
|
xgxs_tx_lane_map_110=0x0132
|
|
xgxs_rx_lane_map_110=0x2031
|
|
|
|
#WC27
|
|
xgxs_tx_lane_map_114=0x2031
|
|
xgxs_rx_lane_map_114=0x2301
|
|
|
|
#WC0
|
|
xgxs_tx_lane_map_1=0x3210
|
|
xgxs_rx_lane_map_1=0x3120
|
|
|
|
#WC1
|
|
xgxs_tx_lane_map_5=0x0132
|
|
xgxs_rx_lane_map_5=0x1023
|
|
|
|
#WC2
|
|
xgxs_tx_lane_map_9=0x3201
|
|
xgxs_rx_lane_map_9=0x3120
|
|
|
|
#WC3
|
|
xgxs_tx_lane_map_13=0x2031
|
|
xgxs_rx_lane_map_13=0x1032
|
|
|
|
#WC4
|
|
xgxs_tx_lane_map_17=0x2310
|
|
xgxs_rx_lane_map_17=0x3210
|
|
|
|
#WC5
|
|
xgxs_tx_lane_map_21=0x2301
|
|
xgxs_rx_lane_map_21=0x3120
|
|
|
|
#WC6
|
|
xgxs_tx_lane_map_25=0x3201
|
|
xgxs_rx_lane_map_25=0x0213
|
|
|
|
#WC7
|
|
xgxs_tx_lane_map_29=0x1302
|
|
xgxs_rx_lane_map_29=0x1023
|
|
|
|
#WC28
|
|
xgxs_tx_lane_map_118=0x1320
|
|
xgxs_rx_lane_map_118=0x1302
|
|
|
|
#WC29
|
|
xgxs_tx_lane_map_122=0x1032
|
|
xgxs_rx_lane_map_122=0x1023
|
|
|
|
#WC30
|
|
xgxs_tx_lane_map_126=0x3120
|
|
xgxs_rx_lane_map_126=0x3120
|
|
|
|
#WC31
|
|
xgxs_tx_lane_map_130=0x1302
|
|
xgxs_rx_lane_map_130=0x2310
|
|
|
|
|
|
#Polarity flip settings
|
|
#WC16
|
|
phy_xaui_tx_polarity_flip_68=0x0000
|
|
phy_xaui_rx_polarity_flip_68=0x0000
|
|
phy_xaui_tx_polarity_flip_69=0x0000
|
|
phy_xaui_rx_polarity_flip_69=0x0000
|
|
|
|
#WC17
|
|
phy_xaui_tx_polarity_flip_72=0x0001
|
|
phy_xaui_rx_polarity_flip_72=0x0002
|
|
phy_xaui_tx_polarity_flip_73=0x0003
|
|
phy_xaui_rx_polarity_flip_73=0x0000
|
|
|
|
#WC18
|
|
phy_xaui_tx_polarity_flip_76=0x0003
|
|
phy_xaui_rx_polarity_flip_76=0x0000
|
|
phy_xaui_tx_polarity_flip_77=0x0003
|
|
phy_xaui_rx_polarity_flip_77=0x0000
|
|
|
|
#WC19
|
|
phy_xaui_tx_polarity_flip_80=0x0003
|
|
phy_xaui_rx_polarity_flip_80=0x0003
|
|
phy_xaui_tx_polarity_flip_81=0x0003
|
|
phy_xaui_rx_polarity_flip_81=0x0003
|
|
|
|
#WC8
|
|
phy_xaui_tx_polarity_flip_34=0x0002
|
|
phy_xaui_rx_polarity_flip_34=0x0000
|
|
phy_xaui_tx_polarity_flip_35=0x0003
|
|
phy_xaui_rx_polarity_flip_35=0x0000
|
|
|
|
#WC9
|
|
phy_xaui_tx_polarity_flip_38=0x0000
|
|
phy_xaui_rx_polarity_flip_38=0x0000
|
|
phy_xaui_tx_polarity_flip_39=0x0002
|
|
phy_xaui_rx_polarity_flip_39=0x0000
|
|
|
|
#WC10
|
|
phy_xaui_tx_polarity_flip_42=0x0001
|
|
phy_xaui_rx_polarity_flip_42=0x0000
|
|
phy_xaui_tx_polarity_flip_43=0x0003
|
|
phy_xaui_rx_polarity_flip_43=0x0000
|
|
|
|
#WC11
|
|
phy_xaui_tx_polarity_flip_46=0x0000
|
|
phy_xaui_rx_polarity_flip_46=0x0000
|
|
phy_xaui_tx_polarity_flip_47=0x0000
|
|
phy_xaui_rx_polarity_flip_47=0x0000
|
|
|
|
#WC12
|
|
phy_xaui_tx_polarity_flip_50=0x0002
|
|
phy_xaui_rx_polarity_flip_50=0x0000
|
|
phy_xaui_tx_polarity_flip_51=0x0000
|
|
phy_xaui_rx_polarity_flip_51=0x0000
|
|
|
|
#WC13
|
|
phy_xaui_tx_polarity_flip_54=0x0002
|
|
phy_xaui_rx_polarity_flip_54=0x0000
|
|
phy_xaui_tx_polarity_flip_55=0x0000
|
|
phy_xaui_rx_polarity_flip_55=0x0000
|
|
|
|
#WC14
|
|
phy_xaui_tx_polarity_flip_58=0x0000
|
|
phy_xaui_rx_polarity_flip_58=0x0000
|
|
phy_xaui_tx_polarity_flip_59=0x0000
|
|
phy_xaui_rx_polarity_flip_59=0x0000
|
|
|
|
#WC15
|
|
phy_xaui_tx_polarity_flip_62=0x0002
|
|
phy_xaui_rx_polarity_flip_62=0x0003
|
|
phy_xaui_tx_polarity_flip_63=0x0002
|
|
phy_xaui_rx_polarity_flip_63=0x0003
|
|
|
|
#WC20
|
|
phy_xaui_tx_polarity_flip_84=0x0003
|
|
phy_xaui_rx_polarity_flip_84=0x0002
|
|
phy_xaui_tx_polarity_flip_85=0x0001
|
|
phy_xaui_rx_polarity_flip_85=0x0003
|
|
|
|
#WC21
|
|
phy_xaui_tx_polarity_flip_88=0x0001
|
|
phy_xaui_rx_polarity_flip_88=0x0001
|
|
phy_xaui_tx_polarity_flip_89=0x0003
|
|
phy_xaui_rx_polarity_flip_89=0x0003
|
|
|
|
#WC22
|
|
phy_xaui_tx_polarity_flip_92=0x0003
|
|
phy_xaui_rx_polarity_flip_92=0x0000
|
|
phy_xaui_tx_polarity_flip_93=0x0003
|
|
phy_xaui_rx_polarity_flip_93=0x0002
|
|
|
|
#WC23
|
|
phy_xaui_tx_polarity_flip_96=0x0001
|
|
phy_xaui_rx_polarity_flip_96=0x0000
|
|
phy_xaui_tx_polarity_flip_97=0x0001
|
|
phy_xaui_rx_polarity_flip_97=0x0000
|
|
|
|
#WC24
|
|
phy_xaui_tx_polarity_flip_102=0x0000
|
|
phy_xaui_rx_polarity_flip_102=0x000F
|
|
|
|
#WC25
|
|
phy_xaui_tx_polarity_flip_106=0x000F
|
|
phy_xaui_rx_polarity_flip_106=0x0000
|
|
|
|
#WC26
|
|
phy_xaui_tx_polarity_flip_110=0x000F
|
|
phy_xaui_rx_polarity_flip_110=0x000F
|
|
|
|
#WC27
|
|
phy_xaui_tx_polarity_flip_114=0x000F
|
|
phy_xaui_rx_polarity_flip_114=0x0007
|
|
|
|
#WC0
|
|
phy_xaui_tx_polarity_flip_1=0x0003
|
|
phy_xaui_rx_polarity_flip_1=0x000F
|
|
|
|
#WC1
|
|
phy_xaui_tx_polarity_flip_5=0x0007
|
|
phy_xaui_rx_polarity_flip_5=0x0000
|
|
|
|
#WC2
|
|
phy_xaui_tx_polarity_flip_9=0x0002
|
|
phy_xaui_rx_polarity_flip_9=0x0008
|
|
|
|
#WC3
|
|
phy_xaui_tx_polarity_flip_13=0x000F
|
|
phy_xaui_rx_polarity_flip_13=0x0000
|
|
|
|
#WC4
|
|
phy_xaui_tx_polarity_flip_17=0x0007
|
|
phy_xaui_rx_polarity_flip_17=0x0000
|
|
|
|
#WC5
|
|
phy_xaui_tx_polarity_flip_21=0x0000
|
|
phy_xaui_rx_polarity_flip_21=0x0000
|
|
|
|
#WC6
|
|
phy_xaui_tx_polarity_flip_25=0x0002
|
|
phy_xaui_rx_polarity_flip_25=0x0005
|
|
|
|
#WC7
|
|
phy_xaui_tx_polarity_flip_29=0x0002
|
|
phy_xaui_rx_polarity_flip_29=0x0000
|
|
|
|
#WC28
|
|
phy_xaui_tx_polarity_flip_118=0x000F
|
|
phy_xaui_rx_polarity_flip_118=0x000F
|
|
|
|
#WC29
|
|
phy_xaui_tx_polarity_flip_122=0x0004
|
|
phy_xaui_rx_polarity_flip_122=0x0000
|
|
|
|
#WC30
|
|
phy_xaui_tx_polarity_flip_126=0x000F
|
|
phy_xaui_rx_polarity_flip_126=0x0000
|
|
|
|
#WC31
|
|
phy_xaui_tx_polarity_flip_130=0x0006
|
|
phy_xaui_rx_polarity_flip_130=0x0000
|
|
|