bb73687514
* Add new CIG device CS6436-54P and CS5435-54P, also update code for CS6436-56P * security kernel update to 4.9.189 for CIG devices * security kernel update to 4.9.189 for CIG devices * Update rules Update rule file
223 lines
6.6 KiB
C
223 lines
6.6 KiB
C
/* --------------------------------------------------------------------
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* A hwmon driver for the CIG cs6436-54P
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*
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* Copyright (C) 2018 Cambridge, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* -------------------------------------------------------------------- */
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#ifndef I2C_LPC_H
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#define I2C_LPC_H 1
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/* ----- Control register bits ---------------------------------------- */
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#define I2C_LPC_PIN 0x80
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#define I2C_LPC_ESO 0x40
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#define I2C_LPC_ES1 0x20
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#define I2C_LPC_ES2 0x10
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#define I2C_LPC_ENI 0x08
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#define I2C_LPC_STO 0x40
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#define I2C_LPC_ACK 0x01
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/*command register*/
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#define I2C_LPC_STA 0x80
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#define I2C_LPC_ABT 0x40
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/*status register*/
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#define I2C_LPC_TBE 0x02
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#define I2C_LPC_IBB 0x80
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#define I2C_LPC_RBF 0x01
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#define I2C_LPC_TD 0x08
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#define I2C_LPC_START I2C_LPC_STA
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#define I2C_LPC_STOP I2C_LPC_STO
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#define I2C_LPC_REPSTART I2C_LPC_STA
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#define I2C_LPC_IDLE
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/* ----- Status register bits ----------------------------------------- */
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/*#define I2C_LPC_PIN 0x80 as above*/
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#define I2C_LPC_INI 0x40 /* 1 if not initialized */
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#define I2C_LPC_STS 0x20
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#define I2C_LPC_BER 0x10
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#define I2C_LPC_AD0 0x08
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#define I2C_LPC_LRB 0x08
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#define I2C_LPC_AAS 0x04
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#define I2C_LPC_LAB 0x02
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#define I2C_LPC_BB 0x80
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/* ----- Chip clock frequencies --------------------------------------- */
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#define I2C_LPC_CLK3 0x00
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#define I2C_LPC_CLK443 0x10
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#define I2C_LPC_CLK6 0x14
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#define I2C_LPC_CLK 0x18
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#define I2C_LPC_CLK12 0x1c
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/* ----- transmission frequencies ------------------------------------- */
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#define I2C_LPC_TRNS90 0x00 /* 90 kHz */
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#define I2C_LPC_TRNS45 0x01 /* 45 kHz */
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#define I2C_LPC_TRNS11 0x02 /* 11 kHz */
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#define I2C_LPC_TRNS15 0x03 /* 1.5 kHz */
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#define I2C_LPC_OWNADR 0
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#define I2C_LPC_INTREG I2C_LPC_ES2
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#define I2C_LPC_CLKREG I2C_LPC_ES1
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#define I2C_LPC_REG_TEST 0x01
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#define I2C_LPC_REG_BUS_SEL 0x80
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#define I2C_LPC_REG_DEVICE_ADDR 0x81
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#define I2C_LPC_REG_BYTE_COUNT 0x83
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#define I2C_LPC_REG_COMMAND 0x84
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#define I2C_LPC_REG_STATUS 0x85
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#define I2C_LPC_REG_DATA_RX1 0x86
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#define I2C_LPC_REG_DATA_RX2 0x87
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#define I2C_LPC_REG_DATA_RX3 0x88
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#define I2C_LPC_REG_DATA_RX4 0x89
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#define I2C_LPC_REG_DATA_TX1 0x8a
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#define I2C_LPC_REG_DATA_TX2 0x8b
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#define I2C_LPC_REG_DATA_TX3 0x8c
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#define I2C_LPC_REG_DATA_TX4 0x8d
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#define ADDR_REG_SFP_STATUS_ADDR 0X62 //reg addr +R/W# //1031
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#define ADDR_REG_SFP_STATUS_TX 0X63 // write data
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#define ADDR_REG_SFP_STATUS_RX 0X64 //read data
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#define ADDR_REG_SFP_STATUS_COMMAND 0X65 //cmd bit7=1,go
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#define ADDR_REG_SFP_STATUS_STATUS 0X66 //status
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#define CPLD_MASTER_INTERRUPT_STATUS_REG 0x20
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#define CPLD_MASTER_INTERRUPT_MASK_REG 0x21
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#define CPLD_MASTER_INTERRUPT_ALL 0x3f
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#define CPLD_MASTER_INTERRUPT_CPLD2 0x20
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#define CPLD_MASTER_INTERRUPT_CPLD1 0x10
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#define CPLD_MASTER_INTERRUPT_PSU2 0x08
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#define CPLD_MASTER_INTERRUPT_PSU1 0x04
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#define CPLD_MASTER_INTERRUPT_6320 0x02
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#define CPLD_MASTER_INTERRUPT_LSW 0x01
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#define CPLD_SLAVE1_INTERRUPT_STATUS_L_REG 0x20
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#define CPLD_SLAVE1_INTERRUPT_STATUS_H_REG 0x21
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#define CPLD_SLAVE2_INTERRUPT_STATUS_L_REG 0x22
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#define CPLD_SLAVE2_INTERRUPT_STATUS_H_REG 0x23
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#define CPLD_SLAVE1_INTERRUPT_MASK_REG 0x24
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#define CPLD_SLAVE2_INTERRUPT_MASK_REG 0x25
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#define CPLD_SLAVE1_PRESENT08_REG 0x01
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#define CPLD_SLAVE1_PRESENT16_REG 0x02
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#define CPLD_SLAVE1_PRESENT24_REG 0x03
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#define CPLD_SLAVE2_PRESENT32_REG 0x04
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#define CPLD_SLAVE2_PRESENT40_REG 0x05
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#define CPLD_SLAVE2_PRESENT48_REG 0x06
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#define CPLD_SLAVE1_RX_LOST08_REG 0x07
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#define CPLD_SLAVE1_RX_LOST16_REG 0x08
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#define CPLD_SLAVE1_RX_LOST24_REG 0x09
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#define CPLD_SLAVE2_RX_LOST32_REG 0x0a
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#define CPLD_SLAVE2_RX_LOST40_REG 0x0b
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#define CPLD_SLAVE2_RX_LOST48_REG 0x0c
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#define CPLD_SLAVE1_TX_FAULT08_REG 0x0d
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#define CPLD_SLAVE1_TX_FAULT16_REG 0x0e
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#define CPLD_SLAVE1_TX_FAULT24_REG 0x0f
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#define CPLD_SLAVE2_TX_FAULT32_REG 0x10
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#define CPLD_SLAVE2_TX_FAULT40_REG 0x11
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#define CPLD_SLAVE2_TX_FAULT48_REG 0x12
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#define CPLD_SLAVE2_PRESENT56_REG 0x19
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#define CPLD_SLAVE2_QSFP_CR56_REG 0x1a
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#define CPLD_SLAVE1_INTERRUPT_PRESENT08 0x0001
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#define CPLD_SLAVE1_INTERRUPT_PRESENT16 0x0002
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#define CPLD_SLAVE1_INTERRUPT_PRESENT24 0x0004
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#define CPLD_SLAVE2_INTERRUPT_PRESENT32 0x0001
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#define CPLD_SLAVE2_INTERRUPT_PRESENT40 0x0002
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#define CPLD_SLAVE2_INTERRUPT_PRESENT48 0x0004
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#define CPLD_SLAVE2_INTERRUPT_QSFP_CR56 0x0200
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#define CPLD_SLAVE2_INTERRUPT_PRESENT56 0x0400
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#define CPLD_SLAVE1_INTERRUPT_RX_LOST08 0x0008
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#define CPLD_SLAVE1_INTERRUPT_RX_LOST16 0x0010
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#define CPLD_SLAVE1_INTERRUPT_RX_LOST24 0x0020
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#define CPLD_SLAVE2_INTERRUPT_RX_LOST32 0x0008
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#define CPLD_SLAVE2_INTERRUPT_RX_LOST40 0x0010
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#define CPLD_SLAVE2_INTERRUPT_RX_LOST48 0x0020
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#define CPLD_SLAVE1_INTERRUPT_TX_FAULT08 0x0040
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#define CPLD_SLAVE1_INTERRUPT_TX_FAULT16 0x0080
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#define CPLD_SLAVE1_INTERRUPT_TX_FAULT24 0x0100
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#define CPLD_SLAVE2_INTERRUPT_TX_FAULT32 0x0040
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#define CPLD_SLAVE2_INTERRUPT_TX_FAULT40 0x0080
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#define CPLD_SLAVE2_INTERRUPT_TX_FAULT48 0x0100
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#define WAIT_TIME_OUT_COUNT 100
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struct i2c_algo_lpc_data {
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void *data; /* private data for lolevel routines */
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void (*setlpc) (void *data, int ctl, int val);
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int (*getlpc) (void *data, int ctl);
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int (*getown) (void *data);
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int (*getclock) (void *data);
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void (*waitforpin) (void *data);
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int (*xfer_begin) (void *data);
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int (*xfer_end) (void *data);
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/* Multi-master lost arbitration back-off delay (msecs)
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* This should be set by the bus adapter or knowledgable client
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* if bus is multi-mastered, else zero
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*/
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unsigned long lab_mdelay;
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};
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struct subsys_private {
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struct kset subsys;
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struct kset *devices_kset;
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struct list_head interfaces;
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struct mutex mutex;
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struct kset *drivers_kset;
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struct klist klist_devices;
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struct klist klist_drivers;
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struct blocking_notifier_head bus_notifier;
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unsigned int drivers_autoprobe:1;
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struct bus_type *bus;
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struct kset glue_dirs;
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struct class *class;
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};
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void cs6436_54p_sysfs_add_client(struct i2c_client *client);
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void cs6436_54p_sysfs_remove_client(struct i2c_client *client);
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#endif /* I2C_LPC8584_H */
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