sonic-buildimage/device/arista
bingwang-ms ac86f71287
Add extra lossy PG profile for ports between T1 and T2 (#11157)
Signed-off-by: bingwang <wang.bing@microsoft.com>

Why I did it
This PR brings two changes

Add lossy PG profile for PG2 and PG6 on T1 for ports between T1 and T2.
After PR Update qos config to clear queues for bounced back traffic #10176 , the DSCP_TO_TC_MAP and TC_TO_PG_MAP is updated when remapping is enable

DSCP_TO_TC_MAP
Before	After	Why do this change
"2" : "1"	"2" : "2"	Only change for leaf router to map DSCP 2 to TC 2 as TC 2 will be used for lossless TC
"6" : "1"	"6" : "6"	Only change for leaf router to map DSCP 6 to TC 6 as TC 6 will be used for lossless TC

TC_TO_PRIORITY_GROUP_MAP
Before	After	Why do this change
"2" : "0"	"2" : "2"	Only change for leaf router to map TC 2 to PG 2 as PG 2 will be used for lossless PG
"6" : "0"	"6" : "6"	Only change for leaf router to map TC 6 to PG 6 as PG 6 will be used for lossless PG

So, we have two new lossy PGs (2 and 6) for the T2 facing ports on T1, and two new lossless PGs (2 and 6) for the T0 facing port on T1.
However, there is no lossy PG profile for the T2 facing ports on T1. The lossless PGs for ports between T1 and T0 have been handled by buffermgrd .Therefore, We need to add lossy PG profiles for T2 facing ports on T1.

We don't have this issue on T0 because PG 2 and PG 6 are lossless PGs, and there is no lossy traffic mapped to PG 2 and PG 6

Map port level TC7 to PG0
Before the PCBB change, DSCP48 -> TC 6 -> PG 0.
After the PCBB change, DSCP48 -> TC 7 -> PG 7
Actually, we can map TC7 to PG0 to save a lossy PG.

How I did it
Update the qos and buffer template.

How to verify it
Verified by UT.
2022-06-28 12:50:33 -07:00
..
x86_64-arista_7050_qx32 Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9199) 2021-11-09 07:21:57 -08:00
x86_64-arista_7050_qx32s [Arista] Change default_sku for 7050QX-32S (#9730) 2022-01-16 07:36:22 +05:30
x86_64-arista_7050cx3_32s Add extra lossy PG profile for ports between T1 and T2 (#11157) 2022-06-28 12:50:33 -07:00
x86_64-arista_7050dx4_32s [Arista] Add ASIC configs for blackhawktd4 (#10885) 2022-06-17 12:50:47 -07:00
x86_64-arista_7050px4_32s [Arista] Add ASIC configs for blackhawktd4 (#10885) 2022-06-17 12:50:47 -07:00
x86_64-arista_7050sx3_48c8 [broadcom]: td2/td3 change cpu cos num to 10 (#9301) 2021-11-17 20:56:46 -08:00
x86_64-arista_7050sx3_48yc8 [broadcom]: td2/td3 change cpu cos num to 10 (#9301) 2021-11-17 20:56:46 -08:00
x86_64-arista_7060_cx32s [AN/LT][Fix bug]:enable phy_an_lt_msft attribute on some platforms (#11147) 2022-06-15 17:29:45 -07:00
x86_64-arista_7060cx2_32s Add platform_asic file to each platform folder in sonic-device-data based package (#8542) 2021-10-08 19:27:48 -07:00
x86_64-arista_7060dx4_32 [Arista] Add 1x100G over 4 lanes configuration for 7060DX4 (#10655) 2022-04-25 08:11:32 -07:00
x86_64-arista_7060dx5_64s [Arista] Add support support for 7060dx5_64s and 7060px5_64s (#10888) 2022-06-16 09:51:42 -07:00
x86_64-arista_7060px4_32 Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9199) 2021-11-09 07:21:57 -08:00
x86_64-arista_7060px5_64s [Arista] Add support support for 7060dx5_64s and 7060px5_64s (#10888) 2022-06-16 09:51:42 -07:00
x86_64-arista_7170_32c [BFN] Update configuration files (#9913) 2022-03-09 09:57:08 +05:30
x86_64-arista_7170_32cd [BFN] Update configuration files (#9913) 2022-03-09 09:57:08 +05:30
x86_64-arista_7170_64c Updated format of generating BUFFER_QUEUE in buffers_defaults templates (#9850) 2022-04-13 09:11:01 -07:00
x86_64-arista_7170b_64c [Arista] Update driver submodules (#9393) 2021-12-08 11:33:36 -08:00
x86_64-arista_7260cx3_64 Add extra lossy PG profile for ports between T1 and T2 (#11157) 2022-06-28 12:50:33 -07:00
x86_64-arista_7280cr3_32d4 Add platform_asic file to each platform folder in sonic-device-data based package (#8542) 2021-10-08 19:27:48 -07:00
x86_64-arista_7280cr3_32p4 Add platform_asic file to each platform folder in sonic-device-data based package (#8542) 2021-10-08 19:27:48 -07:00
x86_64-arista_7280cr3mk_32d4 Add platform_asic file to each platform folder in sonic-device-data based package (#8542) 2021-10-08 19:27:48 -07:00
x86_64-arista_7280cr3mk_32p4 [gearbox] use credo sai v0.7.5 (#10578) 2022-04-15 10:41:43 -07:00
x86_64-arista_7800_sup [chassis][voq]Update bcm config file system_ref_core_clock_khz param for j2cplus linecards (#11212) 2022-06-23 08:03:08 -07:00
x86_64-arista_7800r3_48cq2_lc Updated Chassis MMU settings for 40G/100G/400G line cards (#11108) 2022-06-23 10:03:59 -07:00
x86_64-arista_7800r3_48cqm2_lc Updated Chassis MMU settings for 40G/100G/400G line cards (#11108) 2022-06-23 10:03:59 -07:00
x86_64-arista_7800r3a_36d2_lc Setting the soc property for num_sa_per_sc on macsec encrypt and decrypt (#11166) 2022-06-27 12:53:57 -07:00
x86_64-arista_common [Arista] Add missing configuration files for linecards (#10749) 2022-05-09 11:51:38 -07:00
x86_64-arista_7280cr3k_32d4 [arista]: Add SmartsvilleDDBK and SmartsvilleBkMs (#4662) 2020-05-28 14:59:00 -07:00
x86_64-arista_7280cr3k_32p4 [arista] Add support for more 7280CR3 variants (#3711) 2019-11-06 10:11:38 -08:00
x86_64-arista_7800r3a_36d_lc [Arista] Add support for Wolverine linecards (#8887) 2022-05-20 14:11:06 -07:00
x86_64-arista_7800r3a_36dm2_lc [Arista] Add support for Wolverine linecards (#8887) 2022-05-20 14:11:06 -07:00
x86_64-arista_7800r3a_36p_lc [Arista] Add support for Wolverine linecards (#8887) 2022-05-20 14:11:06 -07:00
x86_64-arista_7800r3ak_36d2_lc [Arista] Add support for Wolverine linecards (#8887) 2022-05-20 14:11:06 -07:00
x86_64-arista_7800r3ak_36dm2_lc [Arista] Add support for Wolverine linecards (#8887) 2022-05-20 14:11:06 -07:00