7302132103
- Support for new platform Questone - Belgite renamed to DS1000 - Hardened bug fixes and unified CLI O/P for Celestica platforms
543 lines
13 KiB
C
543 lines
13 KiB
C
/*
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* cls-switchboard.c - PCI device driver for Silverstone Switch board FPGA.
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*
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* Author: Pradchaya Phucharoen
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*
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* Copyright (C) 2019 Celestica Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/acpi.h>
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#include <linux/interrupt.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/i2c-ocores.h>
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#include "xcvr-cls.h"
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#include "cls-pca954x.h"
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#define MOD_VERSION "2.1.2"
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#define DRV_NAME "cls-switchboard"
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#define I2C_MUX_CHANNEL(_ch, _adap_id) \
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[_ch] = { .adap_id = _adap_id }
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#define FPGA_PCIE_DEVICE_ID 0x7021
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#define MMIO_BAR 0
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#define I2C_BUS_OFS 9
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/* I2C ocore configurations */
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#define OCORE_REGSHIFT 2
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#define OCORE_IP_CLK_khz 62500
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#define OCORE_BUS_CLK_khz 100
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#define OCORE_REG_IO_WIDTH 1
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/* Optical port xcvr configuration */
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#define XCVR_REG_SHIFT 2
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#define XCVR_NUM_PORT 34
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#define XCVR_PORT_REG_SIZE 0x10
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/* i2c_bus_config - an i2c-core resource and platform data
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* @id - I2C bus device ID, for identification.
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* @res - resources for an i2c-core device.
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* @num_res - size of the resources.
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* @pdata - a platform data of an i2c-core device.
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*/
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struct i2c_bus_config {
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int id;
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struct resource *res;
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ssize_t num_res;
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struct ocores_i2c_platform_data pdata;
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};
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/* switchbrd_priv - switchboard private data */
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struct switchbrd_priv {
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unsigned long base;
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int num_i2c_bus;
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struct platform_device **i2cbuses_pdev;
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struct platform_device *regio_pdev;
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struct platform_device *spiflash_pdev;
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struct platform_device *xcvr_pdev;
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};
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/* I2C bus speed param */
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static int bus_clock_master_1 = 100;
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module_param(bus_clock_master_1, int, 0660);
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MODULE_PARM_DESC(bus_clock_master_1,
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"I2C master 1 bus speed in KHz 50/80/100/200/400");
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static int bus_clock_master_2 = 100;
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module_param(bus_clock_master_2, int, 0660);
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MODULE_PARM_DESC(bus_clock_master_2,
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"I2C master 2 bus speed in KHz 50/80/100/200/400");
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static int bus_clock_master_3 = 100;
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module_param(bus_clock_master_3, int, 0660);
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MODULE_PARM_DESC(bus_clock_master_3,
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"I2C master 3 bus speed in KHz 50/80/100/200/400");
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static int bus_clock_master_4 = 100;
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module_param(bus_clock_master_4, int, 0660);
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MODULE_PARM_DESC(bus_clock_master_4,
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"I2C master 4 bus speed in KHz 50/80/100/200/400");
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static int bus_clock_master_5 = 100;
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module_param(bus_clock_master_5, int, 0660);
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MODULE_PARM_DESC(bus_clock_master_5,
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"I2C master 5 bus speed in KHz 50/80/100/200/400");
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// NOTE: Silverstone i2c channel mapping is very wierd!!!
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/* PCA9548 channel config on MASTER BUS 3 */
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static struct pca954x_platform_mode i2c_mux_70_modes[] = {
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 23),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 26),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 27),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 28),
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 29),
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 30),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 31),
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 32)
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};
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static struct pca954x_platform_mode i2c_mux_71_modes[] = {
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 1),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 2),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 3),
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 4),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 5),
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 6),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 15),
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 8)
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};
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static struct pca954x_platform_mode i2c_mux_72_modes[] = {
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 17),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 18),
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 19),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 20),
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 21),
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 22),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 25),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 24)
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};
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static struct pca954x_platform_mode i2c_mux_73_modes[] = {
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 9),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 10),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 11),
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 12),
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 13),
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 14),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 7),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 16)
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};
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static struct pca954x_platform_data om_muxes[] = {
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{
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.modes = i2c_mux_70_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_70_modes),
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},
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{
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.modes = i2c_mux_71_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_71_modes),
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},
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{
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.modes = i2c_mux_72_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_72_modes),
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},
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{
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.modes = i2c_mux_73_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_73_modes),
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},
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};
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/* Optical Module bus 3 i2c muxes info */
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static struct i2c_board_info i2c_info_3[] = {
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{
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I2C_BOARD_INFO("cls_pca9548", 0x70),
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.platform_data = &om_muxes[0],
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},
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{
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I2C_BOARD_INFO("cls_pca9548", 0x71),
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.platform_data = &om_muxes[1],
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},
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{
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I2C_BOARD_INFO("cls_pca9548", 0x72),
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.platform_data = &om_muxes[2],
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},
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{
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I2C_BOARD_INFO("cls_pca9548", 0x73),
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.platform_data = &om_muxes[3],
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},
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};
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/* RESOURCE SEPERATES BY FUNCTION */
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/* Resource IOMEM for i2c bus 1 */
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static struct resource cls_i2c_res_1[] = {
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{
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.start = 0x800, .end = 0x81F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 2 */
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static struct resource cls_i2c_res_2[] = {
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{
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.start = 0x820, .end = 0x83F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 3 */
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static struct resource cls_i2c_res_3[] = {
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{
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.start = 0x840, .end = 0x85F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 4 */
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static struct resource cls_i2c_res_4[] = {
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{
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.start = 0x860, .end = 0x87F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 5 */
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static struct resource cls_i2c_res_5[] = {
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{
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.start = 0x880, .end = 0x89F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for reg access */
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static struct resource reg_io_res[] = {
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{
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.start = 0x00, .end = 0xFF,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for spi flash firmware upgrade */
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static struct resource spi_flash_res[] = {
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{
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.start = 0x1200, .end = 0x121F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for front panel XCVR */
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static struct resource xcvr_res[] = {
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{
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.start = 0x4000, .end = 0x421F,
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.flags = IORESOURCE_MEM,},
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};
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static struct i2c_bus_config i2c_bus_configs[] = {
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{
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.id = 1,
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.res = cls_i2c_res_1,
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.num_res = ARRAY_SIZE(cls_i2c_res_1),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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{
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.id = 2,
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.res = cls_i2c_res_2,
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.num_res = ARRAY_SIZE(cls_i2c_res_2),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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{
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.id = 3,
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.res = cls_i2c_res_3,
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.num_res = ARRAY_SIZE(cls_i2c_res_3),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = ARRAY_SIZE(i2c_info_3),
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.devices = i2c_info_3,
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},
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},
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{
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.id = 4,
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.res = cls_i2c_res_4,
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.num_res = ARRAY_SIZE(cls_i2c_res_4),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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{
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.id = 5,
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.res = cls_i2c_res_5,
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.num_res = ARRAY_SIZE(cls_i2c_res_5),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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};
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/* xcvr front panel mapping */
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static struct port_info front_panel_ports[] = {
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{"QSFP1", 1, QSFP},
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{"QSFP2", 2, QSFP},
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{"QSFP3", 3, QSFP},
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{"QSFP4", 4, QSFP},
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{"QSFP5", 5, QSFP},
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{"QSFP6", 6, QSFP},
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{"QSFP7", 7, QSFP},
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{"QSFP8", 8, QSFP},
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{"QSFP9", 9, QSFP},
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{"QSFP10", 10, QSFP},
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{"QSFP11", 11, QSFP},
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{"QSFP12", 12, QSFP},
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{"QSFP13", 13, QSFP},
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{"QSFP14", 14, QSFP},
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{"QSFP15", 15, QSFP},
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{"QSFP16", 16, QSFP},
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{"QSFP17", 17, QSFP},
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{"QSFP18", 18, QSFP},
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{"QSFP19", 19, QSFP},
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{"QSFP20", 20, QSFP},
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{"QSFP21", 21, QSFP},
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{"QSFP22", 22, QSFP},
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{"QSFP23", 23, QSFP},
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{"QSFP24", 24, QSFP},
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{"QSFP25", 25, QSFP},
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{"QSFP26", 26, QSFP},
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{"QSFP27", 27, QSFP},
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{"QSFP28", 28, QSFP},
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{"QSFP29", 29, QSFP},
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{"QSFP30", 30, QSFP},
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{"QSFP31", 31, QSFP},
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{"QSFP32", 32, QSFP},
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{"SFP1", 33, SFP},
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{"SFP2", 34, SFP}
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/* END OF LIST */
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};
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static struct cls_xcvr_platform_data xcvr_data = {
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.port_reg_size = 0x10,
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.num_ports = ARRAY_SIZE(front_panel_ports),
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.devices = front_panel_ports,
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};
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// TODO: Add a platform configuration struct, and use probe as a factory,
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// so xcvr, fwupgrade device can configured as options.
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static int cls_fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct switchbrd_priv *priv;
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struct platform_device **i2cbuses_pdev;
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struct platform_device *regio_pdev;
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struct platform_device *xcvr_pdev;
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unsigned long rstart;
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int num_i2c_bus, i;
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int err;
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err = pci_enable_device(dev);
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if (err){
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dev_err(&dev->dev, "Failed to enable PCI device\n");
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goto err_exit;
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}
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/* Check for valid MMIO address */
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rstart = pci_resource_start(dev, MMIO_BAR);
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if (!rstart) {
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dev_err(&dev->dev, "Switchboard base address uninitialized, "
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"check FPGA\n");
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err = -ENODEV;
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goto err_disable_device;
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}
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dev_dbg(&dev->dev, "BAR%d res: 0x%lx-0x%llx\n", MMIO_BAR,
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rstart, pci_resource_end(dev, MMIO_BAR));
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priv = devm_kzalloc(&dev->dev,
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sizeof(struct switchbrd_priv), GFP_KERNEL);
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if (!priv){
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err = -ENOMEM;
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goto err_disable_device;
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}
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pci_set_drvdata(dev, priv);
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num_i2c_bus = ARRAY_SIZE(i2c_bus_configs);
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i2cbuses_pdev = devm_kzalloc(
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&dev->dev,
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num_i2c_bus * sizeof(struct platform_device*),
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GFP_KERNEL);
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reg_io_res[0].start += rstart;
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reg_io_res[0].end += rstart;
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xcvr_res[0].start += rstart;
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xcvr_res[0].end += rstart;
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regio_pdev = platform_device_register_resndata(
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&dev->dev, "cls-swbrd-io",
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-1,
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reg_io_res, ARRAY_SIZE(reg_io_res),
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NULL, 0);
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if (IS_ERR(regio_pdev)) {
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dev_err(&dev->dev, "Failed to register cls-swbrd-io\n");
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err = PTR_ERR(regio_pdev);
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goto err_disable_device;
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}
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xcvr_pdev = platform_device_register_resndata(
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NULL,
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"cls-xcvr",
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-1,
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xcvr_res,
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ARRAY_SIZE(xcvr_res),
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&xcvr_data,
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sizeof(xcvr_data));
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if (IS_ERR(xcvr_pdev)) {
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dev_err(&dev->dev, "Failed to register xcvr node\n");
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err = PTR_ERR(xcvr_pdev);
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goto err_unregister_regio;
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}
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for(i = 0; i < num_i2c_bus; i++){
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i2c_bus_configs[i].res[0].start += rstart;
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i2c_bus_configs[i].res[0].end += rstart;
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switch (i + 1) {
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case 1:
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i2c_bus_configs[i].pdata.bus_khz = bus_clock_master_1;
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break;
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case 2:
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i2c_bus_configs[i].pdata.bus_khz = bus_clock_master_2;
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break;
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case 3:
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i2c_bus_configs[i].pdata.bus_khz = bus_clock_master_3;
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break;
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case 4:
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i2c_bus_configs[i].pdata.bus_khz = bus_clock_master_4;
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break;
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case 5:
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i2c_bus_configs[i].pdata.bus_khz = bus_clock_master_5;
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break;
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default:
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i2c_bus_configs[i].pdata.bus_khz = OCORE_BUS_CLK_khz;
|
|
}
|
|
|
|
dev_dbg(&dev->dev, "i2c-bus.%d: 0x%llx - 0x%llx\n",
|
|
i2c_bus_configs[i].id,
|
|
i2c_bus_configs[i].res[0].start,
|
|
i2c_bus_configs[i].res[0].end);
|
|
|
|
i2cbuses_pdev[i] = platform_device_register_resndata(
|
|
&dev->dev, "ocores-i2c",
|
|
i2c_bus_configs[i].id,
|
|
i2c_bus_configs[i].res,
|
|
i2c_bus_configs[i].num_res,
|
|
&i2c_bus_configs[i].pdata,
|
|
sizeof(i2c_bus_configs[i].pdata));
|
|
|
|
if (IS_ERR(i2cbuses_pdev[i])) {
|
|
dev_err(&dev->dev, "Failed to register ocores-i2c.%d\n",
|
|
i2c_bus_configs[i].id);
|
|
err = PTR_ERR(i2cbuses_pdev[i]);
|
|
goto err_unregister_ocore;
|
|
}
|
|
}
|
|
|
|
priv->base = rstart;
|
|
priv->num_i2c_bus = num_i2c_bus;
|
|
priv->i2cbuses_pdev = i2cbuses_pdev;
|
|
priv->regio_pdev = regio_pdev;
|
|
priv->xcvr_pdev = xcvr_pdev;
|
|
return 0;
|
|
|
|
err_unregister_ocore:
|
|
for(i = 0; i < num_i2c_bus; i++){
|
|
if(priv->i2cbuses_pdev[i]){
|
|
platform_device_unregister(priv->i2cbuses_pdev[i]);
|
|
}
|
|
}
|
|
err_unregister_xcvr:
|
|
platform_device_unregister(xcvr_pdev);
|
|
err_unregister_regio:
|
|
platform_device_unregister(regio_pdev);
|
|
err_disable_device:
|
|
pci_disable_device(dev);
|
|
err_exit:
|
|
return err;
|
|
}
|
|
|
|
static void cls_fpga_remove(struct pci_dev *dev)
|
|
{
|
|
int i;
|
|
struct switchbrd_priv *priv = pci_get_drvdata(dev);
|
|
|
|
for(i = 0; i < priv->num_i2c_bus; i++){
|
|
if(priv->i2cbuses_pdev[i])
|
|
platform_device_unregister(priv->i2cbuses_pdev[i]);
|
|
}
|
|
platform_device_unregister(priv->xcvr_pdev);
|
|
platform_device_unregister(priv->regio_pdev);
|
|
pci_disable_device(dev);
|
|
return;
|
|
};
|
|
|
|
static const struct pci_device_id pci_clsswbrd[] = {
|
|
{ PCI_VDEVICE(XILINX, FPGA_PCIE_DEVICE_ID) },
|
|
{0, }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, pci_clsswbrd);
|
|
|
|
static struct pci_driver clsswbrd_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = pci_clsswbrd,
|
|
.probe = cls_fpga_probe,
|
|
.remove = cls_fpga_remove,
|
|
};
|
|
|
|
module_pci_driver(clsswbrd_pci_driver);
|
|
|
|
MODULE_AUTHOR("Pradchaya P.<pphuchar@celestica.com>");
|
|
MODULE_DESCRIPTION("Celestica Silverstone switchboard driver");
|
|
MODULE_VERSION(MOD_VERSION);
|
|
MODULE_LICENSE("GPL");
|