sonic-buildimage/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40
Stephen Sun e3ff08833e
[Mellanox] Support DSCP remapping in dual ToR topo on T0 switch (#12605)
- Why I did it
Support DSCP remapping in dual ToR topo on T0 switch for SKU Mellanox-SN4600c-C64, Mellanox-SN4600c-D48C40, Mellanox-SN2700, Mellanox-SN2700-D48C8.

- How I did it
Regarding buffer settings, originally, there are two lossless PGs and queues 3, 4. In dual ToR scenario, the lossless traffic from the leaf switch to the uplink of the ToR switch can be bounced back.
To avoid PFC deadlock, we need to map the bounce-back lossless traffic to different PGs and queues. Therefore, 2 additional lossless PGs and queues are allocated on uplink ports on ToR switches.

On uplink ports, map DSCP 2/6 to TC 2/6 respectively
On downlink ports, both DSCP 2/6 are still mapped to TC 1
Buffer adjusted according to the ports information:
Mellanox-SN4600c-C64:
56 downlinks 50G + 8 uplinks 100G
Mellanox-SN4600c-D48C40, Mellanox-SN2700, Mellanox-SN2700-D48C8:
24 downlinks 50G + 8 uplinks 100G

- How to verify it
Unit test.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2023-02-07 16:21:59 +02:00
..
buffers_defaults_objects.j2 [Reclaim buffer] Reclaim unused buffers by applying zero buffer profiles (#8768) 2021-11-29 08:04:01 -08:00
buffers_defaults_t0.j2 [Mellanox] Support DSCP remapping in dual ToR topo on T0 switch (#12605) 2023-02-07 16:21:59 +02:00
buffers_defaults_t1.j2 Fix typo and missing files in SN3800 and SN4600C's buffer templates (#9537) 2021-12-20 13:31:45 -08:00
buffers_dynamic.json.j2 [Mellanox] [master] Added D48C40 SKU for 4600C platform (#8201) 2021-07-19 10:07:35 -07:00
buffers.json.j2 [Mellanox] [master] Added D48C40 SKU for 4600C platform (#8201) 2021-07-19 10:07:35 -07:00
hwsku.json [mellanox] remove 2x40G and 4x40G breakout modes due to no hardware support (#8280) 2021-08-01 13:24:26 -07:00
pg_profile_lookup.ini [Mellanox] [master] Added D48C40 SKU for 4600C platform (#8201) 2021-07-19 10:07:35 -07:00
port_config.ini [Mellanox] Add NVIDIA Copyright header to "mellanox" files (#8799) 2021-10-17 19:03:02 +03:00
qos.json.j2 [Mellanox] Support DSCP remapping in dual ToR topo on T0 switch (#12605) 2023-02-07 16:21:59 +02:00
sai_4600c_48x50g_40x100g.xml [Mellanox] Add NVIDIA Copyright header to "mellanox" files (#8799) 2021-10-17 19:03:02 +03:00
sai.profile [Mellanox][vxlan] remove old static config for VXLAN src port range feature (#9956) 2022-02-13 14:55:59 +02:00