e286869b24
- Why I did it 1. Update Mellanox HW-MGMT package to newer version V.7.0030.1011 2. Replace the SONiC PMON Thermal control algorithm with the one inside the HW-MGMT package on all Nvidia platforms 3. Support Spectrum-4 systems - How I did it 1. Update the HW-MGMT package version number and submodule pointer 2. Remove the thermal control algorithm implementation from Mellanox platform API 3. Revise the patch to HW-MGMT package which will disable HW-MGMT from running on SIMX 4. Update the downstream kernel patch list Signed-off-by: Kebo Liu <kebol@nvidia.com>
44 lines
1.7 KiB
Diff
44 lines
1.7 KiB
Diff
From 020ab13e16f943bb66da221507f83634a7d9ca05 Mon Sep 17 00:00:00 2001
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From: Vadim Pasternak <vadimp@nvidia.com>
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Date: Wed, 1 Mar 2023 17:21:48 +0000
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Subject: [PATCH backport 5.10 4/5] platform: mellanox: Change register offset
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addresses
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Move debug register offsets to different location due to hardware changes.
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Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
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Reviewed-by: Michael Shych <michaelsh@nvidia.com>
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---
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drivers/platform/mellanox/mlx-platform.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
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index 4eb327720..b5d51673f 100644
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--- a/drivers/platform/mellanox/mlx-platform.c
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+++ b/drivers/platform/mellanox/mlx-platform.c
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@@ -66,10 +66,6 @@
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#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
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#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
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#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
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-#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0x3c
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-#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0x3d
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-#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0x3e
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-#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0x3f
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#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
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#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
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#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
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@@ -130,6 +126,10 @@
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#define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa
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#define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab
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#define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2
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+#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6
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+#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7
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+#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8
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+#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9
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#define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2
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#define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3
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#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
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--
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2.20.1
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