9e19a9a7cf
Why I did it Adding platform support for centec v682-48y8c and v682-48x8c. V682-48y8c switch has 48 SFP+ (1G/10G/25G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. V682-48y8c is different from V682-48y8c_d in that: transceiver is managed by cpu smbus rather than TsingMa.MX i2c bus. port led is managed by mcu inside TsingMa.MX. fan, psu, sensors, leds are managed by cpu smbus other than the cpu board vendor's close sourse driver. V682-48x8c switch has 48 SFP+ (1G/10G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. CPU used in v682-48y8c and v682-48x8c is Intel(R) Xeon(R) CPU D-1527. How I did it Modify related code in platform and device directory. Upgrade centec sai to v1.9. upgrade python to python3 and kernel version to 5.0 for V682-48y8c_d. How to verify it Build centec amd64 sonic image, verify platform functions (port, sfp, led etc) on centec v682-48y8c and v682-48x8c board. Co-authored-by: shil <shil@centecnetworks.com>
38 lines
1.1 KiB
Python
38 lines
1.1 KiB
Python
#!/usr/bin/env python
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import os
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import time
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def release_board():
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if open('/proc/cmdline', 'r').readlines()[0].find('SONIC_BOOT_TYPE=warm') != -1:
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return
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os.system('i2cset -y 0 0x37 0x4 0x0')
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time.sleep(1)
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os.system('i2cset -y 0 0x37 0x4 0x1')
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time.sleep(1)
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os.system('echo 1 > /sys/bus/pci/devices/0000\:00\:1c.0/remove')
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time.sleep(1)
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os.system('echo 1 > /sys/bus/pci/rescan')
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time.sleep(1)
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# EPLD_QSFP_RST
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os.system('i2cset -y 0 0x36 0x5 0xff')
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os.system('i2cset -y 0 0x37 0x5 0xff')
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# EPLD_QSFP_INT_MASK
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os.system('i2cset -y 0 0x36 0xd 0xff')
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os.system('i2cset -y 0 0x37 0xd 0xff')
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# EPLD_PPU_INT_MASK
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os.system('i2cset -y 0 0x36 0xb 0x00')
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# EPLD_SFP_DISABLE1
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os.system('i2cset -y 0 0x36 0xe 0x00')
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os.system('i2cset -y 0 0x37 0xe 0x00')
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# EPLD_SFP_DISABLE2
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os.system('i2cset -y 0 0x36 0xf 0x00')
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os.system('i2cset -y 0 0x37 0xf 0x00')
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# EPLD_SFP_DISABLE3
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os.system('i2cset -y 0 0x36 0x10 0x00')
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os.system('i2cset -y 0 0x37 0x10 0x00')
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if __name__ == '__main__':
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release_board()
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