252 lines
8.1 KiB
C
252 lines
8.1 KiB
C
/* header file for i2c cpld driver of ufispace_s9300_32d
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*
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* Copyright (C) 2017 UfiSpace Technology Corporation.
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* Leo Lin <leo.yt.lin@ufispace.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef UFISPACE_S9300_I2C_CPLD_H
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#define UFISPACE_S9300_I2C_CPLD_H
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/* CPLD device index value */
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enum cpld_id {
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cpld1,
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cpld2,
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cpld3,
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};
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enum LED_BLINK {
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NOBLINK,
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BLINK,
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};
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enum LED_BLINK_SPEED {
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BLINK_1X, // 0.5hz
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BLINK_4X, // 2hz
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};
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enum LED_STATUS {
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OFF,
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ON,
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};
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enum LED_YELLOW {
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YELLOW_OFF,
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YELLOW_ON,
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};
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enum LED_GREEN {
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GREEN_OFF,
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GREEN_ON,
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};
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/* QSFPDD port number */
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#define QSFPDD_MAX_PORT_NUM 32
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#define QSFPDD_MIN_PORT_NUM 1
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/* SFP+ port number */
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#define SFP_MAX_PORT_NUM 4
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#define SFP_MIN_PORT_NUM 1
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/* CPLD registers */
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/* CPLD 1 */
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#define CPLD_SKU_ID_REG 0x00
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#define CPLD_HW_REV_REG 0x01
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#define CPLD_VERSION_REG 0x02
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#define CPLD_ID_REG 0x03
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#define CPLD_BUILD_VER_REG 0x04
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// Interrupt status
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#define CPLD_MAC_INTR_REG 0x10
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#define CPLD_10G_PHY_INTR_REG 0x13
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#define CPLD_CPLD_FRU_INTR_REG 0x14
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#define CPLD_THERMAL_ALERT_INTR_REG 0x16
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#define CPLD_MISC_INTR_REG 0x1B
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#define CPLD_SYSTEM_INTR_REG 0x1D
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// Interrupt mask
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#define CPLD_MAC_INTR_MASK_REG 0x20
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#define CPLD_10G_PHY_INTR_MASK_REG 0x23
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#define CPLD_CPLD_FRU_INTR_MASK_REG 0x24
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#define CPLD_THERMAL_ALERT_INTR_MASK_REG 0x26
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#define CPLD_MISC_INTR_MASK_REG 0x2B
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// Interrupt event
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#define CPLD_MAC_INTR_EVENT_REG 0x30
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#define CPLD_10G_PHY_INTR_EVENT_REG 0x33
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#define CPLD_CPLD_FRU_INTR_EVENT_REG 0x14
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#define CPLD_THERMAL_ALERT_INTR_EVENT_REG 0x16
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#define CPLD_MISC_INTR_EVENT_REG 0x1B
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// Reset ctrl
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#define CPLD_MAC_RST_REG 0x40
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#define CPLD_10G_PHY_RST_REG 0x42
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#define CPLD_BMC_RST_REG 0x43
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#define CPLD_USB_RST_REG 0x44
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#define CPLD_MUX_RST_REG 0x46
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#define CPLD_MISC_RST_REG 0x48
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#define CPLD_BMC_WATCHDOG_REG 0x4D
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// Sys status
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#define CPLD_DAU_BD_PRES_REG 0x50
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#define CPLD_PSU_STATUS_REG 0x51
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#define CPLD_SYS_PW_STATUS_REG 0x52
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#define CPLD_MISC_REG 0x5B
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// Mux ctrl
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#define CPLD_MUX_CTRL_REG 0x5C
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#define CPLD_MAC_QSFP_SEL_CTRL_REG 0x5F
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// Led ctrl
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#define CPLD_SYS_LED_CTRL_1_REG 0x80
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#define CPLD_SYS_LED_CTRL_2_REG 0x81
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#define CPLD_BEACON_LED_CTRL_REG 0x84
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#define CPLD_PORT_LED_CLR_CTRL_REG 0x85
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// Event Detect Ctrl
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#define CPLD_EVENT_DETECT_CTRL_REG 0x5D
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/* CPLD 2 */
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/* G0 - port 0 ~ 7
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G1 - port 8 ~ 15
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G2 - port 16 ~ 23
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G3 - port 24 ~ 31
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*/
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// Interrupt status
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#define CPLD_QSFPDD_MOD_INT_G0_REG 0x10
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#define CPLD_QSFPDD_MOD_INT_G1_REG 0x11
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#define CPLD_QSFPDD_MOD_INT_G2_REG 0x12
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#define CPLD_QSFPDD_MOD_INT_G3_REG 0x13
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#define CPLD_QSFPDD_PRES_G0_REG 0x14
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#define CPLD_QSFPDD_PRES_G1_REG 0x15
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#define CPLD_QSFPDD_PRES_G2_REG 0x16
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#define CPLD_QSFPDD_PRES_G3_REG 0x17
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#define CPLD_QSFPDD_FUSE_INT_G0_REG 0x18
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#define CPLD_QSFPDD_FUSE_INT_G1_REG 0x19
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#define CPLD_QSFPDD_FUSE_INT_G2_REG 0x1A
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#define CPLD_QSFPDD_FUSE_INT_G3_REG 0x1B
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#define CPLD_SFP_TXFAULT_REG 0x1D
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#define CPLD_SFP_ABS_REG 0x1E
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#define CPLD_SFP_RXLOS_REG 0x1F
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// Interrupt mask
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#define CPLD_QSFPDD_MOD_INT_MASK_G0_REG 0x20
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#define CPLD_QSFPDD_MOD_INT_MASK_G1_REG 0x21
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#define CPLD_QSFPDD_MOD_INT_MASK_G2_REG 0x22
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#define CPLD_QSFPDD_MOD_INT_MASK_G3_REG 0x23
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#define CPLD_QSFPDD_PRES_MASK_G0_REG 0x24
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#define CPLD_QSFPDD_PRES_MASK_G1_REG 0x25
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#define CPLD_QSFPDD_PRES_MASK_G2_REG 0x26
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#define CPLD_QSFPDD_PRES_MASK_G3_REG 0x27
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#define CPLD_QSFPDD_FUSE_INT_MASK_G0_REG 0x28
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#define CPLD_QSFPDD_FUSE_INT_MASK_G1_REG 0x29
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#define CPLD_QSFPDD_FUSE_INT_MASK_G2_REG 0x2A
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#define CPLD_QSFPDD_FUSE_INT_MASK_G3_REG 0x2B
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#define CPLD_SFP_TXFAULT_MASK_REG 0x2D
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#define CPLD_SFP_ABS_MASK_REG 0x2E
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#define CPLD_SFP_RXLOS_MASK_REG 0x2F
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// Interrupt event
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#define CPLD_QSFPDD_MOD_INT_EVENT_G0_REG 0x30
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#define CPLD_QSFPDD_MOD_INT_EVENT_G1_REG 0x31
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#define CPLD_QSFPDD_MOD_INT_EVENT_G2_REG 0x32
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#define CPLD_QSFPDD_MOD_INT_EVENT_G3_REG 0x33
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#define CPLD_QSFPDD_PRES_EVENT_G0_REG 0x34
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#define CPLD_QSFPDD_PRES_EVENT_G1_REG 0x35
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#define CPLD_QSFPDD_PRES_EVENT_G2_REG 0x36
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#define CPLD_QSFPDD_PRES_EVENT_G3_REG 0x37
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#define CPLD_QSFPDD_FUSE_INT_EVENT_G0_REG 0x38
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#define CPLD_QSFPDD_FUSE_INT_EVENT_G1_REG 0x39
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#define CPLD_QSFPDD_FUSE_INT_EVENT_G2_REG 0x3A
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#define CPLD_QSFPDD_FUSE_INT_EVENT_G3_REG 0x3B
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#define CPLD_SFP_TXFAULT_EVENT_REG 0x3D
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#define CPLD_SFP_ABS_EVENT_REG 0x3E
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#define CPLD_SFP_RXLOS_EVENT_REG 0x3F
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// Port ctrl
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#define CPLD_QSFPDD_RESET_CTRL_G0_REG 0x40
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#define CPLD_QSFPDD_RESET_CTRL_G1_REG 0x41
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#define CPLD_QSFPDD_RESET_CTRL_G2_REG 0x42
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#define CPLD_QSFPDD_RESET_CTRL_G3_REG 0x43
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#define CPLD_QSFPDD_LP_MODE_G0_REG 0x44
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#define CPLD_QSFPDD_LP_MODE_G1_REG 0x45
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#define CPLD_QSFPDD_LP_MODE_G2_REG 0x46
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#define CPLD_QSFPDD_LP_MODE_G3_REG 0x47
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#define CPLD_SFP_TX_DIS_REG 0x55
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#define CPLD_SFP_RS_REG 0x56
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#define CPLD_SFP_TS_REG 0x57
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// Port status
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#define CPLD_PORT_INT_STATUS_REG 0x58
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/* bit field structure for register value */
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struct cpld_reg_sku_id_t {
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u8 model_id:8;
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};
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struct cpld_reg_hw_rev_t {
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u8 hw_rev:2;
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u8 deph_rev:1;
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u8 build_rev:3;
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u8 reserved:1;
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u8 id_type:1;
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};
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struct cpld_reg_version_t {
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u8 minor:6;
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u8 major:2;
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};
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struct cpld_reg_id_t {
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u8 id:3;
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u8 release:5;
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};
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struct cpld_reg_beacon_led_ctrl_t {
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u8 reserve:5;
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u8 speed:1;
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u8 blink:1;
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u8 onoff:1;
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};
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/* common manipulation */
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#define INVALID(i, min, max) ((i < min) || (i > max) ? 1u : 0u)
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#define READ_BIT(val, bit) ((0u == (val & (1<<bit))) ? 0u : 1u)
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#define SET_BIT(val, bit) (val |= (1 << bit))
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#define CLEAR_BIT(val, bit) (val &= ~(1 << bit))
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#define TOGGLE_BIT(val, bit) (val ^= (1 << bit))
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#define _BIT(n) (1<<(n))
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#define _BIT_MASK(len) (BIT(len)-1)
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/* bitfield of register manipulation */
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#define READ_BF(bf_struct, val, bf_name, bf_value) \
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(bf_value = ((struct bf_struct *)&val)->bf_name)
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#define READ_BF_1(bf_struct, val, bf_name, bf_value) \
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bf_struct bf; \
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bf.data = val; \
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bf_value = bf.bf_name
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#define HW_REV_GET(val, res) \
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READ_BF(cpld_reg_hw_rev_t, val, hw_rev, res)
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#define DEPH_REV_GET(val, res) \
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READ_BF(cpld_reg_hw_rev_t, val, deph_rev, res)
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#define BUILD_REV_GET(val, res) \
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READ_BF(cpld_reg_hw_rev_t, val, build_rev, res)
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#define ID_TYPE_GET(val, res) \
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READ_BF(cpld_reg_hw_rev_t, val, id_type, res)
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#define CPLD_MAJOR_VERSION_GET(val, res) \
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READ_BF(cpld_reg_version_t, val, major, res)
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#define CPLD_MINOR_VERSION_GET(val, res) \
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READ_BF(cpld_reg_version_t, val, minor, res)
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#define CPLD_ID_ID_GET(val, res) \
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READ_BF(cpld_reg_id_t, val, id, res)
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/* CPLD access functions */
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extern int s9300_cpld_read(u8 cpld_idx, u8 reg);
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extern int s9300_cpld_write(u8 cpld_idx, u8 reg, u8 value);
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#endif
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