04b9ce8e32
Manual verification on switch (TH3 device) admin@str2-xxxxx-01:~$ bcmcmd bsv bsv BRCM SAI ver: [6.0.0.10], OCP SAI ver: [1.9.1], SDK ver: [sdk-6.5.23] drivshell> admin@str2-xxxxx-01:~$ bcmcmd version version Broadcom Command Monitor: Copyright (c) 1998-2021 Broadcom Release: sdk-6.5.23 built 20211020 (Wed Oct 20 06:52:58 2021) From root@fedbbfdbee81:/__w/2/s/output/x86-xgsall-deb/hsdk Platform: X86 OS: Unix (Posix) Chips: BCM56640_A0, BCM56850_A0, BCM56340_A0, BCM56960_A0, BCM56860_A0, BCM56970_A0, BCM56870_A0, BCM56980_A0, BCM56980_B0, BCM56370_A0, BCM56275_A0, BCM56770_A0, Chips: BCM56780_A0, BCM56782_A0, BCM56784_A0, BCM56785_A0, BCM56786_A0, BCM56787_A0, BCM56788_A0, BCM56789_A0, BCM56880_A0, BCM56880_B0, BCM56881_A0, BCM56881_B0, BCM56883_A0, BCM56883_B0, BCM56990_A0, BCM56990_B0, BCM56991_B0, BCM56992_B0, BCM56996_A0, BCM56996_B0, BCM56997_A0, BCM56997_B0 Variant drivers: BCM56780_A0_CNA_1_2_10, BCM56780_A0_DNA_2_7_6_0, BCM56880_A0_CNA_1_2_9, BCM56880_A0_DNA_4_9_5_0 PHYs: BCM5400, BCM54182, BCM54185, BCM54180, BCM54140, BCM54192, BCM54195, BCM54190, BCM54194, BCM54210, BCM54220, BCM54280, BCM54282, BCM54240, BCM54285, BCM5428X, BCM54290, BCM54292, BCM54294, BCM54295, BCM54296, BCM56160-GPHY, BCM53540-GPHY, BCM56275-GPHY, BCM8750, BCM8752, BCM8754, BCM84740, BCM84164, BCM84758, BCM84780, BCM84784, BCM84318, BCM84328, Sesto, BCM82780, copper sfp drivshell>
246 lines
8.0 KiB
C
246 lines
8.0 KiB
C
/*! \file ngbde_ioctl.c
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*
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* NGBDE IOCTL interface.
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*
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*/
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/*
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* $Copyright: Copyright 2018-2021 Broadcom. All rights reserved.
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* The term 'Broadcom' refers to Broadcom Inc. and/or its subsidiaries.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* A copy of the GNU General Public License version 2 (GPLv2) can
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* be found in the LICENSES folder.$
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*/
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#include <lkm/ngbde_ioctl.h>
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#include <ngbde.h>
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long
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ngbde_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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{
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struct ngbde_ioc_cmd_s ioc;
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struct ngbde_dev_s *swdev;
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struct ngbde_irq_reg_s ireg;
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struct ngbde_intr_ack_reg_s ackreg;
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phys_addr_t addr, size;
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unsigned int num_swdev;
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unsigned int rsrc_type, rsrc_idx;
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unsigned int irq_num, intr_cmd;
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uint32_t mreg, mval;
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if (copy_from_user(&ioc, (void *)arg, sizeof(ioc))) {
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return -EFAULT;
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}
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ioc.rc = NGBDE_IOC_SUCCESS;
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switch (cmd) {
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case NGBDE_IOC_MOD_INFO:
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ioc.op.mod_info.version = NGBDE_IOC_VERSION;
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break;
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case NGBDE_IOC_PROBE_INFO:
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ngbde_swdev_get_all(NULL, &num_swdev);
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ioc.op.probe_info.num_swdev = num_swdev;
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break;
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case NGBDE_IOC_DEV_INFO:
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swdev = ngbde_swdev_get(ioc.devid);
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if (!swdev) {
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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ioc.op.dev_info.vendor_id = swdev->vendor_id;
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ioc.op.dev_info.device_id = swdev->device_id;
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ioc.op.dev_info.revision = swdev->revision;
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ioc.op.dev_info.model = swdev->model;
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if (swdev->use_msi) {
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ioc.op.dev_info.flags |= NGBDE_DEV_F_MSI;
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}
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break;
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case NGBDE_IOC_PHYS_ADDR:
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swdev = ngbde_swdev_get(ioc.devid);
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if (!swdev) {
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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rsrc_type = ioc.op.rsrc_id.type;
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rsrc_idx = ioc.op.rsrc_id.inst;
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switch (rsrc_type) {
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case NGBDE_IO_RSRC_DEV_IO:
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if (rsrc_idx >= NGBDE_NUM_IOWIN_MAX) {
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printk(KERN_WARNING
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"ngbde: invalid resource index (%d)\n",
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rsrc_idx);
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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ioc.op.phys_addr.addr = swdev->iowin[rsrc_idx].addr;
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ioc.op.phys_addr.size = swdev->iowin[rsrc_idx].size;
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break;
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case NGBDE_IO_RSRC_DMA_MEM:
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if (rsrc_idx >= NGBDE_NUM_DMAPOOL_MAX) {
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printk(KERN_WARNING
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"ngbde: invalid resource index (%d)\n",
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rsrc_idx);
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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ioc.op.phys_addr.addr = swdev->dmapool[rsrc_idx].dmamem.paddr;
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ioc.op.phys_addr.size = swdev->dmapool[rsrc_idx].dmactrl.size;
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break;
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case NGBDE_IO_RSRC_DMA_BUS:
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if (rsrc_idx >= NGBDE_NUM_DMAPOOL_MAX) {
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printk(KERN_WARNING
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"ngbde: invalid resource index (%d)\n",
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rsrc_idx);
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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ioc.op.phys_addr.addr = swdev->dmapool[rsrc_idx].dmamem.baddr;
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ioc.op.phys_addr.size = swdev->dmapool[rsrc_idx].dmactrl.size;
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break;
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default:
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printk(KERN_WARNING
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"ngbde: unknown resource type (%d)\n",
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rsrc_type);
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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break;
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case NGBDE_IOC_INTR_CTRL:
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irq_num = ioc.op.intr_ctrl.irq_num;
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intr_cmd = ioc.op.intr_ctrl.cmd;
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switch (intr_cmd) {
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case NGBDE_ICTL_INTR_CONN:
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if (ngbde_intr_connect(ioc.devid, irq_num) < 0) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_ICTL_INTR_DISC:
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if (ngbde_intr_disconnect(ioc.devid, irq_num) < 0) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_ICTL_INTR_WAIT:
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if (ngbde_intr_wait(ioc.devid, irq_num) < 0) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_ICTL_INTR_STOP:
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if (ngbde_intr_stop(ioc.devid, irq_num) < 0) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_ICTL_REGS_CLR:
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if (ngbde_intr_regs_clr(ioc.devid, irq_num) < 0) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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default:
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printk(KERN_WARNING
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"%s: unknown interrupt control command (%d)\n",
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MOD_NAME, intr_cmd);
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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break;
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case NGBDE_IOC_IRQ_REG_ADD:
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irq_num = ioc.op.irq_reg_add.irq_num;
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ireg.status_reg = ioc.op.irq_reg_add.status_reg;
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ireg.mask_reg = ioc.op.irq_reg_add.mask_reg;
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ireg.kmask = ioc.op.irq_reg_add.kmask;
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ireg.status_is_masked = false;
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if (ioc.op.irq_reg_add.flags & NGBDE_DEV_IRQ_REG_F_MASKED) {
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ireg.status_is_masked = true;
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}
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ireg.mask_w1tc = false;
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if (ioc.op.irq_reg_add.flags & NGBDE_DEV_IRQ_REG_F_W1TC) {
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ireg.mask_w1tc = true;
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}
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if (ngbde_intr_reg_add(ioc.devid, irq_num, &ireg) < 0) {
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printk(KERN_WARNING
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"%s: Unable to add interrupt register\n",
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MOD_NAME);
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_IOC_INTR_ACK_REG_ADD:
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irq_num = ioc.op.intr_ack_reg_add.irq_num;
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ackreg.ack_reg = ioc.op.intr_ack_reg_add.ack_reg;
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ackreg.ack_val = ioc.op.intr_ack_reg_add.ack_val;
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ackreg.flags = ioc.op.intr_ack_reg_add.flags;
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if (ngbde_intr_ack_reg_add(ioc.devid, irq_num, &ackreg) < 0) {
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printk(KERN_WARNING
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"%s: Unable to add interrupt ack register\n",
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MOD_NAME);
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_IOC_IRQ_MASK_WR:
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irq_num = ioc.op.irq_mask_wr.irq_num;
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mreg = ioc.op.irq_mask_wr.offs;
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mval = ioc.op.irq_mask_wr.val;
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if (ngbde_intr_mask_write(ioc.devid, irq_num, 0, mreg, mval) < 0) {
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printk(KERN_WARNING
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"%s: Unable to write shared register\n",
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MOD_NAME);
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_IOC_PIO_WIN_MAP:
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swdev = ngbde_swdev_get(ioc.devid);
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if (!swdev) {
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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addr = ioc.op.pio_win.addr;
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size = ioc.op.pio_win.size;
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if (ngbde_pio_map(swdev, addr, size) == NULL) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_IOC_IIO_WIN_MAP:
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swdev = ngbde_swdev_get(ioc.devid);
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if (!swdev) {
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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addr = ioc.op.pio_win.addr;
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size = ioc.op.pio_win.size;
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if (ngbde_iio_map(swdev, addr, size) == NULL) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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case NGBDE_IOC_PAXB_WIN_MAP:
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swdev = ngbde_swdev_get(ioc.devid);
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if (!swdev) {
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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addr = ioc.op.pio_win.addr;
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size = ioc.op.pio_win.size;
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if (ngbde_paxb_map(swdev, addr, size) == NULL) {
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ioc.rc = NGBDE_IOC_FAIL;
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}
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break;
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default:
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printk(KERN_ERR "ngbde: invalid ioctl (%08x)\n", cmd);
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ioc.rc = NGBDE_IOC_FAIL;
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break;
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}
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if (copy_to_user((void *)arg, &ioc, sizeof(ioc))) {
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return -EFAULT;
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}
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return 0;
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}
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