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sonic-buildimage/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52
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Stephen Sun fa99059b51 Update buffer configuration for SKUs based on SN3800 (#5320) 
C64: 32 100G down links and 32 100G up links.
D112C8: 112 50G down links and 8 100G up links.
D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2020-09-28 16:16:45 +00:00
..
buffers_defaults_t0.j2 Update buffer configuration for SKUs based on SN3800 (#5320) 2020-09-28 16:16:45 +00:00
buffers_defaults_t1.j2 Update buffer configuration for SKUs based on SN3800 (#5320) 2020-09-28 16:16:45 +00:00
buffers.json.j2 added files to create SKU Mellanox-SN3800-D24C52 (#4808) 2020-06-28 07:22:12 -07:00
pg_profile_lookup.ini Support single ingress pool for MSFT SKUs and optimize headroom calculation (#5194) 2020-08-15 07:52:28 -07:00
port_config.ini [Mellanox] Change port index in port_config.ini to 1-based (#4781) 2020-06-28 07:24:10 -07:00
qos.json.j2 added files to create SKU Mellanox-SN3800-D24C52 (#4808) 2020-06-28 07:22:12 -07:00
sai_3800_24x50g_52x100g.xml added files to create SKU Mellanox-SN3800-D24C52 (#4808) 2020-06-28 07:22:12 -07:00
sai.profile added files to create SKU Mellanox-SN3800-D24C52 (#4808) 2020-06-28 07:22:12 -07:00