From f8a0954053e6e06070ed399e1810bea089ba36bd Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 2 Mar 2023 12:28:11 +0000 Subject: [PATCH backport v.5.10 4/8] platform: mellanox: Modify reset causes description Link: https://patchwork.kernel.org/project/platform-driver-x86/patch/20230814203406.12399-4-vadimp@nvidia.com/ For system of classes VMOD0005, VMOD0010: - remove "reset_from_comex", since this cause doesn't define specific reason. - add more speicific reason "reset_sw_reset", which is set along with removed "reset_from_comex". Signed-off-by: Vadim Pasternak Reviewed-by: Michael Shych --- drivers/platform/mellanox/mlx-platform.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c index 486a3e8da..67865636e 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -3832,12 +3832,6 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mask = GENMASK(7, 0) & ~BIT(2), .mode = 0444, }, - { - .label = "reset_from_comex", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), - .mode = 0444, - }, { .label = "reset_from_asic", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, @@ -3856,6 +3850,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mask = GENMASK(7, 0) & ~BIT(7), .mode = 0444, }, + { + .label = "reset_sw_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, { .label = "reset_comex_pwr_fail", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -- 2.20.1