# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
l2xmsg_shadow_hit_bits=0
l2xmsg_no_cb_during_table_rebuild=1

pbmp_xport_xe.0=0x8111181111c1111811118111181111c111182222
ccm_dma_enable=0
ccmdma_intr_enable=0
ctr_evict_enable=0
mem_cache_enable=0
parity_correction=0
parity_enable=0
phy_enable=0
phy_null=1
pll_bypass=1

init_all_modules=0



#portmap_38=257:10
#portmap_118=258:10


portmap_20=33:400
portmap_24=41:400
portmap_28=49:400
portmap_32=57:400
portmap_40=65:400
portmap_44=73:400
portmap_48=81:400
portmap_52=89:400
portmap_1=1:400
portmap_5=9:400
portmap_9=17:400
portmap_13=25:400
portmap_60=97:400
portmap_64=105:400
portmap_68=113:400
portmap_72=121:400
portmap_80=129:400
portmap_84=137:400
portmap_88=145:400
portmap_92=153:400
portmap_140=225:400
portmap_144=233:400
portmap_148=241:400
portmap_152=249:400
portmap_100=161:400
portmap_104=169:400
portmap_108=177:400
portmap_112=185:400
portmap_120=193:400
portmap_124=201:400
portmap_128=209:400
portmap_132=217:400

phy_chain_rx_lane_map_physical{33.0}=0x65732041
phy_chain_tx_lane_map_physical{33.0}=0x47206531
phy_chain_rx_lane_map_physical{41.0}=0x07561243
phy_chain_tx_lane_map_physical{41.0}=0x36207514
phy_chain_rx_lane_map_physical{49.0}=0x54632071
phy_chain_tx_lane_map_physical{49.0}=0x06241735
phy_chain_rx_lane_map_physical{57.0}=0x07561243
phy_chain_tx_lane_map_physical{57.0}=0x35207614
phy_chain_rx_lane_map_physical{65.0}=0x45623170
phy_chain_tx_lane_map_physical{65.0}=0x51260734
phy_chain_rx_lane_map_physical{73.0}=0x07561243
phy_chain_tx_lane_map_physical{73.0}=0x37245610
phy_chain_rx_lane_map_physical{81.0}=0x45632071
phy_chain_tx_lane_map_physical{81.0}=0x51260734
phy_chain_rx_lane_map_physical{89.0}=0x07561243
phy_chain_tx_lane_map_physical{89.0}=0x26437510
phy_chain_rx_lane_map_physical{1.0}=0x30176524
phy_chain_tx_lane_map_physical{1.0}=0x20615374
phy_chain_rx_lane_map_physical{9.0}=0x37562041
phy_chain_tx_lane_map_physical{9.0}=0x05176432
phy_chain_rx_lane_map_physical{17.0}=0x43607251
phy_chain_tx_lane_map_physical{17.0}=0x70261435
phy_chain_rx_lane_map_physical{25.0}=0x60347125
phy_chain_tx_lane_map_physical{25.0}=0x46357120
phy_chain_rx_lane_map_physical{97.0}=0x47601352
phy_chain_tx_lane_map_physical{97.0}=0x04265137
phy_chain_rx_lane_map_physical{105.0}=0x73206415
phy_chain_tx_lane_map_physical{105.0}=0x26374150
phy_chain_rx_lane_map_physical{113.0}=0x47632051
phy_chain_tx_lane_map_physical{113.0}=0x03254617
phy_chain_rx_lane_map_physical{121.0}=0x63027415
phy_chain_tx_lane_map_physical{121.0}=0x63721045
phy_chain_rx_lane_map_physical{129.0}=0x30154627
phy_chain_tx_lane_map_physical{129.0}=0x04735261
phy_chain_rx_lane_map_physical{137.0}=0x24753061
phy_chain_tx_lane_map_physical{137.0}=0x37614520
phy_chain_rx_lane_map_physical{145.0}=0x47601352
phy_chain_tx_lane_map_physical{145.0}=0x63274510
phy_chain_rx_lane_map_physical{153.0}=0x07361524
phy_chain_tx_lane_map_physical{153.0}=0x36527104
phy_chain_rx_lane_map_physical{225.0}=0x56410273
phy_chain_tx_lane_map_physical{225.0}=0x10274635
phy_chain_rx_lane_map_physical{233.0}=0x15740263
phy_chain_tx_lane_map_physical{233.0}=0x24351607
phy_chain_rx_lane_map_physical{241.0}=0x74015263
phy_chain_tx_lane_map_physical{241.0}=0x04152637
phy_chain_rx_lane_map_physical{249.0}=0x62037514
phy_chain_tx_lane_map_physical{249.0}=0x72453160
phy_chain_rx_lane_map_physical{161.0}=0x46510273
phy_chain_tx_lane_map_physical{161.0}=0x01653724
phy_chain_rx_lane_map_physical{169.0}=0x25743160
phy_chain_tx_lane_map_physical{169.0}=0x07216435
phy_chain_rx_lane_map_physical{177.0}=0x46510273
phy_chain_tx_lane_map_physical{177.0}=0x01652734
phy_chain_rx_lane_map_physical{185.0}=0x25743160
phy_chain_tx_lane_map_physical{185.0}=0x37016425
phy_chain_rx_lane_map_physical{193.0}=0x46510372
phy_chain_tx_lane_map_physical{193.0}=0x06153724
phy_chain_rx_lane_map_physical{201.0}=0x25743160
phy_chain_tx_lane_map_physical{201.0}=0x36017524
phy_chain_rx_lane_map_physical{209.0}=0x47601352
phy_chain_tx_lane_map_physical{209.0}=0x04152736
phy_chain_rx_lane_map_physical{217.0}=0x26453170
phy_chain_tx_lane_map_physical{217.0}=0x36027415

serdes_core_rx_polarity_flip_physical{33}=0x29
serdes_core_tx_polarity_flip_physical{33}=0xfe
serdes_core_rx_polarity_flip_physical{41}=0xb1
serdes_core_tx_polarity_flip_physical{41}=0xe8
serdes_core_rx_polarity_flip_physical{49}=0xca
serdes_core_tx_polarity_flip_physical{49}=0xb6
serdes_core_rx_polarity_flip_physical{57}=0x9b
serdes_core_tx_polarity_flip_physical{57}=0xdc
serdes_core_rx_polarity_flip_physical{65}=0x17
serdes_core_tx_polarity_flip_physical{65}=0x86
serdes_core_rx_polarity_flip_physical{73}=0x9b
serdes_core_tx_polarity_flip_physical{73}=0x55
serdes_core_rx_polarity_flip_physical{81}=0xa
serdes_core_tx_polarity_flip_physical{81}=0x6
serdes_core_rx_polarity_flip_physical{89}=0x9b
serdes_core_tx_polarity_flip_physical{89}=0x48
serdes_core_rx_polarity_flip_physical{1}=0xec
serdes_core_tx_polarity_flip_physical{1}=0x56
serdes_core_rx_polarity_flip_physical{9}=0x13
serdes_core_tx_polarity_flip_physical{9}=0xa6
serdes_core_rx_polarity_flip_physical{17}=0x5a
serdes_core_tx_polarity_flip_physical{17}=0xc6
serdes_core_rx_polarity_flip_physical{25}=0xf
serdes_core_tx_polarity_flip_physical{25}=0x4e
serdes_core_rx_polarity_flip_physical{97}=0x17
serdes_core_tx_polarity_flip_physical{97}=0x2e
serdes_core_rx_polarity_flip_physical{105}=0xce
serdes_core_tx_polarity_flip_physical{105}=0x7c
serdes_core_rx_polarity_flip_physical{113}=0xa
serdes_core_tx_polarity_flip_physical{113}=0x35

serdes_core_rx_polarity_flip_physical{121}=0xb9
serdes_core_tx_polarity_flip_physical{121}=0xef
serdes_core_rx_polarity_flip_physical{129}=0xe8
serdes_core_tx_polarity_flip_physical{129}=0xac
serdes_core_rx_polarity_flip_physical{137}=0xcb
serdes_core_tx_polarity_flip_physical{137}=0x9c
serdes_core_rx_polarity_flip_physical{145}=0x17
serdes_core_tx_polarity_flip_physical{145}=0x32
serdes_core_rx_polarity_flip_physical{153}=0xb9
serdes_core_tx_polarity_flip_physical{153}=0xaf
serdes_core_rx_polarity_flip_physical{225}=0xaa
serdes_core_tx_polarity_flip_physical{225}=0x7
serdes_core_rx_polarity_flip_physical{233}=0x31
serdes_core_tx_polarity_flip_physical{233}=0x47
serdes_core_rx_polarity_flip_physical{241}=0xe8
serdes_core_tx_polarity_flip_physical{241}=0x9e
serdes_core_rx_polarity_flip_physical{249}=0xec
serdes_core_tx_polarity_flip_physical{249}=0x1f
serdes_core_rx_polarity_flip_physical{161}=0x6a
serdes_core_tx_polarity_flip_physical{161}=0xd4
serdes_core_rx_polarity_flip_physical{169}=0x9e
serdes_core_tx_polarity_flip_physical{169}=0x7b
serdes_core_rx_polarity_flip_physical{177}=0x6a
serdes_core_tx_polarity_flip_physical{177}=0xcc
serdes_core_rx_polarity_flip_physical{185}=0x9e
serdes_core_tx_polarity_flip_physical{185}=0x58
serdes_core_rx_polarity_flip_physical{193}=0x6f
serdes_core_tx_polarity_flip_physical{193}=0x24
serdes_core_rx_polarity_flip_physical{201}=0x9e
serdes_core_tx_polarity_flip_physical{201}=0xdf
serdes_core_rx_polarity_flip_physical{209}=0x17
serdes_core_tx_polarity_flip_physical{209}=0xe9
serdes_core_rx_polarity_flip_physical{217}=0xec
serdes_core_tx_polarity_flip_physical{217}=0x68

dport_map_port_20=1
dport_map_port_24=2
dport_map_port_28=3
dport_map_port_32=4
dport_map_port_40=5
dport_map_port_44=6
dport_map_port_48=7
dport_map_port_52=8
dport_map_port_1=9
dport_map_port_5=10
dport_map_port_9=11
dport_map_port_13=12
dport_map_port_60=13
dport_map_port_64=14
dport_map_port_68=15
dport_map_port_72=16
dport_map_port_80=17
dport_map_port_84=18
dport_map_port_88=19
dport_map_port_92=20
dport_map_port_140=21
dport_map_port_144=22
dport_map_port_148=23
dport_map_port_152=24
dport_map_port_100=25
dport_map_port_104=26
dport_map_port_108=27
dport_map_port_112=28
dport_map_port_120=29
dport_map_port_124=30
dport_map_port_128=31
dport_map_port_132=32

#dport_map_port_38=33
#dport_map_port_118=34



core_clock_frequency=1325
dpr_clock_frequency=1000
device_clock_frequency=1325
port_flex_enable=1

#firmware load method, use fast load
load_firmware=0x2