Commit Graph

16 Commits

Author SHA1 Message Date
vmittal-msft
9a15221e46
Update CPU transmitted packets to queue 7 for chassis (#16254)
* Update CPU transmitted packets to TC = 7 for SONIC chassis

* Added new SOC property to permitted list
2023-08-29 18:33:16 -07:00
vmittal-msft
ecb4db58a9
Update PG headroom settings ports based on port speed/cable length (#14908)
* Update PG headroom settings ports based on port speed/cable length

* Updated XOFF settings to use chip level numbers than core

* Updated PG headroom based on uplink/downlink side

* fix for sonic-config-gen tests

* More fixes for unit test cases

* more test fixes

* Merged multiple functions into one
2023-05-19 08:19:27 -07:00
arista-nwolfe
93add6ed05
Add soc property sai_pfc_dlr_init_capability=0 to missing DNX SKUs (#15098) 2023-05-17 14:03:42 -07:00
vmittal-msft
5fc85f3274
Updated default ECN settings for T2 chassis (#14388)
Why I did it
Update ECN settings for T2 chassis

How I did it
Updated qos config file to load these settings during switch bootup

How to verify it
Verified on line card on T2 chassis
2023-05-04 10:01:09 -07:00
arista-nwolfe
990993e3f4
[devices/arista]: Added recycle ports required for egress mirroring (#13967)
Why I did it
Support Egress Mirroring on supported Arista platforms

How I did it
Add necessary soc properties for egress mirroring recycle ports to be created

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>
2023-04-06 10:58:01 -07:00
kenneth-arista
8ddfaec34f
[devices/arista] Update asic_port_name in Arista LCs (#14234)
Updated asic_port_names for all Arista LC SKUs to follow latest naming
conventions to remove redundant ASICx suffix. For
Arista-7800R3-48CQ2-C48, added the asic_port_name mapping.
2023-04-06 10:53:42 -07:00
Sambath Kumar Balasubramanian
71835385c1
sonic-buildimage Remove unused SAT port from arista configs. (#14167)
Why I did it
To fix aristanetworks/sonic#85

How I did it
Remove unnecessary SAT ports

How to verify it
Speed change from 400-100g without any error.
2023-03-09 15:54:20 -08:00
Song Yuan
bab8230444
Add QOS profiles for Arista SKUs (#13829) 2023-02-28 20:43:12 -08:00
Sambath Kumar Balasubramanian
d1bca210a6
sonic-buildimage Make changes to arista config.bcm files to support max cores (#13831)
To support 64 cores on arista skus. Fixes aristanetworks/sonic#77
Remapped recycle ports to lowers core port ids and set appl_param_nof_ports_per_modid to 64.
2023-02-23 17:54:43 -08:00
kenneth-arista
8c2d8ea4af
[device/arista] Reduce SDK stat polling freq in DNX devices (#13429)
Eariler the SDK stat polling was erroneously set to once every msec
which is far more frequent than required by SWSS. The new setting, which
is consistent with other vendor SKUs, is once a second. The net result
is reduced CPU MHz by syncd.
2023-01-30 14:13:01 -08:00
kenneth-arista
06d55b8027
[device/arista] Disabled polled_irq_mode for DNX SKUs (#13349)
Disabled polled_irq_mode for all Arista DNX devices as this mode
leads to excessive use of the CPU via an unneeded interrupt
polling thread.
2023-01-12 23:48:37 -08:00
Deepak Singhal
bf428fd9a7
DNX(J2/J2c/J2c+): Reserve Non-ECMP Fec Resource for Non-ECMP Route Nexthops/NBR Entries (#13076)
Why I did it
On DNX (J2/J2c/J2c+) platforms, Single Path Nexthops and ECMp Nexthop resources(FECs) are shared. BRCM SAI do not have partition of this resource, and hence more single path Nexthop entries, causes ECMP programming to fail in scaled setup.

How I did it
Broadcom provided SAI changes to reserve resources for single path nexthop entries(More details in CSP: https://brcmsemiconductor-csm.wolkenservicedesk.com/wolken-support/allcases/request-details?requestId=CS00012251649).
Along with SAI changes, they provided configurable Macro/flag to reserve NON_ECMP entries.
This PR is to add that flag in various sai.profile files wherever applicable.

PS: We are reserving 3072 single path Nexthop entries on each Linecard. Calculation is as follows.
Max Slots per chassis: 8
Max No of Ports(each LC): 64
MyIP/Subnet Entries per port: 4(v4/v6)
Nbr Entries Per port: 2(v4/v6)

Total Non_ECMP Count: 8x64x(4+2) = 3072

How to verify it
Without this change, the ECMP group count will be shown as Max_count in 'crm show resources all' command, and with this change the ECMP group count will be decreased by 24(3072/128).
2022-12-16 16:43:43 -08:00
Song Yuan
1fd2395f29
Fix port index for multi-asic (#13042)
Port indexes of front panel ports are not contiguous in multi-asic because we didn't distiguish between
front panel and internal ports, e.g., recycle ports. Fix this by assigning index to front panel port first
and then internal ports.
2022-12-16 09:12:36 -08:00
Maxime Lorrillere
298de5abef
Fix missing system_ref_core_clock_khz (#12663)
Add missing system_ref_core_clock_khz in Arista-7800R3A-36D2-C36 and Arista-7800R3A-36D2-C72
2022-12-13 22:20:16 -08:00
kenneth-arista
570e6fb28f
Add aggregate port_config.ini for Wolverine SKU (#12951)
Add missing aggregate port_config.ini needed by sonic-mgmt

Concatenate the ASIC specific port_config.ini from device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/[01] to create the aggregate file.
2022-12-13 22:02:14 -08:00
Sambath Kumar Balasubramanian
7ba1d25757
Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards. (#11813)
Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards.
2022-10-17 11:15:19 -07:00