Commit Graph

4 Commits

Author SHA1 Message Date
gechiang
e0209f745a
[202106]Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9293)
This is to address an issue where it was observed that SAI operations sometime may take a very long to time complete (over 45ms). It was determined that the ALPM distributed thread was causing this issue.
The fix is to disable this debug thread that has no functional purpose.

Preliminary tests looks fine. BGP neighbors were all up with proper routes programmed
interfaces are all up
Manually ran the fib test cases on 7050CX3 (TD3), TD2, TH, TH2, and TH3 based platforms and
thy all passed.
Note: the testing was done over 20201230 image and are porting this change to master branch.
No need to port this to 20201230 branch as a separate PR was already done for that branch. (#9190)

this PR is created to port the changes made by (#9199) but could not be cherry picked directly to 202106 branch.
2021-11-17 20:58:25 -08:00
gechiang
280df2ee46 BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8382)
* BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-25 12:11:23 -07:00
abdosi
b6efb49817
Update bcm soc property bcm_num_cos from 8 to 10 (#5314)
as needed by SAI 3.7 and above. Without this change
Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure
gets corrupted after warm-boot.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-04 07:40:17 -07:00
Michel Moriniaux
62e994d8ec [HWSKU] add Arista-7060CX-32S-T96C8 and Arista-7060CX-32S-Q24C8 (#2617)
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-T96C8 HWSKU

Added the bcm config files for a 96x25G+8x100G ToR

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
2019-03-15 09:45:17 -07:00