Commit Graph

210 Commits

Author SHA1 Message Date
zzhiyuan
d19a953e13
[Arista] Add 1x100G over 4 lanes configuration for 7060DX4 (#10655)
Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2022-04-25 08:11:32 -07:00
bingwang-ms
3fc3259a35
Define qos map AZURE_TUNNEL for QoS remapping of tunnel traffic (#10565)
* Add AZURE_TUNNEL map

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-04-25 15:06:10 +08:00
vmittal-msft
dd243c1024
Changes to support topology and port speed agnostic switch init for TD3 based platforms (#10587) 2022-04-18 15:19:22 -07:00
Junhua Zhai
04f810a346
[gearbox] use credo sai v0.7.5 (#10578)
The v0.7.5 has bug fix for the support of gearbox port and macsec counters. It also includes a owl firmware update with owl.lz4.fw.1.94.0.bin.

How I did it
Update credo sai url for v0.7.5
Update gearbox_config.json with using firmware owl.lz4.fw.1.94.0.bin instead of owl.lz4.fw.1.92.1.bin

How to verify it
Test gearbox port and macsec counter successfully on A7280.
2022-04-15 10:41:43 -07:00
Oleksandr Kozodoi
8c10c01bd8
Updated format of generating BUFFER_QUEUE in buffers_defaults templates (#9850)
This PR includes necessary changes for correct generating BUFFER_QUEUE values in DB. Changes are based on the schema.md

Why I did it
Change format of generating BUFFER_QUEUE in DB according to schema.md and yang-model.

Old format:
    "BUFFER_QUEUE": {
        "Ethernet0,Ethernet100,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet12,Ethernet120,Ethernet124,Ethernet16,Ethernet20,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet4,Ethernet40,Ethernet44,Ethernet48,Ethernet52,Ethernet56,Ethernet60,Ethernet64,Ethernet68,Ethernet72,Ethernet76,Ethernet8,Ethernet80,Ethernet84,Ethernet88,Ethernet92,Ethernet96|queue": {
            "profile": "profile"
        },
        "Ethernet0,Ethernet100,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet12,Ethernet120,Ethernet124,Ethernet16,Ethernet20,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet4,Ethernet40,Ethernet44,Ethernet48,Ethernet52,Ethernet56,Ethernet60,Ethernet64,Ethernet68,Ethernet72,Ethernet76,Ethernet8,Ethernet80,Ethernet84,Ethernet88,Ethernet92,Ethernet96|queue": {
            "profile": "profile"
        }
    },
New format:
    "BUFFER_QUEUE": {
        "Ethernet0|queue": {
            "profile": "profile"
        },
        "Ethernet0|queue": {
            "profile": "profile"
        },
        "Ethernet4|queue": {
            "profile": "profile"
        },
        "Ethernet4|queue": {
            "profile": "profile"
        },
        "Ethernet8|queue": {
            "profile": "profile"
        },
        "Ethernet8|queue": {
            "profile": "profile"
        },
        ...
    }
How I did it
Updated structure of buffers_defaults jinja templates.

Signed-off-by: Oleksandr Kozodoi <oleksandrx.kozodoi@intel.com>
2022-04-13 09:11:01 -07:00
byu343
da43edcf3e
[arista] Update serdes tuning values for 7800r3_48cqm2 (#9967)
This update the serdes tuning values for Arista 7800r3_48cqm2. The values are for the optical transceivers.
2022-04-12 15:53:35 -07:00
Nikola Dancejic
f2acf952fb
[device config] Adding configuration for default route fallback (#10465)
* [device config] Adding configuration for default route fallback
* Set sai_tunnel_underlay_route_mode attribute to fallback to default route if more specific route is unavailable.
2022-04-12 14:43:03 -07:00
byu343
58df23e1d7
[arista] Update serdes tuning values for 7280cr3 (#9966) 2022-04-05 09:49:26 -07:00
bingwang-ms
b9dd1df372
Update qos config to clear queues for bounced back traffic (#10176)
* Update qos config to clear queues for bounced back traffic

Signed-off-by: bingwang <bingwang@microsoft.com>
2022-04-05 22:32:25 +08:00
Kostiantyn Yarovyi
bf5f9c2918
[BFN] Update configuration files (#9913)
* [Barefoot] update switch-tna-sai.conf file

* remove deprecated conf files

* [Barefoot] update switch-tna-sai.conf file for Accton wedge100bf_32qs platform

* pdated switch-tna-sai.conf
2022-03-09 09:57:08 +05:30
abdosi
2bfad16ae1
Fix Headroom value for 7260C64 SKU (#10075)
Updated the Headroom value for (100G,5m) in 7260C64 SKU.
2022-02-24 10:06:43 -08:00
gechiang
ddfe87a71a
[BRCMSAI 6.0.0.13-1] Fix Cancun file directory at new location causing TD3 platform boot issue (#9922) 2022-02-07 08:56:06 -08:00
Samuel Angebault
20f7ae853b
Add platform.json configs for all denali SKUs (#9717) 2022-01-20 12:14:44 +05:30
Samuel Angebault
4e72757dd1
[Arista] Change default_sku for 7050QX-32S (#9730) 2022-01-16 07:36:22 +05:30
zzhiyuan
a6d0a27a18
[Arista] Increase switch PCIe timeout for 7060-cx32s (#9248)
Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
Why I did it
Arista 7060 platform has a rare and unreproduceable PCIe timeout that could possibly be solved with increasing the switch PCIe timeout value. To do this we'll call a script for this platform to increase the PCIe timeout on boot-up.

No issues would be expected from the setpci command. From the PCIe spec:

"Software is permitted to change the value in this field at any
time. For Requests already pending when the Completion
Timeout Value is changed, hardware is permitted to use either
the new or the old value for the outstanding Requests, and is
permitted to base the start time for each Request either on when
this value was changed or on when each request was issued. "

How I did it
Add "platform-init" support in swss docker similar to how "hwsku-init" is called, only this would be for any device belonging to a platform. Then the script would reside in device data folder.

Additionally, add pciutils dependency to docker-orchagent so it can run the setpci commands.

How to verify it
On bootup of an Arista 7060, can execute:
lspci -vv -s 01:00.0 | grep -i "devctl2"
In order to check that the timeout has changed.
2021-12-17 08:43:25 -08:00
Samuel Angebault
d499455752
[Arista] Update driver submodules (#9393)
- Use SfpOptoeBase by default to leverage new `sonic_xcvr` refactor
 - Add support for `Woodleaf` product
 - Move `libsfp-eeprom.so` to a different `.deb` package
 - Add new logrotate configuration for arista logs
 - Improve logging mechanism for the drivers (IO loglevel, fix syslog duplicates)
 - Initialize chassis cards in parallel
 - Refactor of `get_change_event` to fix interrupts treated as presence change
2021-12-08 11:33:36 -08:00
Song Yuan
27a6641fb8
[QoS, Buffer template][new HW SKU] Add qos config and buffer profile for Arista SKU (#8380) 2021-12-07 14:14:32 -08:00
byu343
a8cf990879
Add macsec_ipg setting to arista platforms (#9396) 2021-12-06 10:32:43 +08:00
abdosi
5c2423e974
Added 40G {300/40/5m} pg lookup profile for 7260 100G SKU (#9249)
What I did:
Added 40G {300/40/5m} profile for 7260 100G SKU
2021-11-24 18:56:30 -08:00
Prince Sunny
d6c3a9308c
[broadcom]: td2/td3 change cpu cos num to 10 (#9301)
bcm_num_cos=10 forces SDK default to map internal priority 0-7 to COS 0. It is now consistent with other SKUs.
2021-11-17 20:56:46 -08:00
zzhiyuan
989bd9deb0
[Arista] Fix 7060 flex HWSKU SFP ports and Ethernet8/1 (#9173)
* [Arista] Fix 7060 flex HWSKU SFP ports and Ethernet8/1

* [Arista] Fix polarity flips for Arista 7060 on non-leading intfs

Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2021-11-10 08:46:25 -08:00
gechiang
ef457ab13f
Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9199) 2021-11-09 07:21:57 -08:00
Qi Luo
add9b651b6
Add platform_asic file to each platform folder in sonic-device-data based package (#8542)
#### Why I did it
Add platform_asic file to each platform folder in sonic-device-data package. The file content will be used as the ground truth of mapping from PLATFORM_STRING to switch ASIC family.

One use case of the mapping is to prevent installing a wrong image, which targets for other ASIC platforms. For example, currently we have several ONIE images naming as sonic-*.bin, it's easy to mistakenly install the wrong image. With this mapping built into image, we could fetch the ONIE platform string, and figure out which ASIC it is using, and check we are installing the correct image.

After this PR merged, each platform vendor has to add one mandatory text file  `device/PLATFORM_VENDOR/PLATFORM_STRING/platform_asic`, with the content of the platform's switch ASIC family.

I will update https://github.com/Azure/SONiC/wiki/Porting-Guide after this PR is merged.

You can get a list of the ASIC platforms by `ls -b platform | cat`. Currently the options are
```
barefoot
broadcom
cavium
centec
centec-arm64
generic
innovium
marvell
marvell-arm64
marvell-armhf
mellanox
nephos
p4
vs
```

Also support
```
broadcom-dnx
```

#### How I did it

#### How to verify it
Test one image on DUT. And check the folders under `/usr/share/sonic/device`
2021-10-08 19:27:48 -07:00
byu343
677f31dac3
[arista] Add asic and phy configs for clearwater2ms (#8174)
* Add ASIC configs for clearwater2ms
* Add 100G gearbox configs for clearwater2ms
2021-10-04 19:11:57 -07:00
Ashok Daparthi-Dell
6cbdf11e53
SONIC QOS YANG - Remove qos tables field value refernce format (#7752)
Depends on Azure/sonic-utilities#1626
Depends on Azure/sonic-swss#1754

QOS tables in config db used ABNF format i.e "[TABLE_NAME|name] to refer fieldvalue to other qos tables.

Example:
Config DB:
"Ethernet92|3": {
"scheduler": "[SCHEDULER|scheduler.1]",
"wred_profile": "[WRED_PROFILE|AZURE_LOSSLESS]"
},
"Ethernet0|0": {
"profile": "[BUFFER_PROFILE|ingress_lossy_profile]"
},
"Ethernet0": {
"dscp_to_tc_map": "[DSCP_TO_TC_MAP|AZURE]",
"pfc_enable": "3,4",
"pfc_to_queue_map": "[MAP_PFC_PRIORITY_TO_QUEUE|AZURE]",
"tc_to_pg_map": "[TC_TO_PRIORITY_GROUP_MAP|AZURE]",
"tc_to_queue_map": "[TC_TO_QUEUE_MAP|AZURE]"
},

This format is not consistent with other DB schema followed in sonic.
And also this reference in DB is not required, This is taken care by YANG "leafref".

Removed this format from all platform files to consistent with other sonic db schema.
Example:
"Ethernet92|3": {
"scheduler": "scheduler.1",
"wred_profile": "AZURE_LOSSLESS"
},

Dependent pull requests:
#7752 - To modify platfrom files
#7281 - Yang model
Azure/sonic-utilities#1626 - DB migration
Azure/sonic-swss#1754 - swss change to remove ABNF format
2021-09-28 09:21:24 -07:00
Samuel Angebault
f899a82864
[Arista] Fix Clearwater2 phy initialization when no configuration is provided (#8271)
Why I did it
Fix an issue on the Clearwater2 linecard.
When the linecard is started with a fresh image without configuration, phys would not be initialized.

How I did it
Added default_sku for Clearwater2 which prevents config-setup from failing to create a default config_db.json.
Added some extra logic in the phy-credo-init script to run the phy_config.sh of the hwsku pointed by default_sku if the DEVICE_METADATA.localhost.hwsku information is not populated in CONFIG_DB.

How to verify it
Booting an image with this change and without configuration will lead to the phys being initialized using the phy_config.sh from default_sku.
2021-09-09 13:03:22 -07:00
Samuel Angebault
2e4f473237
[Arista] Update platform library submodules (#8594)
- Disable health monitoring of `psu.voltage` until support is implemented
 - chassis: disable provisioning bit once linecard has booted
 - chassis: fix issue in `show version` when running as `admin`
 - chassis: fix race when reading an eeprom before it's available
 - chassis: implement `get_all_asics` call
 - api: fix `ChassisBase.get_system_eeprom_info` implementation
 - api: add missing thermal condition and info
 - api: fix return value of `ChassisBase.set_status_led`
 - sfp: introduce SfpOptoeBase implementation used based on configuration knob
 - psu: rely on pmbus to read input/output status when other mechanism is missing
 - misc: other refactors and improvements
2021-09-01 01:52:57 -07:00
Ying Xie
7735e8a792
[7050] define hwsku.json for Arista-7050QX-32S-S4Q31 to skip SFP checks for first 4 ports (#8624)
Why I did it
The first 4 ports on this dut are breakout ports. They might not always be connected in lab. Mark them as 'RJ45' to skip the SFP check since they are by default disabled.

How to verify it
run platform test_reboot.py

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2021-08-31 17:15:03 -07:00
Song Yuan
d53c6248e4
[chassis] Set LAG Id range for 7800 chassis (#8052)
Configure LAG Id range in chassisdb.conf for 7800 chassis.
2021-08-30 16:04:07 -07:00
byu343
85a671f5af
[arista] Add gearbox configs for Arista 7280cr3mk (#8146)
* Add gearbox support for 7280cr3mk and its variants
2021-08-26 15:30:11 +08:00
Samuel Angebault
18cd32a218
[Arista] Add VOQ information for Clearwater2 (#8508)
This change introduces 3 columns in the port_config.ini file.
These are coreId, corePortId and numVoq.
The ports for inband and recirc were also renamed properly.
2021-08-20 16:42:56 -07:00
zzhiyuan
144851fea8
[Arista] Add dynamic port breakout hwsku to platforms (#7975)
Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
Why I did it
To support dynamic port breakout Broadcom configurations on Arista platforms.

How I did it
Updated platform.json for platforms and added new hwsku, Broadcom config, and hwsku.json for dynamic port breakout usage.

The name of the new hwsku name used is very similar to the platform name (platform x86_64-arista_7050_qx32s hwsku Arista-7050QX-32S) as the flex hwsku is meant to be the default in the future.

How to verify it
Boot up device with the new hwsku, interfaces are up.
Change hwsku.json with new default breakout mode and reload device, breakout will have successfully been applied.
2021-08-16 07:03:50 -07:00
gechiang
8e903f4566
BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8382)
* BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-10 19:03:22 -07:00
Neetha John
9acf0744a1
Revert "Revert "Update default cable len to 0m for TD2"" (#8354)
* Update default cable len to 0m for TD2 (#8298)
* Update sonic-cfggen tests with the correct cable len

Signed-off-by: Neetha John <nejo@microsoft.com>

As part of the buffer reclamation efforts for TD2, setting the default cable len to 0m which means unused ports will have a cable len of 0m.

Why I did it
To align with the changes in Azure/sonic-swss#1830

How to verify it
- With the default cable len set to 0m and the associated changes in swss, CABLE_LENGTH table had '0m' set for unused ports and accordingly more space was reserved for the shared pool
- Cfggen tests passed with the cable len update
2021-08-06 10:36:10 -07:00
Neetha John
4268662486
Revert "Update default cable len to 0m for TD2 (#8298)" (#8320)
This reverts commit 93e939b8af.
2021-08-03 14:07:41 -07:00
Neetha John
93e939b8af
Update default cable len to 0m for TD2 (#8298)
Signed-off-by: Neetha John <nejo@microsoft.com>

As part of the buffer reclamation efforts for TD2, setting the default cable len to 0m which means unused ports will have a cable len of 0m.

Why I did it
To align with the changes in Azure/sonic-swss#1830

How to verify it
With the default cable len set to 0m and the associated changes in swss, CABLE_LENGTH table had '0m' set for unused ports and accordingly more space was reserved for the shared pool
2021-08-02 09:09:22 -07:00
Samuel Angebault
6ae5e1d6a1
[Arista] Update platform library submodules (#8281)
- Improve chassis linecard restartability
- Fix 'show system-health' cli by adding non standard api
- Fix ledd crash on linecards with Recycle/Inband ports
- Refactor DPM management and add ADM1266 support
- Add state machine to update DPM RTC clock periodically
- Improve xcvr temperature reporting
- Fix lane mapping and `default_sku` for `x86_64-arista_7170_32c` platform
- Fix `7170-32C/CD` platform definition
2021-07-30 17:10:45 -07:00
Samuel Angebault
545c69180f
[Arista] Improve 7280CR3 platform configurations (#8234)
Introduce Arista-7280CR3-C32P4 and Arista-7280CR3-C32D4 hwskus.
Remove deprecated fancontrol configurations.
Add pcie.yaml configurations
Add missing default_sku files
2021-07-24 13:42:27 -07:00
vmittal-msft
e7cec0928b
Updated SONIC buffer pool settings to accomodate SAI adjustment for Arista-7050CX3-32S-C32 (#8159) 2021-07-16 12:32:16 -07:00
Samuel Angebault
17f0217f30
[Arista] Chassis device configurations (#7529)
Add configurations for the following chassis elements

Fabrics 7804R3-FM, 7808R3-FM and 7808R3A-FM
Linecard 7800R3-48CQ2
Supervisor 7800-SUP*
2021-06-30 18:16:20 -07:00
gechiang
6fc279b7c1
Add BRCM SOC Property to not count ACL drops towards interface RX_DRP… (#7945)
* Add BRCM SOC Property to not count ACL drops towards interface RX_DRP counter for 7050CX3 and 7260CX3 DualToR platforms
2021-06-23 18:09:47 -07:00
judyjoseph
3ad830eb49
New sonic-buildimage images for Broadcom DNX ASIC family. (#7598)
Introduce new sonic-buildimage images for Broadcom DNX ASIC family.

sonic-broadcom-dnx.bin
sonic-aboot-broadcom-dnx.swi

How I did it

NO CHANGE to existing make commands

make init; make configure PLATFORM=broadcom;  make target/sonic-aboot-broadcom.swi; make  target/sonic-broadcom.bin

The difference now is that it will result in new broadcom images for DNX asic family as well. 

sonic-broadcom.bin, sonic-broadcom-dnx.bin
sonic-aboot-broadcom.swi, sonic-aboot-broadcom-dnx.swi

Note: This PR also adds support for Broadcom SAI 5.0 (based on 1.8 SAI ) for DNX based platform + changes in platform x86_64-arista_7280cr3_32p4 bcm config files and platform_env.conf files
2021-06-22 11:12:22 -07:00
abdosi
9f4359804e
Updated 7260 64x100 MMU Profile. (#7849)
What I did:

Updated 7260 MMU Profile based on latest MSFT Tier 1 Tomahawk2_MMU_Setting_48x100G_40m_16x100G_300m_v1.0 and
TH2_PGHdrm_MSFT.

How I verify:
Made sure image is up/traffic is flowing/mmu dump looked fine.
SAI qos test need will be updated to support this SKU.
2021-06-15 22:06:48 -07:00
Andriy Kokhan
12a04704ad
[Arista] Added pcie.yaml for x86_64-arista_7170_32cd (#7788)
Process pcied failed on Arista-7170-32CD-C32
```
root@sonic:/# supervisorctl 
chassis_db_init                  EXITED    Jun 03 08:48 AM
dependent-startup                EXITED    Jun 03 08:48 AM
ledd                             RUNNING   pid 28, uptime 3:07:49
lm-sensors                       EXITED    Jun 03 08:48 AM
pcied                            FATAL     Exited too quickly (process log may have details)
```

Signed-off-by: Andriy Kokhan <andriyx.kokhan@intel.com>
2021-06-09 22:08:47 -07:00
Ying Xie
b2a2cf0750
[7050] updating 7050 MMU configurations (#7801)
Why I did it
7050 S4Q31 mmu configuration is missing ALPM configurations, causing not enough memory reserved for routes. Orchagent crashes on a nightly testbed with 6400 route entries.

How I did it
Add the missing ALPM configurations.

How to verify it
Load the configuration on testbed and verified new configuration exists and no more crash.

Signed-off-by: Ying Xie ying.xie@microsoft.com
2021-06-05 21:50:01 -07:00
Neetha John
239a1cc1df
Rename AristaQX-32S skus (#7751)
This PR contains the following changes
Original Arista-7050-QX-32S sku (32x40G ports) has been renamed to Arista-7050QX32S-Q32
Arista-7050-QX-32S is symlinked to Arista-7050QX-32S-S4Q31 (4x10G, 31x40G ports)

Signed-off-by: Neetha John <nejo@microsoft.com>
2021-05-28 22:46:49 -07:00
Ying Xie
a42aa3d316
[MMU] define T1 MMU configuratino for Arista-7260CX3-Q64 (#7718)
Why I did it
Arista-7260CX3-Q64 is missing T1 MMU configuration.

How I did it
Define T1 MMU configuration for Arista-7260CX3-Q64.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2021-05-27 08:20:07 -07:00
Neetha John
6f884b7278
Update PG profile settings for Arista-7050QX-32S-S4Q31 (#7673)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
PG profile settings need to be aligned with Arista-7050-QX-32S

How I did it
Copy over the current settings from Arista-7050-QX-32S and define params for 10G and 1G speeds as well
2021-05-24 17:15:37 -07:00
Neetha John
f744f9354c
Update MMU and QOS settings for Arista-7050QX-32S-S4Q31 (#7672)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
Need proper MMU and Qos settings for Arista-7050QX-32S-S4Q31

How I did it
Updated the settings based on Arista-7050-QX-32S
2021-05-24 09:33:33 -07:00
vmittal-msft
aae315faaf
Updated MMU settings for Arista-7050CX3-32S-C32 T1 topology (#7597) 2021-05-12 21:28:19 -07:00