Commit Graph

20 Commits

Author SHA1 Message Date
DavidZagury
9d1c1659bd
[Mellanox] Update SKUs to enable SDK dumps (#7708)
- Why I did it
To create SDK dump on Mellanox devices when SDK event has occurred.

- How I did it
Set the SKUs keys needed to initialize the feature in SAI.

- How to verify it
Simulate SDK event and check that dump is created in the expected path.
2021-06-21 16:41:18 +03:00
madhanmellanox
4e206ba36e
Adding new SKU Mellanox-SN4600C-C4 (#7815)
Add new SKU of SN4600C switch: Mellanox-SN4600c-c64

Co-authored-by: Madhan Babu <madhan@r-build-sonic06.mtr.labs.mlnx>
2021-06-17 10:04:38 -07:00
Kebo Liu
629f4459d7
[Mellanox] Align PSU fan name in platform.json with latest change in PR #7490 (#7557)
The PSU fan name convention was changed from "psu_{}_fan_{}" to "psu{}_fan{}" in PR #7490, platform.json need to be changed and aligned.
2021-05-07 09:42:40 -07:00
Kebo Liu
5ac048f7e7
[Mellanox] Enhance the platform.json with adding more platform device facts. (#7495)
#### Why I did it

Current platform.json lacks some peripheral device related facts, like chassis/fan/pasu/drawer/thermal/components names, numbers, etc.

#### How I did it

Add platform device facts to the platform.json file

Signed-off-by: Kebo Liu <kebol@nvidia.com>
2021-05-03 12:22:13 -07:00
Nazarii Hnydyn
39b1c12731
[Mellanox]: Fix PCIEd config for SN4600c (#6892)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2021-02-26 00:28:32 -08:00
Sangita Maity
18263c99dd
[DPB|master] Update Dynamic Port Breakout Logic for flexible alias support a… (#6831)
To fix [DPB| wrong aliases for interfaces](https://github.com/Azure/sonic-buildimage/issues/6024) issue, implimented flexible alias support [design doc](https://github.com/Azure/SONiC/pull/749)

> [[dpb|config] Fix the validation logic of breakout mode](https://github.com/Azure/sonic-utilities/pull/1440) depends on this

#### How I did it

1. Removed `"alias_at_lanes"` from port-configuration file(i.e. platfrom.json) 
2. Added dictionary to "breakout_modes" values. This defines the breakout modes available on the platform for this parent port, and it maps to the alias list. The alias list presents the alias names for individual ports in order under this breakout mode.
```
{
    "interfaces": {
        "Ethernet0": {
            "index": "1,1,1,1",
            "lanes": "0,1,2,3",
            "breakout_modes": {
                "1x100G[40G]": ["Eth1"],
                "2x50G": ["Eth1/1", "Eth1/2"],
                "4x25G[10G]": ["Eth1/1", "Eth1/2", "Eth1/3", "Eth1/4"],
                "2x25G(2)+1x50G(2)": ["Eth1/1", "Eth1/2", "Eth1/3"],
                "1x50G(2)+2x25G(2)": ["Eth1/1", "Eth1/2", "Eth1/3"]
            }
        }
}
```
#### How to verify it
`config interface breakout`

Signed-off-by: Sangita Maity <samaity@linkedin.com>
2021-02-26 00:13:33 -08:00
shlomibitton
2076260180
Fix for Mellanox-SN4600C-D112C8 SKU (#6817)
- Why I did it
Mellanox-SN4600C-D112C8 SKU is not configured properly.
It should have 112 50G interfaces and 8 100G interfaces as described on this PR.

- How I did it
Modify sai_profile, port_config.ini and hwsku.json for DPB.

- How to verify it
Apply this HwSKU to a MSN4600C Mellanox platform.

Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2021-02-18 17:44:03 +02:00
Stephen Sun
7790a74d90
Support shared headroom pool for Microsoft SKUs (#6366)
- Why I did it
Support shared headroom pool

Signed-off-by: Stephen Sun stephens@nvidia.com

- How I did it
Port configurations for SKUs based on 2700/3800 platform from 201911
For SN3800 platform:
C64: 32 100G down links and 32 100G up links.
D112C8: 112 50G down links and 8 100G up links.
D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.
For SN2700 platform:
D48C8: 48 50G down links and 8 100G up links
C32: 16 100G downlinks and 16 100G uplinks
Add configuration for Mellanox-SN4600C-D112C8
112 50G down links and 8 100G up links.

- How to verify it
Run regression test.
2021-02-16 08:53:40 -08:00
Vadym Hlushko
ece8297cf8
[DPB] [Mellanox] added capability files for SN4600C platform (#6061)
- Why I did it
platform.json and hwsku.json files are required for a feature called Dynamic Port Breakout

- How I did it
Created capability files according to platform specification SN4600C

- How to verify it
Full qualification requires bugs fixes reported under sonic-buildimage

NOTE: breakout to 4 is currently not available as of missing functionality in DPB implementation.

Signed-off-by: Vadym Hlushko <vadymh@nvidia.com>
2021-01-17 11:13:54 +02:00
Stephen Sun
e010d83fc3
[Dynamic buffer calc] Support dynamic buffer calculation (#6194)
**- Why I did it**
To support dynamic buffer calculation.
This PR also depends on the following PRs for sub modules
- [sonic-swss: [buffermgr/bufferorch] Support dynamic buffer calculation #1338](https://github.com/Azure/sonic-swss/pull/1338)
- [sonic-swss-common: Dynamic buffer calculation #361](https://github.com/Azure/sonic-swss-common/pull/361)
- [sonic-utilities: Support dynamic buffer calculation #973](https://github.com/Azure/sonic-utilities/pull/973)

**- How I did it**
1. Introduce field `buffer_model` in `DEVICE_METADATA|localhost` to represent which buffer model is running in the system currently:
    - `dynamic` for the dynamic buffer calculation model
    - `traditional` for the traditional model in which the `pg_profile_lookup.ini` is used
2. Add the tables required for the feature:
   - ASIC_TABLE in platform/\<vendor\>/asic_table.j2
   - PERIPHERAL_TABLE in platform/\<vendor\>/peripheral_table.j2
   - PORT_PERIPHERAL_TABLE on a per-platform basis in device/\<vendor\>/\<platform\>/port_peripheral_config.j2 for each platform with gearbox installed.
   - DEFAULT_LOSSLESS_BUFFER_PARAMETER and LOSSLESS_TRAFFIC_PATTERN in files/build_templates/buffers_config.j2
   - Add lossless PGs (3-4) for each port in files/build_templates/buffers_config.j2
3. Copy the newly introduced j2 files into the image and rendering them when the system starts
4. Update the CLI options for buffermgrd so that it can start with dynamic mode
5. Fetches the ASIC vendor name in orchagent:
   - fetch the vendor name when creates the docker and pass it as a docker environment variable
   - `buffermgrd` can use this passed-in variable
6. Clear buffer related tables from STATE_DB when swss docker starts
7. Update the src/sonic-config-engine/tests/sample_output/buffers-dell6100.json according to the buffer_config.j2
8. Remove buffer pool sizes for ingress pools and egress_lossy_pool
   Update the buffer settings for dynamic buffer calculation
2020-12-13 11:35:39 -08:00
Kebo Liu
1158701edc
add pcied config files for mellanox platform (#5669)
This PR has a dependency on community change to move PCIe config files from $PLATFORM/plugin folder to $PLATFORM/ folder
- Why I did it
To support PCIed daemon on Mellanox platforms
- How I did it
Add PCIed config yaml files for all Mellanox platforms
Update pmon daemon config files for SimX platforms
2020-11-02 19:45:36 -08:00
Nazarii Hnydyn
5486f87afc
[Mellanox] Update platform components config files. (#5685)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2020-10-25 19:44:37 +02:00
Nazarii Hnydyn
e2b4afc438
[Mellanox] Update platform components config files. (#5360)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2020-09-13 10:23:22 +03:00
Stephen Sun
54fcdbb380
Support single ingress pool for MSFT SKUs and optimize headroom calculation (#4686)
Calculate pool size in t1 as 24 * downlink port + 8 * uplink port

- Take both port and peer MTU into account when calculating headroom
- Worst case factor is decreased to 50%
- Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports
- Mellanox-SN2700 (C32)
  - t0: 16 * 100G/5m + 16 * 100G/40m
  - t1: 16 * 100G/40m + 16 * 100G/300m

Signed-off-by: Stephen Sun <stephens@mellanox.com>

Co-authored-by: Stephen Sun <stephens@mellanox.com>
2020-08-13 13:12:09 +03:00
Junchao-Mellanox
e1f7fb135b
[Mellanox] Add system health configuration file for Mellanox platforms (#4834)
The new feature system health support a platform based configuration file. Add configuration files for all Mellanox platform.

Add a configuration file for SN2700, other platform will use a soft link to it.
2020-07-13 10:20:22 -07:00
shlomibitton
e666bf8490 [Mellanox] Add a new SKU Mellanox-SN4600C-D112C8 (#4833)
Add related files to the device folder:

buffer config templates
pg lookup profile
port_config.ini
sai profile
sensor conf
plugins

Co-authored-by: Stephen Sun <stephens@mellanox.com>
2020-07-12 18:08:52 +00:00
Junchao-Mellanox
563a0fd21e
[Mellanox] Change port index in port_config.ini to 1-based (#4781)
* Change port index in port_config.ini to 1-based
* Add default port index to port_config.ini, change platform plugins to accept 1-based port index
* fix port index in sfp_event.py
2020-06-23 17:21:36 -07:00
shlomibitton
ea63f3e4b2
[mellanox]: Fix for MSN4600C sensors (#4754)
Signed-off-by: Shlomi Bitton <shlomibi@mellanox.com>
2020-06-12 16:08:27 -07:00
Junchao-Mellanox
5e6c20481d
[Mellanox] Enhancement for fan led management (#4437) 2020-05-13 10:01:32 -07:00
shlomibitton
b6291372d9
[Mellanox] Add a new Mellanox platform x86_64-mlnx_msn4600c and new SKU ACS-MSN4600C (#4483)
* New SKU support for MSN4600C

Signed-off-by: Shlomi Bitton <shlomibi@mellanox.com>
2020-04-30 00:30:11 -07:00