Commit Graph

4 Commits

Author SHA1 Message Date
Nazarii Hnydyn
845bb80a3c
[ppi]: Enable global port late create for all Mellanox HWSKUs. (#16945)
HLD: sonic-net/SONiC#1084

To improve FAST reboot dataplane downtime

Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2023-11-01 21:50:14 -07:00
Vadym Hlushko
521a86b2de
[Mellanox] Add mlxtrace to techsupport (#15961)
- Why I did it
Added the fwtrace config files in order to be able to call the mlxstrace utility during the show techsupport dump.

Work item tracking
Microsoft ADO (number only):

- How I did it
Added fwtrace config files. Added path to these files to sai.profile for each mlnx device.

- How to verify it
Execute the show techsupport command and check if mlxstrace output is in system dump.

Signed-off-by: vadymhlushko-mlnx <vadymh@nvidia.com>
2023-08-03 11:36:58 +03:00
Vivek
d3f2d06117
[Mellanox] Add Copyright Headers for missing files (#15136)
Added NVIDIA copyright to missing files under platform/mellanox & device/mellanox
Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com>
2023-05-25 07:55:44 +03:00
Vivek
a68ce12dd6
[Mellanox] [SKU] Added Mellanox-SN4700-A96C8V8 SKU (#12347)
- Why I did it
A new SKU for MSN4700 Platform i.e. Mellanox-SN4700-V16A96

Requirements:

Breakout:
Port 1-24: 4x25G(4)[10G,1G]
Port 25-28: 2x100G[200G,50G,40G,25G,10G,1G]
Port 29-32: 2x200G[100G,50G,40G,25G,10G,1G]
Downlinks: 96 (1-24) + 4 (25-28)
Uplinks: 4 (29-32)
Shared Headroom: Enabled
Over Subscribe Ratio: 1:4
Default Topology: T0
Default Cable Length for T1: 5m
VxLAN source port range set: No
Static Policy Based Hashing Supported: No

Additional Details:
QoS params: The default ones defined in qos_config.j2 will be applied
Small Packet Percentage: Used 50% for traditional buffer model Note: For dynamic model, the value defined in LOSSLESS_TRAFFIC_PATTERN|AZURE|small_packet_percentage is used
SKU was drafted under the assumption that the downlink ports uses xcvr's that will only support the first 4 lanes of the physical port they are connected to. Hence for the ports 1-24, the last four lanes are not used
Cable Lengths used for generating buffer_defaults_{t0,t1}.j2 values

Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com>
2022-10-20 09:50:07 +03:00