Commit Graph

206 Commits

Author SHA1 Message Date
Junchao-Mellanox
6fd31a5018
[Mellanox] Update platform files for SN4800 (#8540)
- Why I did it
Update platform data files for SN4800 to support chassis management

- How I did it
Update pcie.yml
Update sensors.conf
Update platform.json

- How to verify it
Run platform test suite in sonic-mgmt
2021-08-25 21:13:07 +03:00
Alexander Allen
7e4c4e2b95
[Mellanox] Add 2x100G and 4x50G breakout modes to MSN4410 platform (#8419)
- Why I did it
The MSN4410 platform was missing 2x100G and 4x50G supported breakout modes in platform.json

- How I did it
Added the aforementioned breakout modes to platform.json

- How to verify it
Run show interface breakout on a MSN4410 and verify that 2x100G and 4x50G are listed in the supported breakout modes for ports 1-24.
2021-08-22 15:53:03 +03:00
tomer-israel
aa6d4574e3
[Mellanox] fix syseeprom info values on mellanox simulator platforms msn4700 and msn4800 (#8387)
#### Why I did it
The values of the syseeprom were not valid

#### How I did it
I took the correct hexdump values from a real switch and created this hex file again

#### How to verify it
decode-syseeprom will display the new values
2021-08-15 01:12:32 -07:00
madhanmellanox
3ad4096ea2
Adding SKU Mellanox-SN3800-D100C12S2 (#8441)
* Adding SKU Mellanox-SN3800-D100C12S2

Co-authored-by: Madhan Babu <madhan@l-csi-0241l.mtl.labs.mlnx>
2021-08-13 19:17:38 -07:00
Kebo Liu
9d2ccda1ec
[Mellanox] Add new sensor conf to support SN4410 A1 system (#8379)
#### Why I did it

New SN410 A1 system has a different sensor layout with A0 system, needs a new sensor conf file to support it.

#### How I did it

Since the SN4410 A1 system use exactly the same sensor layout as the SN4700 A1 system, so add a symbol link linking to the SN4700 A1 sensor conf file to reuse.

#### How to verify it

Run sensor test against the SN4410 A1 system;
Run platform related regression test against the SN4410 A1 system
2021-08-11 17:31:58 -07:00
Alexander Allen
5259af2e2b
[mellanox] remove 2x40G and 4x40G breakout modes due to no hardware support (#8280)
Mellanox platforms do not support 2x40G or 4x40G breakout modes.

Signed-off-by: Alexander Allen <arallen@nvidia.com>
2021-08-01 13:24:26 -07:00
Vivek Reddy
b0620ee055
[Mellanox] [SKU] Fix the shared headroom for 4600C-C64 SKU (#8242)
Removed ingress_lossy_pool from the BUFFER_POOL list
Fx the the egress_lossless_pool_size value

Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com>
2021-07-29 08:21:28 -07:00
Vivek Reddy
69ed4417ca
[Mellanox] [master] Added D48C40 SKU for 4600C platform (#8201)
*Added new SKU for SN4600C Platform: Mellanox-SN4600C-D48C40
Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com>
2021-07-19 10:07:35 -07:00
Vivek Reddy
f95f8ead9e
[Mellanox][master][SKU] sonic interface names are aligned to 4 instead of 8 for 4600/4600C platforms (#8155)
*Edited platform.json for 4600 & 4600C
*Edited hwsku.json and port_config.ini files for all the SKU's present under these platforms
Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com>
2021-07-13 18:59:48 -07:00
DavidZagury
9d1c1659bd
[Mellanox] Update SKUs to enable SDK dumps (#7708)
- Why I did it
To create SDK dump on Mellanox devices when SDK event has occurred.

- How I did it
Set the SKUs keys needed to initialize the feature in SAI.

- How to verify it
Simulate SDK event and check that dump is created in the expected path.
2021-06-21 16:41:18 +03:00
Alexander Allen
d2e62af85d
[device][mellanox] Fix supported breakout modes on MSN4410 (#7853)
- Why I did it
The default breakout mode according to hwsku.json for the MSN4410 is 1x400G and this is not a supported breakout mode according to its platform.json

This causes a conflict on boot of this platform and no containers on the switch will init successfully.

- How I did it
Referenced the platform specification files and updated platform.json

- How to verify it
Install master version of SONiC on MSN4410
Boot switch and verify swss is successfully running using docker ps
2021-06-20 19:35:44 +03:00
madhanmellanox
4e206ba36e
Adding new SKU Mellanox-SN4600C-C4 (#7815)
Add new SKU of SN4600C switch: Mellanox-SN4600c-c64

Co-authored-by: Madhan Babu <madhan@r-build-sonic06.mtr.labs.mlnx>
2021-06-17 10:04:38 -07:00
Stephen Sun
80d01f2f9a
[Mellanox] Enhance Python3 support for platform API (#7410)
- Why I did it
Enhance the Python3 support for platform API. Originally, some platform APIs call SDK API which didn't support Python 3. Now the Python 3 APIs have been supported in SDK 4.4.3XXX, Python3 is completely supported by platform API

- How I did it
Start all platform daemons from python3
1. Remove #/usr/bin/env python at the beginning of each platform API file as the platform API won't be started as daemons but be imported from other daemons.
2. Adjust SDK API calls accordingly

- How to verify it
Manually test and run regression platform test

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2021-06-15 17:57:48 +03:00
Stephen Sun
132420095a
[Mellanox] Support buffer configuration for 2km cables (#7337)
#### Why I did it
Support 2km cables for Microsoft SKUs

#### How I did it
1. Update pg_profile_lookup.ini with 2000m cable supported
2. Update buffer configuration for t1 with uplink cable 2000m
  - For SN3800 platform:
    - C64:
      - t0: 32 100G down links and 32 100G up links.
      - t1: 56 100G down links and 8 100G up links with 2 km cable.
    - D112C8: 112 50G down links and 8 100G up links.
    - D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
    - D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.
  - For SN2700 platform:
    - D48C8: 48 50G down links and 8 100G up links.
    - C32:
      - t0: 16 100G down links and 16 100G up links.
      - t1: 24 100G down links and 8 100G up links with 2 km cable.
  - For SN4600C platform:
    - D112C8: 112 50G down links and 8 100G up links.

#### How to verify it
Run regression test
2021-05-30 20:07:10 -07:00
Kebo Liu
bf21dbce87
[Mellanox] Add support for MSN4600 A1 system (#7732)
Add new sensor conf for MSN4600 A1 system
Add a Mellanox hw-management patch to support MSN4600 A1 system
2021-05-27 09:52:45 -07:00
Kebo Liu
953f91343a
[Mellanox] Update the Spectrum-2 platform PSU sensor's label in the sensor conf file (#7706)
#### Why I did it
The label for PSU related sensors on the Spectrum-2 platform is not aligned with the physical location of the PSU. 

#### How I did it
Update the label in the sensor conf file for those relevant platforms

Signed-off-by: Kebo Liu <kebol@nvidia.com>
2021-05-25 10:41:53 -07:00
tomer-israel
b1a7f670d7
[Mellanox] Add initial support for SN4800 for simulation device (#7448)
#### Why I did it
Add initial support of SN4800 platform for Mellanox ASIC simulation device.
NOTE: This is work in progress and not full support of the platform.

#### How I did it
Add new folders for SN4800 with zero ports based on SN4700 Spectrum-3 switch.
2021-05-18 09:34:33 -07:00
Prince Sunny
ea80325726
Vxlan src port range for breakout SKU (#7612)
*Extended Vxlan src port range for lab breakout SKU - Mellanox-SN3800-D112C8
2021-05-14 08:58:51 -07:00
tomer-israel
3ccc45f5b8
[Mellanox] Add initial support for SN4800 platform (#7447)
- Why I did it
Add initial support of SN4800 platform .
NOTE: This is work in progress and not full support of the platform.

- How I did it
Add new folders for SN4800 with zero ports based on SN4700 Spectrum-3 switch.

- How to verify it
Simulator device was tested. See #7448
2021-05-12 22:21:04 +03:00
Kebo Liu
629f4459d7
[Mellanox] Align PSU fan name in platform.json with latest change in PR #7490 (#7557)
The PSU fan name convention was changed from "psu_{}_fan_{}" to "psu{}_fan{}" in PR #7490, platform.json need to be changed and aligned.
2021-05-07 09:42:40 -07:00
Junchao-Mellanox
a795bc0b8e
[Mellanox] Support new sensor conf file for MSN4700 A1/A0 (#7535)
#### Why I did it

MSN4700 A1/A0 used different sensor chip but keep the existing platform name *x86_64-mlnx_msn4700-r0*, this is a workaround to replace the sensor conf on MSN4700 A1/A0

#### How I did it

Use a shell script to get the sensor conf path and copy that files to /etc/sensors.d/sensors.conf
2021-05-06 10:13:26 -07:00
Andriy Yurkiv
e52fdcfd72
[Mellanox] Add support to VXLAN src port range setting via SAI profile for r SN3800-D28C49S1 (#7500)
- Why I did it
Enable VXLAN src port range configuration via SAI profile for Mellanox-SN3800-D28C49S1 SKU

- How I did it
Added SAI_VXLAN_SRCPORT_RANGE_ENABLE=1 configuration to appropriate sai.profile

Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>
2021-05-04 17:34:33 +03:00
Kebo Liu
5ac048f7e7
[Mellanox] Enhance the platform.json with adding more platform device facts. (#7495)
#### Why I did it

Current platform.json lacks some peripheral device related facts, like chassis/fan/pasu/drawer/thermal/components names, numbers, etc.

#### How I did it

Add platform device facts to the platform.json file

Signed-off-by: Kebo Liu <kebol@nvidia.com>
2021-05-03 12:22:13 -07:00
Andriy Yurkiv
21009be840
[devices][hwsku] add support to VXLAN src port range feature (#7394)
Enable VXLAN src port range configuration via SAI profile
2021-04-29 10:05:02 -07:00
Junchao-Mellanox
e58348733d
[Mellanox] Fix platform json for MSN2100 (#7345)
2x40G is not supported on MSN2100, need remove it from platform.json
2021-04-27 16:26:42 -07:00
madhanmellanox
29763cd095
Adding new SKU Mellanox-SN3800-D28C49S1 (#7404) 2021-04-23 09:19:56 -07:00
shlomibitton
b0bfa2b86b
[Mellanox] Fix for all Spectrum based systems: SAI profile speed configurations (#7119)
Fix to the correct value for all SPC1 devices.
For 10G added 10GB_CX4_XAUI, 10GB_KX4, 10GB_KR, 10GB_SR and 10GB_ER_LR
For 50G added 50GB_SR2

This bitmask represents all the options available for interface type and some were missing.
Note: it was working just fine if you were setting the value from SONiC CLI but not from the default SAI Profile.

Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2021-04-19 10:03:15 -07:00
Kebo Liu
ef98890e6e
[Mellanox] Fix incomplete platform name for MSN4600C in sfputil plugin (#7259)
The platform name for MSN4600C in sfputil pliugin is not complete: "x86_64-mlnx_msn4600c" -> "x86_64-mlnx_msn4600c-r0"

Signed-off-by: Kebo Liu <kebol@nvidia.com>
2021-04-08 10:15:31 -07:00
Stephen Sun
46a7fac1aa
Bug fix: Support dynamic buffer calculation on ACS-MSN3420 and ACS-MSN4410 (#7113)
- Why I did it
Add missed files for dynamic buffer calculation for ACS-MSN3420 and ACS-MSN4410

- How I did it
asic_table.j2: Add mapping from platform to ASIC
Add buffer_dynamic.json.j2 for ACS-MSN4410.

- How to verify it
Check whether the dynamic buffer calculation daemon starts successfully.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2021-04-07 20:33:15 +03:00
Junchao-Mellanox
48042b7256
[Mellanox] Use softlink for sfputils on MSN4410 platform (#7092)
The file device/mellanox/x86_64-mlnx_msn4410-r0/plugins/sfputil.py is not a software link for device/mellanox/x86_64-mlnx_msn2700-r0/plugins/sfputil.py. And it is still using python2 syntex which causes some SFP CLI error. The PR is to change it to a softlink and add 4410 support in device/mellanox/x86_64-mlnx_msn2700-r0/plugins/sfputil.py.
2021-03-27 11:56:48 -07:00
Lior Avramov
d19bb02ce4
[Mellanox]: Fix PCIEd configuration files for SN3700 system (#7058)
Update with correct PCI addresses

Signed-off-by: liora <liora@nvidia.com>
2021-03-15 21:06:12 -07:00
madhanmellanox
721948f3e4
[mellanox]: Fixing wrong index in Mellanox-SN3800-D28C50 SKU (#7032)
Co-authored-by: Madhan Babu <madhan@l-csi-0241l.mtl.labs.mlnx>
2021-03-11 20:16:51 -08:00
Dror Prital
b85caa581f
[DPB] [Mellanox] added capability files for SN2700-D40C8S8 SKU (#6878)
#### Why I did it

Additional file for DPB in order to support SKU SN2700-D40C8S8 on master

#### How I did it

Add hwsku.json file

#### How to verify it

Enforce  "Mellanox-SN2700-D40C8S8 SKU on Master and see it works as expected, meaning:

Port 1/3 will be used as 4x10G
Port 2/4 - Not exist (blocked since 1 and 3 split to 4)
Port 7/8/9/10/23/24/25/26 will used as 100G
All other ports will be used as 2x50G

This PR should be added on top of PR:
https://github.com/Azure/sonic-buildimage/pull/6876

#### Description for the changelog

Adding hwsku.json file to SN2700-D40C8S8 SKU
2021-03-05 12:43:22 -08:00
Junchao-Mellanox
0e071493de
Change buffer config for new SKU Mellanox-SN2700-D40C8S8 (#6926)
#### Why I did it

Change buffer config for new SKU Mellanox-SN2700-D40C8S8

#### How I did it

Reuse the buffer config of SKU Mellanox-SN2700-D48C8

#### How to verify it

Run sonic-mgmt qos test and all passed
2021-03-04 14:12:59 -08:00
DavidZagury
724785db15
[DPB] [Mellanox] Fix files for SN4600 platform (#6930)
- Why I did it
Fix the build and fix the SN4600 DPB support

- How I did it
Fix port configuration file for SN4600 based on recent changes

- How to verify it
System bringup is completed, all interfaces are up.
Platform tests suits all is passing.
2021-03-02 07:35:18 +02:00
DavidZagury
08202017d9
[DPB] [Mellanox] added capability files for SN4600 platform (#6887)
- Why I did it
To add support for the dynamic breakout on Mellanox platform x86_64-mlnx_msn4600

- How I did it
Add the relevant files describing Mellanox platform x86_64-mlnx_msn4600 breakout modes to a new device folder.

- How to verify it
System bringup is completed, all interfaces are up.
Platform tests suits all is passing.
2021-03-01 12:43:33 +02:00
Lior Avramov
bc1ed0a516
[Mellanox]: Fix PCIEd configuration files for SN3700 and SN3800 systems (#6913)
- Why I did it
To fix PCIEd errors in log.

- How I did it
Update pcie.yaml with the right PCI addresses.

- How to verify it
Check logs, operation occurs each minute.

Signed-off-by: liora <liora@nvidia.com>
2021-03-01 12:36:18 +02:00
Nazarii Hnydyn
39b1c12731
[Mellanox]: Fix PCIEd config for SN4600c (#6892)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2021-02-26 00:28:32 -08:00
Nazarii Hnydyn
923dc52f15
[Mellanox]: Fix PCIEd config for SN4600 (#6894)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2021-02-26 00:28:17 -08:00
Sangita Maity
18263c99dd
[DPB|master] Update Dynamic Port Breakout Logic for flexible alias support a… (#6831)
To fix [DPB| wrong aliases for interfaces](https://github.com/Azure/sonic-buildimage/issues/6024) issue, implimented flexible alias support [design doc](https://github.com/Azure/SONiC/pull/749)

> [[dpb|config] Fix the validation logic of breakout mode](https://github.com/Azure/sonic-utilities/pull/1440) depends on this

#### How I did it

1. Removed `"alias_at_lanes"` from port-configuration file(i.e. platfrom.json) 
2. Added dictionary to "breakout_modes" values. This defines the breakout modes available on the platform for this parent port, and it maps to the alias list. The alias list presents the alias names for individual ports in order under this breakout mode.
```
{
    "interfaces": {
        "Ethernet0": {
            "index": "1,1,1,1",
            "lanes": "0,1,2,3",
            "breakout_modes": {
                "1x100G[40G]": ["Eth1"],
                "2x50G": ["Eth1/1", "Eth1/2"],
                "4x25G[10G]": ["Eth1/1", "Eth1/2", "Eth1/3", "Eth1/4"],
                "2x25G(2)+1x50G(2)": ["Eth1/1", "Eth1/2", "Eth1/3"],
                "1x50G(2)+2x25G(2)": ["Eth1/1", "Eth1/2", "Eth1/3"]
            }
        }
}
```
#### How to verify it
`config interface breakout`

Signed-off-by: Sangita Maity <samaity@linkedin.com>
2021-02-26 00:13:33 -08:00
DavidZagury
5aee92e56d
[Mellanox] Add support for SN4600 system (#6879)
- Why I did it
Add support for new 64x200G SN4600 systems

- How I did it
Add all relevant files (w/o platform.json and hwsku.json as they will come later) with default SKU.

- How to verify it
Install image on switch, verify all ports are up and configured properly, run full platform SONiC tests.
2021-02-25 09:30:43 +02:00
Dror Prital
51eee8ccce
Add new SKU of Mellanox-SN2700-D40C8S8 (#6876)
#### Why I did it

Add new SKU for SN2700 Mellanox system that supports the following port configuration:
8 X 100G
40 X 50G
8 X 10G

#### How I did it

Add new Folder - "Mellanox-SN2700-D40C8S8" under /sonic-buildimage/device/mellanox/x86_64-mlnx_msn2700-r0/
that contains the relevant files supporting this SKU

the buffers are based on SKU: D48C8 . Later on it will be configured specific for this SKU

#### How to verify it

Bring up the image, run "show interface status" and make sure that all ports are up and reflect the following requirement:
Port 1/3 will be used as 4x10G
Port 2/4 - Not exist (blocked since 1 and 3 split to 4)
Port 7/8/9/10/23/24/25/26 will used as 100G
All other ports will be used as 2x50G

#### Which release branch to backport (provide reason below if selected)

- [ ] 201811
- [ ] 201911
- [ ] 202006
- [X] 202012

#### Description for the changelog

Support new SKU under the name of SN2700-D40C8S8
2021-02-24 10:34:12 -08:00
shlomibitton
2076260180
Fix for Mellanox-SN4600C-D112C8 SKU (#6817)
- Why I did it
Mellanox-SN4600C-D112C8 SKU is not configured properly.
It should have 112 50G interfaces and 8 100G interfaces as described on this PR.

- How I did it
Modify sai_profile, port_config.ini and hwsku.json for DPB.

- How to verify it
Apply this HwSKU to a MSN4600C Mellanox platform.

Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2021-02-18 17:44:03 +02:00
Stephen Sun
7790a74d90
Support shared headroom pool for Microsoft SKUs (#6366)
- Why I did it
Support shared headroom pool

Signed-off-by: Stephen Sun stephens@nvidia.com

- How I did it
Port configurations for SKUs based on 2700/3800 platform from 201911
For SN3800 platform:
C64: 32 100G down links and 32 100G up links.
D112C8: 112 50G down links and 8 100G up links.
D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.
For SN2700 platform:
D48C8: 48 50G down links and 8 100G up links
C32: 16 100G downlinks and 16 100G uplinks
Add configuration for Mellanox-SN4600C-D112C8
112 50G down links and 8 100G up links.

- How to verify it
Run regression test.
2021-02-16 08:53:40 -08:00
Joe LeVeque
18f2c5cfdd
[platform] Update QSFP method name 'parse_qsfp_dom_capability' -> 'parse_dom_capability' (#6695)
**- Why I did it**
PR https://github.com/Azure/sonic-platform-common/pull/102 modified the name of the SFF-8436 (QSFP) method to align the method name between all drivers, renaming it from `parse_qsfp_dom_capability` to `parse_dom_capability`. Once the submodule was updated, the callers using the old nomenclature broke. This PR updates all callers to use the new naming convention.

**- How I did it**

Update the name of the function globally for all calls into the SFF-8436 driver.

Note that the QSFP-DD driver still uses the old nomenclature and should be modified similarly. I will open a PR to handle this separately.
2021-02-05 14:41:05 -08:00
Vadym Hlushko
48e7116bcd
[DPB][SN3700C] extended set of speeds for split modes (#6277)
platform.json and hwsku.json files has not a full set of speeds for split modes

Signed-off-by: Vadym Hlushko <vadymh@nvidia.com>
2021-01-24 16:33:52 -08:00
Vadym Hlushko
709c1ecb06
[DPB][SN4700] extended set of speeds for split modes (#6278)
platform.json and hwsku.json files has not a full set of speeds for split modes

Signed-off-by: Vadym Hlushko <vadymh@nvidia.com>
2021-01-24 16:33:25 -08:00
Vadym Hlushko
4e1c102883
[DPB] [Mellanox] added capability files for SN3420 platform (#6020)
platform.json and hwsku.json files are required for a feature called Dynamic Port Breakout

Signed-off-by: Vadym Hlushko <vadymh@nvidia.com>
2021-01-19 09:47:19 -08:00
Vadym Hlushko
ece8297cf8
[DPB] [Mellanox] added capability files for SN4600C platform (#6061)
- Why I did it
platform.json and hwsku.json files are required for a feature called Dynamic Port Breakout

- How I did it
Created capability files according to platform specification SN4600C

- How to verify it
Full qualification requires bugs fixes reported under sonic-buildimage

NOTE: breakout to 4 is currently not available as of missing functionality in DPB implementation.

Signed-off-by: Vadym Hlushko <vadymh@nvidia.com>
2021-01-17 11:13:54 +02:00
Vadym Hlushko
db5a88eef7
[DPB] [Mellanox] added capability files for SN4410 platform (#6059)
- Why I did it
platform.json and hwsku.json files are required for a feature called Dynamic Port Breakout

- How I did it
Created capability files according to platform specification SN4410

- How to verify it
Full qualification requires bugs fixes reported under sonic-buildimage

Signed-off-by: Vadym Hlushko <vadymh@nvidia.com>
2021-01-17 11:08:42 +02:00