Commit Graph

8 Commits

Author SHA1 Message Date
gechiang
ef457ab13f
Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9199) 2021-11-09 07:21:57 -08:00
gechiang
8e903f4566
BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8382)
* BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-10 19:03:22 -07:00
Samuel Angebault
468aac92b7
[Arista] Update platform configurations for 7060DX4 and 7060PX4 (#6084)
Current support for the 7060PX4-32 and 7060DX4 was broken.
With this change, ports are now linking fine.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-12-04 10:11:06 -08:00
zzhiyuan
3da996bbf8
[arista]: Add disable_pcie_firmware_check soc property (#5543)
This is to fix pcie firmware check assert in Broadcom SDK once the SAI changes merges. This will be in the future but adding the soc property in the broadcom config now.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-10-06 18:35:15 -07:00
abdosi
a6a10f05b7
In SAI 3.5 by default we are supporting 256 Group with 64 Memeber each. (#5400)
However in SAI 3.7 default behaviout got changes to 128 Group and 128
    Memeber each.

    This change is to make sure we are using same ECMP Group/Memeber Per
    Group for 3.7 also so that behaviour is consistent.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-22 11:21:12 -07:00
Samuel Angebault
de4fa1874a
[arista]: remove the soc property disabling sram scan (#4623) 2020-05-20 12:44:48 -07:00
zzhiyuan
16e85712b7 [devices]: Add tuning for Arista 7060PX/DX4 32x400G (#3145)
* Add serdes polarity for 32x400G Arista 7060PX/DX4

* Add serdes polarity for 64x100G on Arista 7060PX/DX4
2019-07-12 11:25:19 -07:00
Samuel Angebault
d84aa49d38 [device/Arista] Add HwSku profiles for the 7060PX-32 (#2973)
* Add port configuration for HWSKU Arista-7060PX4-O32

* Add 64x100G configuration for 7060PX4-32
2019-06-06 15:38:11 -07:00