as needed by SAI 3.7 and above. Without this change
Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure
gets corrupted after warm-boot.
Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
* Remove the divide by 4 operation to the under the hood SAI
This is to avoid the need and thus the confusion for application program to know
the mmu internal architecture
This change must have support from SAI change to reach the correct
config
Signed-off-by: Wenda <wenni@microsoft.com>
* Relegate the divide by 4 operation to the under the hood SAI for egress
lossless pool
Extend to 7060 and 6100
Signed-off-by: Wenda <wenni@microsoft.com>
* Add more TH/TH2 hwskus
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* Update config test
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* Add TH2 ingress lossy profile
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* Move the divide by 4 operation to SAI internal
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* [bcm SAI] Upgrade Broadcom SAI to version 3.5.3.1-15
- Broadcom SAI 3.5 GA release 20190924.
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU
Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines
Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
* [HWSKU] Added Arista-7060CX-32S-T96C8 HWSKU
Added the bcm config files for a 96x25G+8x100G ToR
Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU
Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines
Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
