Commit Graph

7 Commits

Author SHA1 Message Date
mssonicbld
fd6523b423
Fix port index for multi-asic (#13042) (#13086)
Port indexes of front panel ports are not contiguous in multi-asic because we didn't distiguish between
front panel and internal ports, e.g., recycle ports. Fix this by assigning index to front panel port first
and then internal ports.

Co-authored-by: Song Yuan <64041228+ysmanman@users.noreply.github.com>
2022-12-16 14:56:12 -08:00
vmittal-msft
89ac469d62 Updated config files to disable DLR_INIT capability (#12401) 2022-10-25 20:42:28 +00:00
Sambath Kumar Balasubramanian
1d627f73c8
[Chassis][Voq] Update bcm config file system_ref_core_clock_khz param for j2cplus linecards. (#11760)
Update the bcm config file system_ref_core_clock_khz param to
handlesystems with J2cplus linecards.
We need system_ref_core_clock_khz to be set to 1600000 for supporting j2
and j2cplus linecards on the same chassis.
2022-08-19 16:15:12 -07:00
kenneth-arista
2280f3854c [Arista] Enable larger number of LAGs on 7800 LCs (#11070)
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.

Why I did it
The SOC property changes are necessary to match #10519 which increases the number of system LAG IDs to 1024.

Description for the changelog
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.
2022-08-08 20:40:54 +00:00
vmittal-msft
8035e3d9a7 Updated Chassis MMU settings for 40G/100G/400G line cards (#11108)
* Updated Chassis MMU settings for 40G/100G/400G line cards
2022-07-05 16:10:50 +00:00
arista-nwolfe
b3672c1f57
Setting the soc property for num_sa_per_sc on macsec encrypt/decrypt (cherry-pick of PR 11166) (#11279) 2022-07-05 09:06:24 -07:00
Maxime Lorrillere
392899682f
[Arista] Add support for Wolverine linecards (#8887)
Add support for WolverineQCpu, WolverineQCpuMs, WolverineQCpuBk, WolverineQCpuBkMs

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-20 14:11:06 -07:00