4 Commits

Author	SHA1	Message	Date
Stephen Sun	c8277a4eba	Update buffer configuration for SKUs based on SN3800 (#5320) ... C64: 32 100G down links and 32 100G up links. D112C8: 112 50G down links and 8 100G up links. D24C52: 24 50G down links, 20 100G down links, and 32 100G up links. D28C50: 28 50G down links, 18 100G down links, and 32 100G up links. Signed-off-by: Stephen Sun <stephens@nvidia.com>	2020-09-22 19:10:18 +03:00
Stephen Sun	54fcdbb380	Support single ingress pool for MSFT SKUs and optimize headroom calculation (#4686) ... Calculate pool size in t1 as 24 * downlink port + 8 * uplink port - Take both port and peer MTU into account when calculating headroom - Worst case factor is decreased to 50% - Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports - Mellanox-SN2700 (C32) - t0: 16 * 100G/5m + 16 * 100G/40m - t1: 16 * 100G/40m + 16 * 100G/300m Signed-off-by: Stephen Sun <stephens@mellanox.com> Co-authored-by: Stephen Sun <stephens@mellanox.com>	2020-08-13 13:12:09 +03:00
Stephen Sun	8f0ff4b764	[Mellanox] Calculate the buffer size based on the latest excel and with gearbox considered (#4239)	2020-03-11 13:44:18 -07:00
Nazarii Hnydyn	fc101b6ceb	[mellanox]: Add new Mellanox-SN3800-D112C8 sku. (#4085) ... Signed-off-by: Nazarii Hnydyn <nazariig@mellanox.com>	2020-01-30 18:54:09 -08:00