Commit Graph

5 Commits

Author SHA1 Message Date
zitingguo-ms
ae90bfae4b [AN/LT][Fix bug]:enable phy_an_lt_msft attribute on some platforms (#11147) 2022-06-16 02:13:22 +00:00
gechiang
ef457ab13f
Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9199) 2021-11-09 07:21:57 -08:00
gechiang
8e903f4566
BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8382)
* BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-10 19:03:22 -07:00
abdosi
b6efb49817
Update bcm soc property bcm_num_cos from 8 to 10 (#5314)
as needed by SAI 3.7 and above. Without this change
Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure
gets corrupted after warm-boot.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-04 07:40:17 -07:00
Michel Moriniaux
62e994d8ec [HWSKU] add Arista-7060CX-32S-T96C8 and Arista-7060CX-32S-Q24C8 (#2617)
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-T96C8 HWSKU

Added the bcm config files for a 96x25G+8x100G ToR

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
2019-03-15 09:45:17 -07:00