Commit Graph

4 Commits

Author SHA1 Message Date
guxianghong
64f5b98caa
[centec][build] Fix docker-syncd-centec-rpc build fail (#9612) (#9964)
Why I did it
Fix docker-syncd-centec-rpc build fail. Detail fail log can be derived from https://dev.azure.com/mssonic/be1b070f-be15-4154-aade-b1d3bfb17054/_apis/build/builds/71157/logs/9.

How I did it
Merge PR #9612 from master branch.

How to verify it
make ENABLE_SYNCD_RPC=y target/docker-syncd-centec-rpc.gz
make ENABLE_SYNCD_RPC=y target/docker-saiserver-centec.gz
2022-03-21 09:56:59 -07:00
guxianghong
bb798a3628
[centec] Support saiserver docker for centec-x86 and centec-arm64 platform (#9162)
Fix docker-syncd-centec-rpc.gz compile fail
Support Centec saiserver docker

Co-authored-by: Xianghong Gu <xgu@centecnetworks.com>
2021-11-15 21:58:47 -08:00
guxianghong
d4f9fa56aa
[Centec] upgrade to buster docker for DOCKER_SYNCD_CENTEC_RPC, docker-saiserver-centec and platform-modules (#6423)
Centec syncd have beend upgraded to buster, docker-syncd-centec-rpc do not need generate stretch based docker.

Co-authored-by: Xianghong Gu <xgu@centecnetworks.com>
2021-01-12 12:36:10 -08:00
taochengyi
08f3b9720b
[centec]: Add centec arm64 architecture support for E530 (#4641)
summary of E530 platfrom:
 - CPU: CTC5236, arm64
 - LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G.
- device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports.
- device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports.

add new files in three directories:
device/centec/arm64-centec_e530_24x2c-r0
device/centec/arm64-centec_e530_48t4x_p-r0
platform/centec-arm64

Co-authored-by: taocy <taocy2@centecnetworks.com>
Co-authored-by: Gu Xianghong <gxh2001757@163.com>
Co-authored-by: shil <shil@centecnetworks.com>
2020-08-06 03:16:11 -07:00