Commit Graph

3 Commits

Author SHA1 Message Date
Stephen Sun
fa99059b51 Update buffer configuration for SKUs based on SN3800 (#5320)
C64: 32 100G down links and 32 100G up links.
D112C8: 112 50G down links and 8 100G up links.
D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2020-09-28 16:16:45 +00:00
Stephen Sun
f6a8678d8f
Support single ingress pool for MSFT SKUs and optimize headroom calculation (#5194)
This is to backport the #4886 to 201911

Calculate pool size in t1 as 24 * downlink port + 8 * uplink port

- Take both port and peer MTU into account when calculating headroom
- Worst case factor is decreased to 50%
- Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports
- Mellanox-SN2700 (C32)
  - t0: 16 * 100G/5m + 16 * 100G/40m
  - t1: 16 * 100G/40m + 16 * 100G/300m

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2020-08-15 07:52:28 -07:00
madhanmellanox
67e183d0dc added files to create SKU Mellanox-SN3800-C64 (#4812)
* added files to create SKU Mellanox-SN3800-C64
Co-authored-by: Madhan Babu <madhan@arc-build-server.mtr.labs.mlnx>
2020-06-22 17:39:31 -07:00