Commit Graph

290 Commits

Author SHA1 Message Date
mssonicbld
537c0afdb4
[Arista][x86_64-arista_7050_qx32] Add Components to platform.json (#15252) (#15584) 2023-06-23 05:04:38 +08:00
arista-nwolfe
1dea6e4627
[202211] Cherry-picked commits from PR13967 for 202211 (#14791)
* Added recycle ports required for egress mirroring

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>

* Added missing mirror recycle ports for jr2-a7280cr3

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>

---------

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>
2023-06-22 08:13:42 -07:00
Samuel Angebault
c1a7677b63 [Arista] fix platform.json for a few devices (#15308)
Why I did it
sonic-mgmt is failing tests due to invalid test data in platform.json
Fwutil is upset the chassis name in the platform_component.json of the 7060CX-32S

How I did it
Fixed the aforementioned issues
2023-06-16 09:55:02 +08:00
Arvindsrinivasan Lakshmi Narasimhan
6a3a6c77f4 set the default value for the port fec to RS on J2 based LC (#15346)
Why I did it
Work item tracking
Microsoft ADO (24182162):
How I did it
update the config.bcm to set the default fec RS 100G Linecard

How to verify it
Tests on chassis
2023-06-10 14:32:36 +08:00
Samuel Angebault
f394121903 [Arista] Add missing platform_components.json (#14067)
Provide platform-components.json for Clearwater2 and Wolverine

These files are needed for fwutil platform sonic-mgmt tests to pass.

Fix PikeZ platform_components.json

Co-authored-by: Patrick MacArthur <pmacarthur@arista.com>
Co-authored-by: Andy Wong <andywong@arista.com>
2023-03-20 20:54:49 +08:00
mssonicbld
7b61e894ac
sonic-buildimage Remove unused SAT port from arista configs. (#14167) (#14333) 2023-03-19 23:08:48 +08:00
Song Yuan
09a3f922fb Add QOS profiles for Arista SKUs (#13829) 2023-03-19 22:33:05 +08:00
Patrick MacArthur
ff5605ae00
fix platform.json on Wolverine for thermal sensors (#13984)
Why I did it
Manual rebase of PR #13524 to 202211 branch.

How I did it
See PR #13524
2023-02-28 08:54:01 +08:00
andywongarista
be51191fd8 [Arista] Add other chassis names to platform_components.json for 720DT-48S (#12378)
Why I did it
The 720DT-48S platform has variants with different chassis names, and these need to all be included in platform_components.json to ensure that sonic-mgmt platform_tests/fwutil/test_fwutil.py::test_fwutil_show passes

How I did it
Updated platform_components.json with the variant names for 720DT-48S.

How to verify it
Ran aforementioned testcase and verified that it passes on the different variants.
2023-02-22 20:55:50 +08:00
wenyiz2021
9635f960f0 [Arista] [Platform] Update platform.json for psu led (#13523)
Why I did it
By specifying 'status_led' 'controllable' to false for psu section, it means the platform is not yet supporting psu status led

How I did it
specify 'status_led' 'controllable' to false for psu section

How to verify it
by running test in pdb, manually add {'status_led' : {'controllable' : False}} in dictionary
this flag will be able to get False and skip testing:
ce290c735d/tests/platform_tests/api/test_psu.py (L337)
2023-02-18 06:34:33 +08:00
Richard.Yu
fe1fc4cf6a
[broadcom]: Set default SYNCD_SHM_SIZE for Broadcom XGS devices (#13297) (#13807)
After upgrade to brcmsai 8.1, the sdk running environment (container) recommended with mininum memory size as below

TH4/TD4(ltsw) uses 512MB
TH3 used 300MB
Helix4/TD2/TD3/TH/TH 256 MB
Base on this requirement, adjust the default syncd share memory size and set the memory size for special ACISs in platform_env.conf file for different types of Broadcom ASICs.

How I did it
Add the platform_env.conf file if none of it for broadcom platform (base on platform_asic file)
Add the 'SYNCD_SHM_SIZE' and set the value

for ltsw(TD4/TH4) devices set to 512M at least (update the platform_env.conf)
for Td2/TH2/TH devices set to 256M
for TH3 set to 300M

verify

How to verify it
verify the image with code fix
Check with UT
Check on lab devices

On a problematic device which cannot start successfully
Run with the command
$ cat /proc/linux-kernel-bde
Broadcom Device Enumerator (linux-kernel-bde)
Module parameters:
        maxpayload=128
        usemsi=0
        dmasize=32M
        himem=(null)
        himemaddr=(null)
DMA Memory (kernel): 33554432 bytes, 0 used, 33554432 free, local mmap
No devices found
$ docker rm -f syncd
syncd
$ sudo /usr/bin/syncd.sh start
Cannot get Broadcom Chip Id. Skip set SYNCD_SHM_SIZE.
Creating new syncd container with HWSKU Force10-S6000
a4862129a7fea04f00ed71a88715eac65a41cdae51c3158f9cdd7de3ccc3dd31
$ docker inspect syncd | grep -i shm
            "ShmSize": 67108864,
                "Tag": "fix_8.1_shm_issue.67873427-9f7ca60a0e",
On Normal device
$ docker inspect syncd | grep -i shm
            "ShmSize": 268435456,
                "Tag": "fix_8.1_shm_issue.67873427-9f7ca60a0e"
change the config syncd_shm.ini to b85=128m

$ docker rm -f syncd
syncd
$ sudo /usr/bin/syncd.sh start
Creating new syncd container with HWSKU Force10-S6000
3209ffc1e5a7224b99640eb9a286c4c7aa66a2e6a322be32fb7fe2113bb9524c
$  docker inspect syncd | grep -i shm
            "ShmSize": 134217728,
                "Tag": "fix_8.1_shm_issue.67873427-9f7ca60a0e",
change the config under
/usr/share/sonic/device/x86_64-dell_s6000_s1220-r0/Force10-S6000/platform_env.conf
and run command

$ cat /usr/share/sonic/device/x86_64-dell_s6000_s1220-r0/platform_env.conf
SYNCD_SHM_SIZE=300m

$ sudo /usr/bin/syncd.sh start
Creating new syncd container with HWSKU Force10-S6000
897f6fcde1f669ad2caab7da4326079abd7e811bf73f018c6dacc24cf24bfda5
$  docker inspect syncd | grep -i shm
            "ShmSize": 314572800,
                "Tag": "fix_8.1_shm_issue.67873427-9f7ca60a0e",

Signed-off-by: richardyu-ms <richard.yu@microsoft.com>
2023-02-15 15:58:49 +08:00
kenneth-arista
67610d7e4f [device/arista] Reduce SDK stat polling freq in DNX devices (#13429)
Eariler the SDK stat polling was erroneously set to once every msec
which is far more frequent than required by SWSS. The new setting, which
is consistent with other vendor SKUs, is once a second. The net result
is reduced CPU MHz by syncd.
2023-02-11 02:38:01 +08:00
Jing Kan
1f9ff1ca3d [Arista 720DT] Create SKU alias Arista-720DT-G48S4 (#12905) 2023-02-06 12:36:59 +08:00
byu343
2f27120c8a [Arista]: Add hwSku Arista-7260CX3-D108C10 (#13242)
* [Arista]: Add hwSku Arista-7260CX3-D108C10

* Add buffer-related config for Arista-7260CX3-D108C10
2023-02-04 10:48:14 +08:00
kenneth-arista
e3790d3044 [device/arista] Disabled polled_irq_mode for DNX SKUs (#13349)
Disabled polled_irq_mode for all Arista DNX devices as this mode
leads to excessive use of the CPU via an unneeded interrupt
polling thread.
2023-02-04 10:48:10 +08:00
andywongarista
19e94dfbfc [Arista] Update ip packet checksum when set to 0xffff on 720DT-48S (#13088)
Why I did it
This is to fix test_forward_ip_packet_with_0xffff_chksum_tolerant test failure on 720DT-48S. IP packets with checksum set to 0xffff will be forwarded with the same checksum on this platform, instead of updating to the correct value.

How I did it
Add bcm config sai_verify_incoming_chksum=0 so that checksum is updated instead of being left unchanged when checksum is 0xffff. Note that packets with invalid checksum are still dropped with this config.
2023-02-04 09:53:41 +08:00
mssonicbld
05fb3f628f
[Arista] add support for hardware sku Arista-7260CX3-D92C16 (#13438) (#13448) 2023-01-20 17:36:37 +08:00
andywongarista
85700117db [Arista] Enable ipv6 128b lpm on 720DT-48S (#12832)
Why I did it
Added to allow test_crm_route to pass; the test tries to add a /126 ipv6 route and this change is required in order for the count of available routes to be updated correctly.
2022-12-10 10:33:21 +08:00
Bohan Yang
9b7a04dc0e [Arista]Add media_settings.json for x86_64-arista_7800r3a_36d2_lc (#12444)
Why I did it
TX FIR tuning should be done based on the type of inserted transceiver

How I did it
Add media_settings.json which contains the tuning data for 100G optic and 400G optic.

How to verify it
Tested against x86_64-arista_7800r3a_36d2_lc
2022-12-10 10:33:21 +08:00
bingwang-ms
2e0d958a42 Apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP to uplink ports on dualtor (#12730)
Why I did it
The PR is to apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP to uplink ports on dualtor.
The traffic with DSCP 2 and DSCP 6 from T1 is treated as lossless traffic.

DSCP    TC    Queue
2      2     2
6      6     6
Traffic with DSCP 2 or DSCP 6 from downlink is still treated as lossy traffic as before.

How I did it
Define DSCP_TO_TC_MAP|AZURE_UPLINK and TC_TO_QUEUE_MAP|AZURE_UPLINK.

How to verify it
Verified by UT
Verified by coping the new template to a testbed, and rendering a config_db.json
2022-12-10 10:33:21 +08:00
Samuel Angebault
5cd134f32b [Arista] Update platform.json for 7060CX-32S (#12783)
Why I did it
Some sonic-mgmt platform_tests/api were failing on the 7060CX-32S

How I did it
Added the missing metadata in platform.json and platform_components.json
This is purely test data and does not impact our API implementation.

How to verify it
Run platform_tests / api and expect 100% pass rate.
2022-12-10 10:33:21 +08:00
Samuel Angebault
9c8049868c [Arista] Update platform.json for 7260CX3-64 (#12757)
Why I did it
Some sonic-mgmt platform_tests/api were failing on the 7260CX3-64

How I did it
Added the missing metadata in platform.json and platform_components.json
This is purely test data and does not impact our API implementation.

How to verify it
Run platform_tests/api and expect 100% passrate.
2022-12-10 10:33:21 +08:00
Neetha John
dc21c9605e
[Profile separation] MMU infrastructure update for TD2 (#12626)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
There is a need to have separate profiles on compute and storage and this infra update will help achieve that

How I did it
Moved buffer pool/profile and qos definitions on TD2 to a common folder and all TD2 hwsku's will reference that folder
2022-11-17 12:58:11 -08:00
wenyiz2021
fecc7c6a1d
[Arista] [platform] Add thermal info in platform.json (#12714)
add 1 more thermal entry
2022-11-17 11:05:16 -08:00
Samuel Angebault
4d62689914
[Arista] Add pcie.yaml to 7280CR3-32D4 variants (#12700) 2022-11-14 13:29:30 -08:00
wenyiz2021
39ebf80f1b
[arista] [chassis] Add psu/thermal info in platform.json for sup (#12667)
update psu info in platform.json on sup
2022-11-14 11:03:52 -08:00
wenyiz2021
f581a77a64
[Chassis] [Arista] correct platform.json for sup and LC6 names (#12627)
add platform.json separately for LC6 that has different name, bc of supporting macsec
Signed-off-by: Wenyi Zhang <wenyizhang@microsoft.com>
2022-11-08 12:56:39 -08:00
judyjoseph
c259c996b4
Use the macsec_enabled flag in platform to enable macsec feature state (#11998)
* Use the macsec_enabled flag in platform to enable macesc feature state
* Add macsec supported metadata in DEVICE_RUNTIME_METADATA
2022-11-08 11:03:38 -08:00
arlakshm
c4be3a51aa
[chassis][Arista] add supervisor to the platform_env.conf (#12615)
Why I did it
Fixes #12614

How I did it
In the container_checker the database_chassis is added to expected container if device is supervisor
To detect the device is superviso, add supervisor=1 to the platform_env.conf of 7808 sup platform

How to verify it
run container_checker monit check
Signed-off-by: Arvindsrinivasan Lakshmi Narasimhan <arlakshm@microsoft.com>
2022-11-07 15:30:02 -08:00
andywongarista
34b6cc0de2
[Arista] Fix content of platform.json for DCS-7050CX3-32S (#12082)
* Fix platform.json for 7050cx3

* Add platform_components.json

* Mark thermals as not controllable
2022-10-18 18:38:28 -07:00
vmittal-msft
cca17ce104
Updated config files to disable DLR_INIT capability (#12401) 2022-10-18 10:13:07 -07:00
Sambath Kumar Balasubramanian
7ba1d25757
Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards. (#11813)
Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards.
2022-10-17 11:15:19 -07:00
Bohan Yang
fad4034000
Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872)
Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards.
2022-10-13 20:36:44 -07:00
Ying Xie
1ad1e19733
[RDMA] create split profiles for Arista-7050CX3-32S (#12228)
Moving buffer configuration files to sub folders to enable multiple buffer profiles. Otherwise, non-functional change.

Signed-off-by: Ying Xie ying.xie@microsoft.com
2022-10-06 14:15:23 -07:00
andywongarista
2f46689a05
[Arista] Add components for 720DT-48S (#12217)
Why I did it
Add components data for sonic-mgmt testing

How I did it
Update platform.json and add platform_components.json

How to verify it
Ran sonic-mgmt tests (test_chassis and test_component)
2022-10-03 13:53:34 +08:00
Samuel Angebault
5ff45c5846
Implement ssd_util plugin for Arista products (#11981)
Why I did it
Some Arista products do not have an SSD but use an eMMC instead.
The SsdUtil plugin is therefore extended to support both.

How I did it
Implemented ssd_util.py platform plugin loaded by ssdutil.
This plugin fallback to the default SONiC implementation if the arista one can't be found.

How to verify it
Run show platform ssdhealth on a product with an eMMC
2022-09-21 14:56:14 +08:00
Junhua Zhai
63c14d2e9e
[PikeZ] Update port alias in Arista-720DT-48S (#12086)
Fix #12037, by following HLD https://github.com/sonic-net/SONiC/blob/master/doc/sonic-port-name.md.
2022-09-20 20:04:14 +08:00
Maxime Lorrillere
0a7dd50dcb
[Chassis][Voq]Configure midplane network on supervisor (#11725)
Multi-asic Docker instances are created behind Docker's default bridge
which doesn't allow talking to other Docker instances that are in the
host network (like database-chassis).

On linecards, we configure midplane interfaces to let per-asic docker
containers talk to CHASSIS_DB on the supervisor through internal chassis
network.

On the supervisor we don't need to use chassis internal network, but we
still need a similar setup in order to allow fabric containers to talk
to database-chassis
2022-09-15 17:23:41 -07:00
bingwang-ms
dc9eaa53fb
Map TC6 to Queue 1 for regular traffic (#11904)
Why I did it
This PR is to update TC_TO_QUEUE_MAP|AZURE for SKU Arista-7050CX3-32S-D48C8 and Arista-7260CX3 T0.

The change is only to align the TC_TO_QUEUE_MAP for regular traffic and bounced traffic. It has no impact on business because we have no traffic being mapped to TC2 or TC6.

How I did it
Update TC_TO_QUEUE_MAP|AZURE , and test cases as well.

How to verify it
Verified by running test case test_j2files.py

/sonic/src/sonic-config-engine$ python3 setup.py test -s tests/test_j2files.py
running test
......
----------------------------------------------------------------------
Ran 29 tests in 25.390s

OK
2022-09-08 09:18:26 -07:00
Dev Ojha
c601f24139
[Arista7050cx3] TD3 SKU changes for pg headroom value after interop testing with cisco 8102 (#11901)
Why I did it
After PFC interop testing between 8102 and 7050cx3, data packet losses were observed on the Rx ports of the 7050cx3 (inflow from 8102) during testing. This was primarily due to the slower response times to react to PFC pause packets for the 8102, when receiving such frames from neighboring devices. To solve for the packet drops, the 7050cx3 pg headroom size has to be increased to 160kB.

How I did it
Modified the xoff threshold value to 160kB in the pg_profile file to allow for the buffer manager to read that value when building the image, and configuring the device

How to verify it
run "mmuconfig -l" once image is built


Signed-off-by: dojha <devojha@microsoft.com>
2022-08-31 11:08:32 -07:00
Samuel Angebault
f2c9a3584d
[Arista] Fix content of platform.json for DCS-720DT-48S (#11855)
Why I did it
Content of platform.json was outdated and some platform_tests/api of sonic-mgmt were failing.

How I did it
Added the necessary values to platform.json

How to verify it
Running platform_tests/api of sonic-mgmt should yield 100% passrate.
2022-08-29 10:45:24 +08:00
andywongarista
1b83e418f8
Enable AN for Ethernet24-47 (#11839)
Enable port AN ON explicitly and then port will become (oper status) UP. Somehow those ports AN are not default ON in bcm sdk.
2022-08-26 09:30:11 +08:00
Junhua Zhai
abda50c791
Correct port index in Arista-720DT-48S/phy24_config.json (#11699)
Port index 22 is associated with phy23_config.json, then same port index 22 in phy24_config.json may cause gearbox port creation error. Port Ethernet22 maps to index 23.
2022-08-17 12:48:40 +08:00
bingwang-ms
dc799356aa
Support different DSCP_TO_TC_MAP for T1 in dualtor deployment (#11569)
* Support different DSCP_TO_TC_MAP for T1 in dualtor deployment
2022-08-01 09:35:34 +08:00
Jiahua Wang
7683ff5791
[arista]: Add sai_mdio_access_clause22=1 in td3x2-a720dt-48s-flex.config.bcm (#11303)
Add sai_mdio_access_clause22=1 in td3x2-a720dt-48s-flex.config.bcm

Signed-off-by: Jiahua Wang <jiahua.wang@broadcom.com>
2022-07-27 10:04:40 -07:00
andywongarista
07dbc149df
[Arista] Add missing configs for 720DT-48S (#11362)
* Why I did it
Followup to #10656. This change adds the remaining configs for the 720DT-48S platform.

* How I did it
Adds the following:
gearbox_config.json and other gearbox-related config files, to enable traffic on external PHY ports (Ethernet0-23)
sensors.conf
pcie.yaml
Also add missing facts in platform.json

* How to verify it
show interfaces status shows links up on interfaces Ethernet0-23
traffic flows with no errors on interfaces Ethernet0-23
Note: above testing depends on Add gbsyncd container for broncos #11154 and [orchagent]: Enhance initSaiPhyApi sonic-swss#2367, as well as having the appropriate PAI driver.

Co-authored-by: Samuel Angebault <staphylo@arista.com>
2022-07-20 11:36:16 +08:00
Neetha John
765741ac73
Update 7260 MMU and ECN settings (#11449)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
Improve throughput and latency for 7260 deployments

How I did it
Update the dynamic threshold to 0 and ECN settings as 2mb/10mb/5%

How to verify it
Updated unit tests to use the modified values for 7260 ecn settings.
2022-07-18 17:08:20 -07:00
Ying Xie
503a0f7088 [Buffer] Separate buffer profile for Arista-7060CX-32S-Q24C8
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-12 11:48:01 -07:00
Ying Xie
aee63310f6 [7060] fix default port map
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-12 11:48:01 -07:00
zzhiyuan
55e72a3397 [Arista] [201811] Add Arista-7260CX3-D96C16 HWSKU (#10034)
Why I did it
This was an ask by Microsoft to provide:
7260 config.bcm file for hardware sku Arista-7260CX3-D92C16 (Named Arista-7260CX3-D96C16).

There are 16 100G uplinks:
Ethernet13-20/1
Ethernet45-52/1

All other ports are breakout to 2 50G ports.

How I did it
Copied existing Arista-7260CX3-D108C8 HWSKU and altered the bcm.config and port_config.ini files.

How to verify it
The new 100G ports do come up with a 201811 image using this HWSKU.

Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2022-07-12 11:48:01 -07:00