Commit Graph

130 Commits

Author SHA1 Message Date
Ikki Zhu
9a7eb495c2
[E1031] add platform specific reboot command support (#15889)
* [E1031] add platform specific reboot command support

Why I did it
E1031: add platform specific cold reboot support

How I did it
Use the CPLD to trigger board level power cycle when cold reboot

How to verify it
Do reboot stress test and check the reboot cause history

* [E1031] try to umount filesystem before power cycle reboot

* [E1031] remove fstrim in customized reboot script
2023-08-02 17:20:53 -07:00
Ying Xie
bf49154493
Potential fix for Celestica E1031 device hang (#15822)
set CPU max_cstate to 0

Co-authored-by: Sumukha Tumkur Vani <sumukhatv@outlook.com>
2023-07-14 08:38:45 -07:00
Ikki Zhu
9fcbd5ed1d
fix possible cpld race access issue (#15371)
Why I did it
fix possible cpld race read issue between watchdog and reboot cause
process

How I did it
Use fcntl.flock to limit parallel access to cpld sys file

How to verify it
It can be simulated and verified with following python script

``` python3
import fcntl
import signal
import threading

exit_flag = False

def get_cpld_reg_value(getreg_path, register):
    file = open(getreg_path, 'w+')
    # Acquire an exclusive lock on the file
    fcntl.flock(file, fcntl.LOCK_EX)

    try:
        file.write(register + '\n')
        file.flush()

        # Seek to the beginning of the file
        file.seek(0)

        # Read the content of the file
        result = file.readline().strip()
    finally:
        # Release the lock and close the file
        fcntl.flock(file, fcntl.LOCK_UN)
        file.close()

    return result

def cpld_read(thread_num, cpld_reg, expect_val):
    while not exit_flag:
        val
= get_cpld_reg_value("/sys/devices/platform/dx010_cpld/getreg",
cpld_reg)
        #print(f"Thread {thread_num}: get cpld reg {cpld_reg}, value
{val}")
        if val != expect_val:
            print(f"Thread {thread_num}: get cpld reg {cpld_reg}, value
{val}, expect_val {expect_val}")

def signal_handler(sig, frame):
    global exit_flag
    print("Ctrl+C detected. Quitting...")
    exit_flag = True

if __name__ == '__main__':
    # Register the signal handler for Ctrl+C
    signal.signal(signal.SIGINT, signal_handler)

    t1 = threading.Thread(target=cpld_read, args=(1, '0x103', '0x11',))
    t2 = threading.Thread(target=cpld_read, args=(2, '0x141', '0x00',))
    t1.start()
    t2.start()
    t1.join()
    t2.join()
```
2023-06-07 11:29:18 -07:00
george-deng88
2b527d301f
[Celestica] Optimize Silverstone led init process (#14852)
Why I did it
Optimize Silverstone led init process, this linkscan = off can cause the sonic port link status async with bcm shell after reboot.

How I did it
Remove redundant code.

How to verify it
After reboot, the ports can linkup normally.
2023-05-24 15:50:12 -07:00
Ikki Zhu
f550c86bd7
[Seastone] DX010 platform switch to sfp-refactor based sfp impl (#13972)
Why I did it
sonic-sfp based sfp impl would be deprecated in future, change to sfp-refactor based implementation.

How I did it
Use the new sfp-refactor based sfp implementation for seastone.

How to verify it
Manual test sfp platform api or run sfp platform test cases.
2023-03-27 10:17:21 -07:00
Ikki Zhu
f801b8fb2d
[Seastone] fix dx010 qsfp eeprom data write issue (#13930)
Why I did it
Platform cases test_tx_disable, test_tx_disable_channel, test_power_override failed in dx010.

How I did it
Add i2c access algorithm for CPLD i2c adapters.

How to verify it
Verify it with platform_tests/api/test_sfp.py::TestSfpApi test cases.
2023-03-01 14:35:53 +08:00
Ikki Zhu
f8a393c3a1
add psu fans status led available config (#13926)
Why I did it
Seastone does not have the psu fans' status led, need to reflect it in platform.json.

How I did it
Set the psu fans status led available to false.

How to verify it
Verify it with platform_tests/api/test_psu_fans.py::TestPsuFans::test_set_fans_led case.
2023-02-22 10:55:55 -08:00
george-deng88
3097e4258d
Fix Celestica Silverstone addDecapTunnel failed issue (#13235)
*Why I did it
     The current sonic image bringup failed on Silverstone:
     4:56:15.957705 sonic NOTICE swss#orchagent: :- addDecapTunnel: Create overlay loopback router interface oid:6000000000520
 *How I did it
     Enable bcm switch Tunnel function on Silverstone.
 *How to verify it
     The new sonic image can bringup OK on Silverstone.
2023-02-14 12:18:19 -08:00
Ikki Zhu
f6701f5fd7
[DX010 platform] fix dx010 platform testcase issues (#13595)
Why I did it
1. fix chassis test_set_fans_led case
2. fix chassis get_name case mismatch issue
3. fix fan_drawer test_set_fans_speed
4. fix component test_components test case

How I did it
Add corresponding configuration into chassis json file

How to verify it
Run platform tests cases to verify these failure cases
2023-02-09 19:07:13 -08:00
Ikki Zhu
1dec473495
[Celestica DX010] fix fan drawer and watchdog platform testcase issues (#13426)
Why I did it
fix DX010 fan drawer and watchdog platform test case issues

How I did it
1. Add fan_drawer get_maximum_consumed_power support
2. Adjust maximum watchdog timeout value check

How to verify it
Run test_fan_drawer and test_watchdog test cases.
2023-02-06 09:27:46 -08:00
Ikki Zhu
eba30ff26f
[Celestica Seastone] fix multi sonic platform issues (#13356)
Why I did it
Fix the following issues for Seastone platform:

- system-health issue: show system-health detail will not complete #9530, Celestica Seastone DX010-C32: show system-health detail fails with 'Chassis' object has no attribute 'initizalize_system_led' #11322
- show platform firmware updates issue: Celestica Seastone DX010-C32: show platform firmware updates #11317
- other platform optimization

How I did it
Modify and optimize the platform implememtation.

How to verify it
Manual run the test commands described in these issues.
2023-01-18 16:27:48 -08:00
Jemston Fernando
892f26556c
[platform]: Fix Belgite platform issues (#13389)
As part of platform hardening this commit fixes several platform issues
in various components like PSU, FAN, Temperature, LED.
2023-01-18 10:00:07 -08:00
Ikki Zhu
8ad69f77a4
Seastone add platform capability enhancement config (#13079) 2023-01-04 10:17:50 -08:00
Mai Bui
51a1eb112b
[device/celestica] Mitigation for command injection vulnerability (#11740)
Signed-off-by: maipbui <maibui@microsoft.com>
Dependency: [PR (#12065)](https://github.com/sonic-net/sonic-buildimage/pull/12065) needs to merge first.
#### Why I did it
1. `eval()` - not secure against maliciously constructed input, can be dangerous if used to evaluate dynamic content. This may be a code injection vulnerability.
2. `subprocess()` - when using with `shell=True` is dangerous. Using subprocess function without a static string can lead to command injection.
3. `os` - not secure against maliciously constructed input and dangerous if used to evaluate dynamic content.
4. `is` operator - string comparison should not be used with reference equality.
5. `globals()` - extremely dangerous because it may allow an attacker to execute arbitrary code on the system
#### How I did it
1. `eval()` - use `literal_eval()`
2. `subprocess()` - use `shell=False` instead. use an array string. Ref: [https://semgrep.dev/docs/cheat-sheets/python-command-injection/#mitigation](https://semgrep.dev/docs/cheat-sheets/python-command-injection/#mitigation)
3. `os` - use with `subprocess`
4. `is` - replace by `==` operator for value equality
5. `globals()` - avoid the use of globals()
2022-12-09 10:30:20 -05:00
Ikki Zhu
ad49100985
Seastone: fix platform fan psu and temperature issues (#12567)
Why I did it:
Fix multiple seastone platform issues caused by sonic kernel upgrade.

How I did it:
Get gpio base id with new label path in gpio sys fs.

How to verify it:
After the change, show platform fan/psustatus/temperature works well.
2022-12-05 09:44:55 -08:00
Ying Xie
a544a07931
Enable Dx010 LPM (#12642)
Why I did it
DX010 platform has limited routing table size.

How I did it
Enabling LPM.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-11-09 08:15:41 -08:00
jerseyang
ca546ddec3
Sync platform-modules-belgite deb's kernel version 5.10.0-8-2 with master runtime kernel version 5.10.0-12-2 (#10946)
# Why I did it
platform-modules-belgite's deb requests linux-image-5.10.0-8-2-amd64-unsigned, which does not match the runtime kernel version

# How I did it
update the belgite's deb configuration in deb's control

# How to verify it
check the firsttime boot log in belgite platform

Co-authored-by: nicwu-cel <nicwu@celestica.com>
2022-08-18 12:56:04 +08:00
Ikki Zhu
c9ae87418b
[hlx/sfp] fix hlx platform sfp+ tx disable issue (#11532)
Why I did it:
To fix hlx platform sfp+ module tx disable issue

How I did it:
Fix sfp+ tx disable function according SFF-8472 specification

Co-authored-by: Eric Zhu <erzhu@celestica.com>
2022-07-28 09:39:23 +08:00
Taylor Cai
c0866d68a4
[device/celestica]:Fix failed test case of Seastone snmp (#11430)
* Update psu.py
* Update thermal.py
2022-07-27 12:14:13 +08:00
Kevin Wang
e5d77d779d [Buffer] Separate buffer profile for Celestica-DX010-D48C8
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Ying Xie
61b52a2af7 [buffer] create infrastructure to enable buffer/QoS profiles
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-12 11:48:01 -07:00
zitingguo-ms
e2078627c7
[AN/LT][Fix bug]:enable phy_an_lt_msft attribute on some platforms (#11147) 2022-06-15 17:29:45 -07:00
Taylor Cai
11f0bffe13
[device/celestica]:Fix failed test case of Haliburton snmp (#10844) 2022-05-26 00:06:50 +08:00
jerseyang
c92bfe0728
Add belgite support (#9511)
Why I did it
add celestica belgite platform

How I did it
add belgite platform in celestica

Co-authored-by: nicwu-cel <nicwu@celestica.com>
Co-authored-by: anjian <anjian@celestica.com>
Co-authored-by: sandycelestica <sandyli@celestica.com>
2022-05-23 18:45:37 -07:00
Taylor Cai
988a687182
Fix issue test_crm and test_fib (#10585)
Why I did it
Fix issue (https://github.com/Azure/sonic-buildimage/issues/9171) and (https://github.com/Azure/sonic-buildimage/issues/9236)

How I did it
Add flag in config file for get correct count of IPv6 entry.
Add init config file to set IPv4 ECMP hash on L4.

How to verify it
Compile the sonic_platform wheel for e1031, then upload to device and install the wheel, verify using testbed.
2022-04-22 20:35:52 +08:00
Eric Zhu
4caa887642
Fix issue of partially parsing syseeprom value (#10020) (#10276)
Why I did it
The current code assumes that the value part does not have whitespace. So everything after the whitespace will be ignored. The syseeprom values returned from platform API do not match the output of "show platform syseeprom" on dx010 and e1031 device.

How I did it
This change improved the regular expression for parsing syseeprom values to accommodate whitespaces in the value.
PR 10021 provides the solution, but committed to the wrong place for dx010 and e1031.

How to verify it
Compile the sonic_platform wheel for dx010, then upload to device and install the wheel, verify the platform eeprom API.

Signed-off-by: Eric Zhu <erzhu@celestica.com>
2022-03-21 09:25:36 -07:00
gechiang
ddfe87a71a
[BRCMSAI 6.0.0.13-1] Fix Cancun file directory at new location causing TD3 platform boot issue (#9922) 2022-02-07 08:56:06 -08:00
Christian Svensson
bc56e064c3
[Celestica/Seastone2] Load interface LEDs (#9769)
Tested on a Celestica Seastone2 DX030 switch

Testing scenarios:
- Various QSFP ports in both normal and breakout config.
- 100G and 40G link speed show different colors.
- SFP1 port works.

Signed-off-by: Christian Svensson <blue@cmd.nu>
2022-01-19 00:42:51 -08:00
Viktor Ekmark
1b657becc9
[Celestica Seastone2] Build correct platform files (#9660)
* fix workdir for seastone2

Signed-off-by: Viktor Ekmark <viktor@ekmark.se>

* seastone2: Add I2C SFP definition for SFP1

Signed-off-by: Christian Svensson <blue@cmd.nu>

* [device/cel_seastone_2] sfputil logic for SFP1

Earlier logic resulted in the name of SFP1 being SFP33 which is not
correct. The cannonical source is seastone2_fpga module and it calls it
SFP1, so ensure the logic does as well.

Signed-off-by: Christian Svensson <blue@cmd.nu>

* [device/cel_seastone_2] sysfs paths for SFP1

Various changes that plumbs the correct port presence and DOM decoding
for the SFP1 port.

Signed-off-by: Christian Svensson <blue@cmd.nu>

Co-authored-by: Christian Svensson <blue@cmd.nu>
2022-01-16 12:11:28 +05:30
Aravind Mani
ac2885a988
[SFP-Refactor] Modify transceiver key name (#9447)
* Modify transceiever key name

* fix alignment
2021-12-09 12:38:45 +05:30
Wirut Getbamrung
b28c800f17
[device/celestica]: add controllable config to platform.json of e1031 (#9183) 2021-11-30 13:59:21 +08:00
gechiang
ef457ab13f
Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9199) 2021-11-09 07:21:57 -08:00
Qi Luo
add9b651b6
Add platform_asic file to each platform folder in sonic-device-data based package (#8542)
#### Why I did it
Add platform_asic file to each platform folder in sonic-device-data package. The file content will be used as the ground truth of mapping from PLATFORM_STRING to switch ASIC family.

One use case of the mapping is to prevent installing a wrong image, which targets for other ASIC platforms. For example, currently we have several ONIE images naming as sonic-*.bin, it's easy to mistakenly install the wrong image. With this mapping built into image, we could fetch the ONIE platform string, and figure out which ASIC it is using, and check we are installing the correct image.

After this PR merged, each platform vendor has to add one mandatory text file  `device/PLATFORM_VENDOR/PLATFORM_STRING/platform_asic`, with the content of the platform's switch ASIC family.

I will update https://github.com/Azure/SONiC/wiki/Porting-Guide after this PR is merged.

You can get a list of the ASIC platforms by `ls -b platform | cat`. Currently the options are
```
barefoot
broadcom
cavium
centec
centec-arm64
generic
innovium
marvell
marvell-arm64
marvell-armhf
mellanox
nephos
p4
vs
```

Also support
```
broadcom-dnx
```

#### How I did it

#### How to verify it
Test one image on DUT. And check the folders under `/usr/share/sonic/device`
2021-10-08 19:27:48 -07:00
Wirut Getbamrung
800de696db
[Celestica/sonic_platform]: Fixed failed test cases in Haliburton platform testing (#8815)
* [device/celestica-e1031]: fix apis follow lastest spec
* [device/celestica-e1031]: fix lgtm (#261)
2021-10-08 11:10:05 +08:00
Ashok Daparthi-Dell
6cbdf11e53
SONIC QOS YANG - Remove qos tables field value refernce format (#7752)
Depends on Azure/sonic-utilities#1626
Depends on Azure/sonic-swss#1754

QOS tables in config db used ABNF format i.e "[TABLE_NAME|name] to refer fieldvalue to other qos tables.

Example:
Config DB:
"Ethernet92|3": {
"scheduler": "[SCHEDULER|scheduler.1]",
"wred_profile": "[WRED_PROFILE|AZURE_LOSSLESS]"
},
"Ethernet0|0": {
"profile": "[BUFFER_PROFILE|ingress_lossy_profile]"
},
"Ethernet0": {
"dscp_to_tc_map": "[DSCP_TO_TC_MAP|AZURE]",
"pfc_enable": "3,4",
"pfc_to_queue_map": "[MAP_PFC_PRIORITY_TO_QUEUE|AZURE]",
"tc_to_pg_map": "[TC_TO_PRIORITY_GROUP_MAP|AZURE]",
"tc_to_queue_map": "[TC_TO_QUEUE_MAP|AZURE]"
},

This format is not consistent with other DB schema followed in sonic.
And also this reference in DB is not required, This is taken care by YANG "leafref".

Removed this format from all platform files to consistent with other sonic db schema.
Example:
"Ethernet92|3": {
"scheduler": "scheduler.1",
"wred_profile": "AZURE_LOSSLESS"
},

Dependent pull requests:
#7752 - To modify platfrom files
#7281 - Yang model
Azure/sonic-utilities#1626 - DB migration
Azure/sonic-swss#1754 - swss change to remove ABNF format
2021-09-28 09:21:24 -07:00
yozhao101
e46dd633d8
[healthd] Add system health configuration for platform Celestica E1031 (#8783)
This PR aims to fix the healthd crash issue by adding system health monitoring configuration file for platform Celestica E1031 by adding a new configuration file under the path device/celestica/x86_64-cel_e1031-r0/.

How to verify it
I manually restart the system-health.service and confirmed that healthd is running.

Signed-off-by: Yong Zhao <yozhao@microsoft.com>
2021-09-18 10:31:36 -07:00
gechiang
df66c88572
BRCM Disable ACL Drop counted towards interface RX_DRP counters part II (#8596) 2021-08-26 00:18:04 -07:00
Christian Svensson
c64b08fb9d
[cel seastone 2] Add 10G SFP1 front port (#8267)
Why I did it
The SFP1 port was disabled in the default configuration.

How I did it
This commit enables the 10G front port for usage.
This was done using a DX030 together with an Arista switch using bcmsh and phy diag xe0 dsc to figure out what lane mappings make sense.

Validated on Celestica Seastone2 DX030.

How to verify it
Own a Celestica DX030
Connect the front SFP1 port to something.
It works :-)
You can do tcpdump -i Ethernet128 -n and you will see both incoming and outgoing LLDP.
2021-08-17 10:11:16 -07:00
gechiang
8e903f4566
BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8382)
* BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-10 19:03:22 -07:00
Wirut Getbamrung
4bf873bf42
[device/celestica]: Fix failed test cases of Haliburton platform API (#7579)
- Why I did it
To fix failed test cases of Haliburton platform APIs that found on platform_tests script
- How I did it
Add device/celestica/x86_64-cel_e1031-r0/platform.json
Update functions to support python3.7
Add more functions follow latest sonic_platform_base
Fix the bug
- How to verify it
Run platform_tests script

Signed-off-by: Wirut Getbamrung [wgetbumr@celestica.com]
2021-07-23 06:18:39 -07:00
Wirut Getbamrung
4ae6d3f5c9
[device/celestica]: Fix remaining failed test cases of Seastone-DX010 platform API (#7743)
**- Why I did it**
- To fix failed test cases of Seastone-DX010 platform APIs that found on [platform_tests](https://github.com/Azure/sonic-mgmt/tree/master/tests/platform_tests/api) script

**- How I did it**
1. Add device/celestica/x86_64-cel_seastone-r0/platform.json 
2. Update functions to support python3.7
3. Add more functions follow latest sonic_platform_base
4. Fix the bug
2021-05-28 12:56:09 -07:00
Wirut Getbamrung
cfda77b3de
[device/celestica]: Add thermalctld support on Haliburton platform APIs (#6493)
- Removed the old function for detecting a faulty fan.
- Removed the old function for detecting excess temperature.
- Implement thermal_manager APIs based on ThermalManagerBase
- Implement thermal_conditions APIs based on ThermalPolicyConditionBase
- Implement thermal_actions APIs based on ThermalPolicyActionBase
- Implement thermal_info APIs based on ThermalPolicyInfoBase
- Add thermal_policy.json
2021-05-03 09:14:35 -07:00
Wirut Getbamrung
fbcb9403e8
[device/celestica]: Fix failed test cases of DX010 platform APIs (#6564)
1. Add device/celestica/x86_64-cel_seastone-r0/platform.json 
2. Update functions to support python3.7
3. Add more functions follow latest sonic_platform_base
4. Fix the bug

Co-authored-by: 119064273 <2276096708@qq.com>
Co-authored-by: Eric Zhu <erzhu@celestica.com>
Co-authored-by: doni@celestica.com <doni@celestica.com>
2021-04-02 10:08:31 -07:00
Ying Xie
197dd4e675
[e1031] add GbE and higig port to E1031 port_config.ini (#7208)
Why I did it
These ports are being enumerated by the latest SAI. But they are not defined in port_config.ini.

SONiC end up trying to delete these 3 ports and hit SAI error and crash.

How I did it
Add the GbE and the 2 HiGig ports in the port_config.ini.

How to verify it
Put the port_config.ini on a device crashing with port deleting. load minigraph and the crash stopped.

Signed-off-by: Ying Xie ying.xie@microsoft.com
2021-04-01 07:46:03 -07:00
Dmytro Shevchuk
d8627e6414
[yang] update yang model, add autoneg to sonic-port (#5963)
Dynamic Port Breakout fall in case "autoneg" field exist in config_db.

- How I did it
Added "autoneg" field in sonic-port yang model.

- How to verify it
Add "autoneg" field into config_db like this:

"Ethernet8": {
    "index": "2", 
    "lanes": "8,9,10,11", 
    "fec": "rs", 
    "pfc_asym": "off", 
    "mtu": "9100", 
    "alias": "Ethernet8", 
    "admin_status": "up", 
    "autoneg": "on", 
    "speed": "100000",
},
2021-03-30 08:27:58 -07:00
Wirut Getbamrung
6ae2cb5607
[device/celestica]: Add xcvrd event support for Haliburton (#6517)
#### Why I did it
- The xcvrd service requires an event detection function, unplug or plug in the transceiver.

#### How I did it
- Add sysfs interrupt to notify userspace app of external interrupt
- Implement get_change_event() in chassis api.
- Also begin installing Python 3 sonic-platform package for Celestica platforms
2021-03-08 10:10:11 -08:00
Sangita Maity
18263c99dd
[DPB|master] Update Dynamic Port Breakout Logic for flexible alias support a… (#6831)
To fix [DPB| wrong aliases for interfaces](https://github.com/Azure/sonic-buildimage/issues/6024) issue, implimented flexible alias support [design doc](https://github.com/Azure/SONiC/pull/749)

> [[dpb|config] Fix the validation logic of breakout mode](https://github.com/Azure/sonic-utilities/pull/1440) depends on this

#### How I did it

1. Removed `"alias_at_lanes"` from port-configuration file(i.e. platfrom.json) 
2. Added dictionary to "breakout_modes" values. This defines the breakout modes available on the platform for this parent port, and it maps to the alias list. The alias list presents the alias names for individual ports in order under this breakout mode.
```
{
    "interfaces": {
        "Ethernet0": {
            "index": "1,1,1,1",
            "lanes": "0,1,2,3",
            "breakout_modes": {
                "1x100G[40G]": ["Eth1"],
                "2x50G": ["Eth1/1", "Eth1/2"],
                "4x25G[10G]": ["Eth1/1", "Eth1/2", "Eth1/3", "Eth1/4"],
                "2x25G(2)+1x50G(2)": ["Eth1/1", "Eth1/2", "Eth1/3"],
                "1x50G(2)+2x25G(2)": ["Eth1/1", "Eth1/2", "Eth1/3"]
            }
        }
}
```
#### How to verify it
`config interface breakout`

Signed-off-by: Sangita Maity <samaity@linkedin.com>
2021-02-26 00:13:33 -08:00
Joe LeVeque
c6178259fc
[Celestica] Ensure concrete platform API classes call base class initializer (#6852)
In preparation for the merging of Azure/sonic-platform-common#173, which properly defines class and instance members in the Platform API base classes.

It is proper object-oriented methodology to call the base class initializer, even if it is only the default initializer. This also future-proofs the potential addition of custom initializers in the base classes down the road.
2021-02-25 11:20:53 -08:00
Sujin Kang
d5238ae8dd
[pcie.yaml] Move pcie configuration file path to platform directory (#6475)
- Why I did it
The pcie configuration file location is under plugin directory not under platform directory.
#6437

- How I did it

Move all pcie.yaml configuration file from plugin to platform directory.
Remove unnecessary timer to start pcie-check.service
Move pcie-check.service to sonic-host-services
- How to verify it
Verify on the device
2021-02-21 08:27:37 -08:00
Joe LeVeque
18f2c5cfdd
[platform] Update QSFP method name 'parse_qsfp_dom_capability' -> 'parse_dom_capability' (#6695)
**- Why I did it**
PR https://github.com/Azure/sonic-platform-common/pull/102 modified the name of the SFF-8436 (QSFP) method to align the method name between all drivers, renaming it from `parse_qsfp_dom_capability` to `parse_dom_capability`. Once the submodule was updated, the callers using the old nomenclature broke. This PR updates all callers to use the new naming convention.

**- How I did it**

Update the name of the function globally for all calls into the SFF-8436 driver.

Note that the QSFP-DD driver still uses the old nomenclature and should be modified similarly. I will open a PR to handle this separately.
2021-02-05 14:41:05 -08:00