Commit Graph

23 Commits

Author SHA1 Message Date
Stephen Sun
386f4e190a
[Mellanox] [201911] Support shared headroom pool (#5908) 2021-01-07 09:20:22 +02:00
Nazarii Hnydyn
0b7518b7b5 [Mellanox] Update platform components config files. (#5685)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2020-11-03 08:19:19 -08:00
Stephen Sun
fa99059b51 Update buffer configuration for SKUs based on SN3800 (#5320)
C64: 32 100G down links and 32 100G up links.
D112C8: 112 50G down links and 8 100G up links.
D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2020-09-28 16:16:45 +00:00
Nazarii Hnydyn
d46dc0ff25 [Mellanox] Update platform components config files. (#5360)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2020-09-19 14:10:07 -07:00
Stephen Sun
f6a8678d8f
Support single ingress pool for MSFT SKUs and optimize headroom calculation (#5194)
This is to backport the #4886 to 201911

Calculate pool size in t1 as 24 * downlink port + 8 * uplink port

- Take both port and peer MTU into account when calculating headroom
- Worst case factor is decreased to 50%
- Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports
- Mellanox-SN2700 (C32)
  - t0: 16 * 100G/5m + 16 * 100G/40m
  - t1: 16 * 100G/40m + 16 * 100G/300m

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2020-08-15 07:52:28 -07:00
Stephen Sun
b76f8fafdb [Mellanox] Update the buffer setting (#4989)
* Update the buffer size based on the latest excel

Signed-off-by: Stephen Sun <stephens@mellanox.com>

* Align the buffer configuration with the latest formula:

- reduce redundant "*2" in formula
- use port MTU for local sending the PFC frame and peer lossless MTU for peer sending lossless traffic

Buffer pool size updated accordingly.

Signed-off-by: Stephen Sun <stephens@mellanox.com>
2020-08-03 23:06:21 -07:00
Junchao-Mellanox
acafde1895 [Mellanox] Change port index in port_config.ini to 1-based (#4781)
* Change port index in port_config.ini to 1-based
* Add default port index to port_config.ini, change platform plugins to accept 1-based port index
* fix port index in sfp_event.py
2020-06-28 07:24:10 -07:00
madhanmellanox
33e2264746 added files to create SKU Mellanox-SN3800-D24C52 (#4808)
* added files to create SKU Mellanox-SN3800-D24C52

Co-authored-by: Madhan Babu <madhan@arc-build-server.mtr.labs.mlnx>
2020-06-28 07:22:12 -07:00
madhanmellanox
67e183d0dc added files to create SKU Mellanox-SN3800-C64 (#4812)
* added files to create SKU Mellanox-SN3800-C64
Co-authored-by: Madhan Babu <madhan@arc-build-server.mtr.labs.mlnx>
2020-06-22 17:39:31 -07:00
madhanmellanox
b94c12d920 modified files relevant to SKU Mellanox-SN3800-D112C8 (#4810)
* modified files relevant to SKU Mellanox-SN3800-D112C8

Co-authored-by: Madhan Babu <madhan@arc-build-server.mtr.labs.mlnx>
2020-06-22 17:38:42 -07:00
madhanmellanox
415000b8b2 added files to create SKU Mellanox-SN3800-D28C50 (#4809)
* added files to create SKU Mellanox-SN3800-D28C50

Co-authored-by: Madhan Babu <madhan@arc-build-server.mtr.labs.mlnx>
2020-06-22 17:37:46 -07:00
Junchao-Mellanox
0a70571011
[201911][thermal control] Backport feature from master branch (#4677)
Backport thermal control feature from master branch to 201911 branch by cherry-picking commits and manually resolving conflicts.
2020-06-08 11:20:43 -07:00
Nazarii Hnydyn
c266435d40
Revert "Add thermal control support for SONiC (#3949)" (#4527)
This reverts commit 109a13cc03.

Conflicts:
	dockers/docker-platform-monitor/docker-pmon.supervisord.conf.j2
2020-05-04 21:20:47 +03:00
Junchao-Mellanox
109a13cc03 Add thermal control support for SONiC (#3949) 2020-04-30 22:39:17 -07:00
Stephen Sun
56072ce938 [Mellanox] Fix error in sensors.conf for 3700/3700c/3800 (#4506) 2020-04-30 22:18:18 -07:00
Stephen Sun
b646045958 [Mellanox]Mellanox-SN3800-D112C8 support warm-reboot (#4482) 2020-04-30 22:15:12 -07:00
Mykola F
aa30030fd1 [devices][Mellanox] create sai.xml for MSN3800-D112-C8 (#4334)
sai_xml contains info about port splits, previously it simply linked to the MSN3800 sai xml, which does not have splits. New version describes splits and speeds according to Mellanox-SN3800-D112-C8 SKU.

Practically it can cause port recreation on SAI init.

Signed-off-by: Mykola Faryma <mykolaf@mellanox.com>
2020-04-01 23:28:43 -07:00
Stephen Sun
774487badc [Mellanox] Calculate the buffer size based on the latest excel and with gearbox considered (#4239) 2020-03-14 18:01:39 -07:00
Nazarii Hnydyn
651f4a068e [mellanox] Add fwutil platform components. (#3999)
Signed-off-by: Nazarii Hnydyn <nazariig@mellanox.com>
2020-02-24 10:15:38 -08:00
Stepan Blyshchak
3ba436118d [mellanox] enable ISSU on SPC2 systems (#4087)
Signed-off-by: Stepan Blyschak <stepanb@mellanox.com>
2020-02-13 16:03:42 -08:00
Nazarii Hnydyn
a4ca818ca9 [mellanox]: Add new Mellanox-SN3800-D112C8 sku. (#4085)
Signed-off-by: Nazarii Hnydyn <nazariig@mellanox.com>
2020-02-03 15:39:14 -08:00
Nazarii Hnydyn
37ba921449 [mellanox] Update SN3800 device configs. (#3633)
Signed-off-by: Nazarii Hnydyn <nazariig@mellanox.com>
2019-10-19 12:11:58 +03:00
Nazarii Hnydyn
c6e442b946 [mellanox]: Added SN3800 platform (#3262)
* [mellanox]: Added SN3800 platform.

Signed-off-by: Nazarii Hnydyn <nazariig@mellanox.com>
2019-08-01 16:25:44 -07:00