Commit Graph

621 Commits

Author SHA1 Message Date
Arun Saravanan Balachandran
33ef26d97b
[201911] DellEMC: S6000, S6100 - Enable thermalctld, Platform API changes (#9384)
Why I did it
To incorporate the below changes in DellEMC S6100, S6000 platforms.

Enable thermalctld
Backport Platform API changes from master branch.
How I did it
Remove 'skip_thermalctld:true' in pmon_daemon_control.json
Implement the platform API methods in the respective device files
How to verify it
Verified that platform data is displayed by show platform fan and show platform temperature commands.
2021-12-10 12:23:22 -08:00
abdosi
cff7fbb5c1 Added 40G {300/40/5m} pg lookup profile for 7260 100G SKU (#9249)
What I did:
Added 40G {300/40/5m} profile for 7260 100G SKU
2021-11-24 18:57:01 -08:00
Santhosh Kumar T
ddf40cb729
[201911] Dell S6000 I2C not responding to certain optics - porting (#8855) 2021-10-25 15:25:12 +05:30
shihjeff
940aaa0cbe
[201911] [Innovium] Update Cameo & Wistron Drivers (#7855)
Fix #8068

Update Innovium configs on Cameo and Wistron platforms
2021-07-21 09:09:36 -07:00
madhanmellanox
2bec3004ef
[201911] Adding SKU Mellanox-SN3800-D100C12S2 (#7972)
* [201911]: Adding SKU Mellanox-SN3800-D100C12S2
Co-authored-by: Madhan Babu <madhan@l-csi-0241l.mtl.labs.mlnx>
2021-06-30 09:04:52 -07:00
Neetha John
86c2f4248c
Update PG profile settings for Arista-7050QX-32S-S4Q31 (#7674)
PG profile settings need to be aligned with Arista-7050-QX-32S
2021-06-15 15:01:40 -07:00
abdosi
86a11e5a1e
Updated 7260 MMU Profile based on latest MSFT Tier 1 (#7882)
Updated 7260 MMU Profile based on latest MSFT Tier 1 Tomahawk2_MMU_Setting_48x100G_40m_16x100G_300m_v1.0 and
TH2_PGHdrm_MSFT

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2021-06-15 13:08:47 -07:00
Ying Xie
0e82381335 [7050] updating 7050 MMU configurations (#7801)
Why I did it
7050 S4Q31 mmu configuration is missing ALPM configurations, causing not enough memory reserved for routes. Orchagent crashes on a nightly testbed with 6400 route entries.

How I did it
Add the missing ALPM configurations.

How to verify it
Load the configuration on testbed and verified new configuration exists and no more crash.

Signed-off-by: Ying Xie ying.xie@microsoft.com
2021-06-14 13:56:01 -07:00
Neetha John
27985784eb Rename AristaQX-32S skus (#7751)
This PR contains the following changes
Original Arista-7050-QX-32S sku (32x40G ports) has been renamed to Arista-7050QX32S-Q32
Arista-7050-QX-32S is symlinked to Arista-7050QX-32S-S4Q31 (4x10G, 31x40G ports)

Signed-off-by: Neetha John <nejo@microsoft.com>
2021-05-31 08:02:06 -07:00
Neetha John
df61f462d5 Update MMU and QOS settings for Arista-7050QX-32S-S4Q31 (#7672)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
Need proper MMU and Qos settings for Arista-7050QX-32S-S4Q31

How I did it
Updated the settings based on Arista-7050-QX-32S
2021-05-31 08:01:26 -07:00
Ying Xie
897b4d2b32 [Arista] add MMU configuration for Arista 7260 C64 (#7027)
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2021-05-31 07:46:38 -07:00
Stephen Sun
d44936fa59
[Mellanox][201911] Support buffer configuration for 2km cable (#7338)
#### Why I did it
1. Update pg_profile_lookup.ini with 2000m cable supported
2. Update buffer configuration for t1 with uplink cable 2000m
  - For SN3800 platform:
    - C64:
      - t0: 32 100G down links and 32 100G up links.
      - t1: 56 100G down links and 8 100G up links with 2 km cable.
    - D112C8: 112 50G down links and 8 100G up links.
    - D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
    - D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.
  - For SN2700 platform:
    - D48C8: 48 50G down links and 8 100G up links
    - C32:
      - t0: 16 100G down links and 16 100G up links.
      - t1: 24 100G down links and 8 100G up links with 2 km cable.

Signed-off-by: Stephen Sun <stephens@nvidia.com>

#### How I did it

#### How to verify it
Run QoS regression test
2021-05-30 20:03:16 -07:00
Kebo Liu
4955956b51
Correct the Spectrum-2 platform PSU sensor's label in the sensor conf file (#7707)
#### Why I did it
The label for PSU related sensors on the Spectrum-2 platform is not aligned with the physical location of the PSU.

#### How I did it
Update the label in the sensor conf file for those relevant platforms

Signed-off-by: Kebo Liu <kebol@nvidia.com>
2021-05-25 13:50:53 -07:00
Tony Titus
fbd4e452c7
[201911] [Innovium] Add new platforms and config updates (#7545)
Update Innovium configs + Add new platforms supporting Innovium chips
2021-05-17 12:30:20 -07:00
Prince Sunny
68b717b556 Vxlan src port range for breakout SKU (#7612)
*Extended Vxlan src port range for lab breakout SKU - Mellanox-SN3800-D112C8
2021-05-14 11:42:58 -07:00
Andriy Yurkiv
eb87eb664d [Mellanox] Add support to VXLAN src port range setting via SAI profile for r SN3800-D28C49S1 (#7500)
- Why I did it
Enable VXLAN src port range configuration via SAI profile for Mellanox-SN3800-D28C49S1 SKU

- How I did it
Added SAI_VXLAN_SRCPORT_RANGE_ENABLE=1 configuration to appropriate sai.profile

Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>
2021-05-14 11:41:35 -07:00
Junchao-Mellanox
e592984991
[Mellanox] [201911] Support new sensor conf file for MSN4700 A1/A0 (#7536)
#### Why I did it

MSN4700 A1/A0 used different sensor chip but keep the existing platform name *x86_64-mlnx_msn4700-r0*, this is a workaround to replace the sensor conf on MSN4700 A1/A0

#### How I did it

Use a shell script to get the sensor conf path and copy that files to /etc/sensors.d/sensors.conf
2021-05-06 15:01:35 -07:00
Andriy Yurkiv
4ff9f29350 [devices][hwsku] add support to VXLAN src port range feature (#7394)
Enable VXLAN src port range configuration via SAI profile
2021-05-03 18:30:41 -07:00
madhanmellanox
da6cf08917
[201911] Created a new 3800 SKU - D28C49S1 (#7312) 2021-04-23 14:48:50 -07:00
Aravind Mani
89adef3032
[201911] Dell S6100: Modify transceiver change event from interrupt to poll mode (#7334)
#### Why I did it

- xcvrd crash was seen in latest 201811 images.
- For Dell S6100,API 2.0 uses poll mode while 1.0 was still using interrupt mode.

#### How I did it

- Modified get_transceiver_change_event in 1.0 to poll mode in all the related branches.

Backport of https://github.com/Azure/sonic-buildimage/pull/7309 to the 201911 branch
2021-04-20 15:23:48 -07:00
rkdevi27
47011a8e2c
[201911][DellEMC] Fix abrupt reboot in S6000 (#6909)
The S6000 devices, the cold reboot is abrupt and it is likely to cause issues which will cause the device to land into EFI shell. Hence the platform reboot will happen after graceful unmount of all the filesystems as in S6100.
2021-03-30 16:14:45 -07:00
shlomibitton
ac7f831357
Fix for all SPC1 devices sai profile speed configurations (#7120)
#### Why I did it
SAI profile files speed configuration have wrong bitmap value for 10/50G speed option.

#### How I did it
Fix to the correct value for all SPC1 devices.

#### How to verify it
Configure on these platforms ports with 10/50G speed using this fix.
2021-03-22 14:36:55 -07:00
Junchao-Mellanox
5cf9c369e9 Change buffer config for new SKU Mellanox-SN2700-D40C8S8 (#6926)
#### Why I did it

Change buffer config for new SKU Mellanox-SN2700-D40C8S8

#### How I did it

Reuse the buffer config of SKU Mellanox-SN2700-D48C8

#### How to verify it

Run sonic-mgmt qos test and all passed
2021-03-04 22:45:45 -08:00
Lior Avramov
c7b9aa7fb4
[thermalctld] Disable thermalctld on Mellanox simx platforms (#6855)
Signed-off-by: liora <liora@nvidia.com>

Co-authored-by: liora <liora@nvidia.com>
2021-03-03 11:33:27 -08:00
SuvarnaMeenakshi
272781855e [multi-asic][vs]: Add new multi-asic vs hwsku with four asics (#6558)
- Why I did it
Current mutli-asic vs hwsku consists of 6 asics with each asic having 32 interfaces. When bringing this up, below issue was seen:
When all 32 interfaces(sonic interfaces and linux interface) are set to 9100 mtu, DMA error is seen "DMA: Out of SW-IOMMU space for 4096 bytes at device 0000:06:03.0" which can be fixed by updating swiotlb=65536 in /host/grub/grub.cfg .In order to keep multi-asic VS lighter and easier to bring up and test, new hwsku 'msft_four_asic_vs' is added to represent 4-asic hwsku with 2 frontend asics and 2 backend asics and each asic having 8 interfaces interconnected by port-channels.
- How I did it
Add msft_four_asic_hwsku directory to have the right number of directories (4) and update port_config.ini and lanemap.ini files to include 8 ports information.
Add topology.sh script to create the internal asic-asic connectivity.
- How to verify it
Update asic.conf with the 4 asic information as below and build sonic-vs.img:
NUM_ASIC=4
DEV_ID_ASIC_0=0
DEV_ID_ASIC_1=1
DEV_ID_ASIC_2=2
DEV_ID_ASIC_3=3
Modify sonic_multiasic.xml to have 8 front panel interfaces.
create virtual switch using "sudo virsh sonic_mutliasic.xml" command.
Start topology service and Load config_db files for switch and each asic.
Ensure that that all internal interfaces and port_channels are coming up.
multi-asic vs testbed:
Bring up mutli-asic VS testbed with a multi-asic image(asic.conf updated to 4 asics) and using t1-lag topology.
./testbed-cli.sh -t vtestbed.csv -m veos_vtb -k ceos add-topo vms-kvm-four-asic-t1-lag password.txt
Load minigraph/config_dbs.
Ensure all internal and external interfaces come up.
No change on single asic vs.
2021-02-25 18:55:21 -08:00
SuvarnaMeenakshi
f694787521 [vs]: Update swiotlb buffer size to support multi-asic VS platform. (#6674)
Current mutli-asic vs hwsku consists of 6 asics with each asic having 32 interfaces.
When bringing this up, below issue was seen:
When all 32 interfaces in each namespace (sonic interfaces and linux interface) is set to 9100 mtu, DMA error is seen "DMA: Out of SW-IOMMU space for 4096 bytes at device 0000:06:03.0" which can be fixed by updating swiotlb=65536 in /host/grub/grub.cfg .

Signed-off-by: SuvarnaMeenakshi <sumeenak@microsoft.com>
2021-02-25 18:43:15 -08:00
SuvarnaMeenakshi
9208dc507b [multi-asic][vs]: Update topology script to retrieve hwsku from minigraph (#6219)
Update topology script to retrieve hwsku from minigraph
if hwsku information is not available in config_db.
Fix clean up of interfaces in msft_multi_asic_vs hwsku
topology script.
- Why I did it
When bringing up multi-asic VS switch, topology service is started during boot up.
Topology service starts a shell script which runs the topology script present in /usr/share/sonic/device// directory. To invoke hwsku specific script, the topology script tries to retrieve hwsku information from config_db.
During initial boot up config_db might not be populated. In order to start topology service before config_db is updated,
update topology script to get hwsku information from minigraph.xml if it is available.
This will be helpful to bring up multi-asic VS testbed by loading minigraph and starting topology service.
- How I did it
Update topology.sh script to retrieve hwsku information from minigraph.xml.
Fix clean up function on msft_multi_asic_vs toplogy script.
- How to verify it
single-asic VS - no change; topology service is only enabled for multi-asic VS.
multi-asic VS - Bring up multi-asic VS image, copy minigraph to vs image, start topology service. Topology service should be successful.
to test clean up function fix, start topology service - make sure interfaces are created and moved to the right namespaces.
stop topology service - make sure namespace do not have any interface and all front end interfaces are present in default namespace.
2021-02-25 18:42:44 -08:00
Dror Prital
940944e41c
Support new SKU under the name of SN2700-D40C8S8 (#6822)
#### Why I did it

Add new SKU for SN2700 Mellanox system that supports the following port configuration:
8 X 100G
40 X 50G
8 X 10G

#### How I did it

Add new Folder - "Mellanox-SN2700-D40C8S8" under /sonic-buildimage/device/mellanox/x86_64-mlnx_msn2700-r0/
that contains the relevant files supporting this SKU

#### How to verify it

Bring up the image, run "show interface status" and make sure that all ports are up and reflect the following requirement:
Port 1/3 will be used as 4x10G
Port 2/4 - Not exist (blocked since 1 and 3 split to 4)
Port 7/8/9/10/23/24/25/26 will used as 100G
All other ports will be used as 2x50G

#### Which release branch to backport (provide reason below if selected)

- [ ] 201811
- [X] 201911
- [ ] 202006
- [ ] 202012

#### Description for the changelog

Support new SKU under the name of SN2700-D40C8S8
2021-02-21 09:24:45 -08:00
Wirut Getbamrung
a5de91069c [device/celestica]: Add thermalctld support on DX010 platform APIs (#6089)
**- Why I did it**
- The thermalctld daemon on the Pmon docker requires support from the thermal manager API.

**- How I did it**
- Removed the old function for detecting a faulty fan.
- Removed the old function for detecting excess temperature.
- Implement thermal_manager APIs based on ThermalManagerBase
- Implement thermal_conditions APIs based on ThermalPolicyConditionBase
- Implement thermal_actions APIs based on ThermalPolicyActionBase
- Implement thermal_info APIs based on ThermalPolicyInfoBase
- Add thermal_policy.json
2021-02-18 18:09:57 -08:00
Volodymyr Boiko
06334ff438 [barefoot][device][plugins] Fix sfp reset (#6745)
Fix sfp reset in Barefoot's sfputil

Signed-off-by: Volodymyr Boyko <volodymyrx.boiko@intel.com>
2021-02-18 18:07:49 -08:00
zzhiyuan
511541f7f0
[Arista] Use thermalctld instead of fancontrol (#6173)
**- Why I did it**
There is a preference to use thermalctld instead of fancontrol for 201911 release branch. The Arista platform submodule updates and thermal policies in the platforms will allow Arista devices to use thermalctld instead of fancontrol.

**- How I did it**
I cherry-picked the necessary commits from master branch for sonic-platform-modules-arista into 201911 branch. I've also added the file to skip fancontrol and added the thermal policies json.

**- How to verify it**
On Gardena, Upperlake, Clearlake, and Lodoga thermalctld is up and running with no errors. Fans show ~29%.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2021-01-27 08:31:32 -08:00
Stephen Sun
386f4e190a
[Mellanox] [201911] Support shared headroom pool (#5908) 2021-01-07 09:20:22 +02:00
Myron Sosyak
64acd48012
[Barefoot] [201911] Fix default profile for Newport (#6307)
Fix default profile for Newport platform

Signed-off-by: Volodymyr Boyko <volodymyrx.boiko@intel.com>
2021-01-05 10:08:52 -08:00
Junchao-Mellanox
547ec0a905 Add a configuration to delay start xcvrd for fast-reboot (#5643) 2020-12-22 09:51:54 -08:00
Aravind Mani
add9752bff [devices]: DellEMC Z9264f buffer changes (#5429)
**- Why I did it**
Converted two SP model to single pool model and modified the buffer size.
**- How I did it**
Changed buffer_default settings for all the DellEMC Z9264f HWSKU's.
**- How to verify it**
Check SP register values in NPU shell.
**- Which release branch to backport (provide reason below if selected)**
Need to be cherry picked for 201911 branch.
2020-11-14 12:25:19 -08:00
Lawrence Lee
cb32b362f5 Make backend device checking more robust (#5730)
Treat devices that are ToRRouters (ToRRouters and BackEndToRRouters) the same when rendering templates
 Except for BackEndToRRouters belonging to a storage cluster, since these devices have extra sub-interfaces created
Treat devices that are LeafRouters (LeafRouters and BackEndLeafRouters) the same when rendering templates

Signed-off-by: Lawrence Lee <lawlee@microsoft.com>
2020-11-14 08:39:08 -08:00
shlomibitton
ed186405dd Fix MSN4700 sensors labels (#5861)
Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2020-11-10 12:28:40 -08:00
Aravind Mani
825e05ae95
DellEMC Z9264f: Fix show version error (#5808)
import os.path in eeprom.py to fix the issue
2020-11-05 00:19:51 -08:00
Nazarii Hnydyn
0b7518b7b5 [Mellanox] Update platform components config files. (#5685)
Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
2020-11-03 08:19:19 -08:00
shlomibitton
40190298ca [Mellanox] Add sensors labels for human readable output for MSN2010 (#5658)
Add sensors labels for human readable output for MSN2010

Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2020-11-03 08:19:19 -08:00
shlomibitton
86249769d3 [Mellanox] Add sensors labels for human readable output for MSN2100 (#5659)
Add sensors labels for human readable output for MSN2100

Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2020-11-03 08:19:19 -08:00
shlomibitton
00638f51bf [Mellanox] Add sensors labels for human readable output for MSN2410 (#5660)
Add sensors labels for human readable output for MSN2410
2020-11-03 08:19:19 -08:00
shlomibitton
fcce160bdc [Mellanox] Add sensors labels for human readable output for MSN2700 (#5661)
Add sensors labels for human readable output for MSN2700

Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2020-11-03 08:19:19 -08:00
shlomibitton
31109194c2 [Mellanox] Add sensors labels for human readable output for MSN2740 (#5662)
Add sensors labels for human readable output for MSN2740
2020-11-03 08:19:19 -08:00
shlomibitton
55f6ed8288 [Mellanox] Fixes sensors labels for human readable output for MSN3420 (#5664)
Fixes sensors labels for human readable output for MSN3420

Signed-off-by: Shlomi Bitton <shlomibi@nvidia.com>
2020-11-03 08:19:19 -08:00
Aravind Mani
3734bf326b
[201911] DellEMC platform API 2.0 for Z9264f, S5232f (#5637)
Add platform API 2.0 support for Z9264f, S5232f in 201911 branch
2020-10-28 10:01:47 -07:00
Tony Titus
05dc6834c2
[201911] Update Innovium device support (#5341)
- Add new device delta_evs-a-32q56 support for Innovium
- Update qos and buffer json files
- Update Innovium config files
2020-10-07 10:51:24 -07:00
Kebo Liu
46e57e050c [Mellanox] Refactor SFP related platform API and plugins with new SDK API (#5326)
Refactor SFP reset, low power get/set API, and plugins with new SDK SX APIs. Previously they were calling SDK SXD APIs which have glibc dependency because of shared memory usage.

Remove implementation "set_power_override", "tx_disable_channel", "tx_disable" which using SXD APIs, once related SDK SX API available, will add them back based on new SDK SX APIs.
2020-09-29 15:39:52 +00:00
jostar-yang
1def4ed15f [as7326-56x]Fix port_eeprom i2c mapping (#5466)
**- Why I did it**
There is error i2c mapping for port 11,12 and port 19, 20. 

**- How I did it**
Fix to correct i2c mapping

Co-authored-by: Jostar Yang <jostar_yang@accton.com.tw>
2020-09-28 16:21:19 +00:00
Stephen Sun
fa99059b51 Update buffer configuration for SKUs based on SN3800 (#5320)
C64: 32 100G down links and 32 100G up links.
D112C8: 112 50G down links and 8 100G up links.
D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2020-09-28 16:16:45 +00:00