3 Commits

Author	SHA1	Message	Date
Sudharsan Dhamal Gopalarathnam	434a641026	[DPB][Mellanox]Fixing DPB modes in Mellanox-SN2700-D40C8S8 (#8953) ... #### Why I did it Fixing https://github.com/Azure/sonic-buildimage/issues/8938 Fixing 1x10G DPB mode in Mellanox-SN2700-D40C8S8 SKU as it was causing sonic-cfggen to fail. #### How I did it Added correct mode format in hwksu.json in Mellanox-SN2700-D40C8S8 and updated platform.json for the new mode. #### How to verify it Using sonic-cfggen verify it works fine	2021-10-12 18:16:13 -07:00
Alexander Allen	5259af2e2b	[mellanox] remove 2x40G and 4x40G breakout modes due to no hardware support (#8280) ... Mellanox platforms do not support 2x40G or 4x40G breakout modes. Signed-off-by: Alexander Allen <arallen@nvidia.com>	2021-08-01 13:24:26 -07:00
Dror Prital	b85caa581f	[DPB] [Mellanox] added capability files for SN2700-D40C8S8 SKU (#6878) ... #### Why I did it Additional file for DPB in order to support SKU SN2700-D40C8S8 on master #### How I did it Add hwsku.json file #### How to verify it Enforce "Mellanox-SN2700-D40C8S8 SKU on Master and see it works as expected, meaning: Port 1/3 will be used as 4x10G Port 2/4 - Not exist (blocked since 1 and 3 split to 4) Port 7/8/9/10/23/24/25/26 will used as 100G All other ports will be used as 2x50G This PR should be added on top of PR: https://github.com/Azure/sonic-buildimage/pull/6876 #### Description for the changelog Adding hwsku.json file to SN2700-D40C8S8 SKU	2021-03-05 12:43:22 -08:00