Commit Graph

514 Commits

Author SHA1 Message Date
mssonicbld
5e4cda9c1c
Fix openconfig_acl.py (#16303) (#16422) 2023-09-03 21:22:49 +08:00
Zhijian Li
2941df3289 [minigraph-parser] Update the definition of acl table type BMCDATA and BMCDATAV6 (#16249)
Why I did it
According to ACL-Table-Type-HLD, the value type of MATCHES, ACTIONS and BIND_POINTS should be list instead of string. Opening this PR to update the definition of BMCDATA and BMCDATAV6.

How I did it
Update the definition of BMCDATA and BMCDATAV6 in minigraph-parser.

How to verify it
Verified by UT and build SONiC image.
2023-09-03 20:44:05 +08:00
kenneth-arista
9a5c188b3c Add YANG model for FABRIC_PORT (#15629)
#### Why I did it

Introduce YANG model for FABRIC in CONFIG_DB, which was added in https://github.com/sonic-net/sonic-buildimage/pull/14170.

#### How I did it

This is a clone of @jfeng-arista's PR https://github.com/sonic-net/sonic-buildimage/pull/14282 to resolve conflicts with upstream changes. 

#### How to verify it

Passing pipeline build is sufficient.
2023-09-03 18:32:51 +08:00
vmittal-msft
5ee18ece65 Update WRED profile on system ports (#15612)
* Update WRED profile on system ports
2023-08-07 14:33:42 +08:00
mssonicbld
471a3a8067
Add support data for fabric monitoring in CONFIG_DB. (#14170) (#16045)
Added support data for fabric monitoring in CONFIG_DB

The CONFIG_DB now has the FABRIC_MONITOR|FABRIC_MONITOR_DATA table for default value for fabric port monitoring. An example output of getting this table is:

sonic-db-cli CONFIG_DB hgetall "FABRIC_MONITOR|FABRIC_MONITOR_DATA"
{'monErrThreshCrcCells': '1', 'monErrThreshRxCells': '61035156', 'monPollThreshIsolation': '1', 'monPollThreshRecovery': '8'}

The CONFIG_DB now also has a table for each fabric port for its isolate status.
An example output of getting this table is:

sonic-db-cli CONFIG_DB hgetall "FABRIC_PORT|Fabric20"
{'alias': 'Fabric20', 'isolateStatus': 'False', 'lanes': '20'}

Co-authored-by: jfeng-arista <98421150+jfeng-arista@users.noreply.github.com>
2023-08-07 09:26:45 +08:00
mssonicbld
b812e562c8
[minigraph] remove number of lanes check for changing speed from 400G to 100G and set speed setting before lane reconfiguration (#15721) (#16054) 2023-08-07 03:24:30 +08:00
Zhijian Li
90dc056824 Update the defination of acl table type BMCDATA and BMCDATAV6 (#15385)
Why I did it
Update the definition of acl table type BMCDATA and BMCDATAV6 in minigraph parser.

Work item tracking
Microsoft ADO (number only): 24101023
How I did it
Update the definition of acl table type BMCDATA and BMCDATAV6 in minigraph parser.

How to verify it
Ran unittest to verify this update:
2023-06-26 16:41:02 +08:00
mssonicbld
260173782a
Fix a check for yang validation (#15498) (#15600) 2023-06-26 16:15:11 +08:00
Prince Sunny
f75116ab7a
Create default Vxlan and Vnet configs (#13409)
* Create default Vxlan and Vnet configs for ToRs with Appliance Resource type
2023-06-14 16:07:46 -07:00
Saikrishna Arcot
f84dfd2345
Re-add 127.0.0.1/8 when bringing down the interfaces (#15080)
* Re-add 127.0.0.1/8 when bringing down the interfaces

With #5353, 127.0.0.1/16 was added to the lo interface, and then
127.0.0.1/8 was removed. However, when bringing down the lo interface,
like during a config reload, 127.0.0.1/16 gets removed, but 127.0.0.1/8
isn't added back to the interface. This means that there's a period of
time where 127.0.0.1 is not available at all, and services that need to
connect to 127.0.01 (such as for redis DB) will fail.

To fix this, when going down, add 127.0.0.1/8. Add this address before
the existing configuration gets removed, so that 127.0.0.1 is available
at all times.

Note that running `ifdown lo` doesn't actually bring down the loopback
interface; the interface always stays "physically" up.

Signed-off-by: Saikrishna Arcot <sarcot@microsoft.com>
2023-06-13 18:45:39 -07:00
Neetha John
6a8f1bad63
[brcm] Update SOC properties for DLR_INIT based pfcwd recovery (#15286)
* [202205] Update SOC properties for DLR_INIT based pfcwd recovery (#15217)

Why I did it
Update soc properties for certain roles that need to use pfcwd dlr init based recovery mechanism

How to verify it
Updated the templates on a 7050cx3 dual tor and 7260 T1 which satisfies these conditions and validated pfcwd recovery which uses DLR_INIT based mechanism. Also validated that this mechanism is not used on 7050cx3 single tor with the updated templates

Signed-off-by: Neetha John <nejo@microsoft.com>
2023-06-03 14:39:38 -07:00
abdosi
3a098cfdea
Update AclInterface and Management Interfaces parsing for multi-asic case (#14952)
* AclInterface and Management Interfaces are parsed on finding first valid node for it.
Above logic works for multi-asic scenarios where ACL Interface and Management Interfaces are present in DPG order {Host, Asicx, Asicy} but not when DPG is in {Asicx, Asicy, Host} order.
2023-06-02 16:04:14 -07:00
Guilt
a73d443c1d
[CI][doc][build] Trim src folder files trailing blanks (#15162)
- Run pre-commit tox profile to trim all trailing blanks
- Use several commits with a per-folder based strategy
  to ease their merge

Issue #15114

Signed-off-by: Guillaume Lambert <guillaume.lambert@orange.com>
2023-05-24 10:01:43 -07:00
Yaqiang Zhu
c69d71af1c
[minigraph] Add rack_mgmt_rack parse support in minigraph.py (#15064)
Why I did it
We need to store information of power shelf in config_db for SONiC MX switch. Current minigraph parser cannot parse rack_mgmt_map field.

Work item tracking
Microsoft ADO (number only): 22179645
How I did it
Add support for parsing rack_mgmt_map.
2023-05-20 09:25:21 -07:00
abdosi
b5b5883c27
[minigraph.py]: Updated Static Route Minigraph Attribute property (#14951)
What I did:
Updated Static Route Attribute in Minigraph. NGS Minigraph has define semantics of static route differently.
See below for differences:-

Microsoft ADO: 17956325

Before

<AssociatedTo>8.0.0.1/32</AssociatedTo>
<Address>192.168.1.2,192.168.2.2</Address>
<AttachTo>PortChannel40,PortChannel50</AttachTo>

Now:

<Address>8.0.0.1</Address>
<AttachTo>PortChannel40,192.168.1.2;PortChannel50,192.168.2.2</AttachTo>

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2023-05-19 11:49:10 -07:00
vmittal-msft
ecb4db58a9
Update PG headroom settings ports based on port speed/cable length (#14908)
* Update PG headroom settings ports based on port speed/cable length

* Updated XOFF settings to use chip level numbers than core

* Updated PG headroom based on uplink/downlink side

* fix for sonic-config-gen tests

* More fixes for unit test cases

* more test fixes

* Merged multiple functions into one
2023-05-19 08:19:27 -07:00
abdosi
b7d04b6bd5
[minigraph]: Enhancement to minigraph parsing for chassis/multi-asic use case (#14243)
Following changes are done:    

Added Support where if asic configuration is not present in minigraph sonic-cfggen do not error out but instead process it gracefully. 

Use Case: In Supervisor we have number of asic are define as max possible but in minigraph configuration of only valid/available asics only are present. Without this change load_minigraph fails.

Microsoft ADO: 17956325

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2023-05-18 10:57:16 -07:00
jfeng-arista
771a0d0fbc
YANG model for FABRIC_MONITOR|FABRIC_MONITOR_DATA (#14390)
#### Why I did it
Table FABRIC_MONITOR|FABRIC_MONITOR_DATA in CONFIG_DB was added in https://github.com/sonic-net/sonic-buildimage/pull/14170 
The YANG model for that table is still missing. 

Need to wait https://github.com/sonic-net/sonic-buildimage/pull/14170 get merged first.

#### How I did it
Added new YANG model FABRIC_MONITOR and associated unit tests.

#### How to verify it
Passing unit tests
2023-05-15 13:20:23 -07:00
Tejaswini Chadaga
4e60f0d563
Template change for BGP monitors on T2 (#14844)
Why I did it
To support BGPMon sessions from each T2 linecard ASIC

Work item tracking
Microsoft ADO (number only): 17873174
How I did it
Added change in BGPMon configuration to use Loopback4096 as source interface, since this has a unique IP per ASIC.

How to verify it
Tested by manually setting up BGPMon session on T2 LC and verified that Loopback4096 could be used as source
2023-05-09 13:40:00 -07:00
anamehra
ab7bcb43b7
[minigraph.py]: Enable 400G to 100G/40G speed change via minigraph for all platforms (#14736)
There are chassis-packet and Single asic platforms which support this 400G to 100G/40G speed change via config.
Enabling this feature for all platforms which can support this. Keeping it enabled for all does not affect the platforms
which do not support this feature yet.

Signed-off-by: anamehra anamehra@cisco.com
2023-05-05 13:52:40 -07:00
vmittal-msft
5fc85f3274
Updated default ECN settings for T2 chassis (#14388)
Why I did it
Update ECN settings for T2 chassis

How I did it
Updated qos config file to load these settings during switch bootup

How to verify it
Verified on line card on T2 chassis
2023-05-04 10:01:09 -07:00
Zhijian Li
77728f5e36
[minigraph-parser] Support ACL interface type BmcData in minigraph parser (#14703)
* Support ACL interface type BmcData in minigraph parser

* Support ACL interface type BmcData in minigraph parser

* add unittest

* Add a global dict for storing the defination of custom acl tables
2023-04-26 16:07:38 -07:00
ganglv
8caa32bc55
[sonic-cfggen] Track missing yang models (#10963)
#### Why I did it
sonic-config-engine unit test needs to detect missing yang models.

#### How I did it
Update unit test, return error for missing yang models.

#### How to verify it
Run unit test for sonic-config-engine
2023-04-20 22:12:11 -07:00
Stepan Blyshchak
04099f075d
[BGP] support BGP pending FIB suppression (#12853)
Signed-off-by: Stepan Blyschak stepanb@nvidia.com

DEPENDS: #12852

Why I did it
To support BGP pending FIB suppression.

How I did it
I backported patches from FRR 8.4 feature that allows communicating ASIC route status back to FRR.
Also, added a new field in DEVICE_METADATA YANG model table. Added UT for YANG model changes.

How to verify it
Run on the switch.
2023-04-20 19:56:13 +08:00
vdahiya12
9e2d457a42
[minigraph] add support for changing T1 ports speed from 400G to 100G and vice-versa (#14505)
Open
[minigraph] add support for changing T1 ports speed from 400G to 100G and vice-versa
#14505
vdahiya12 wants to merge 9 commits into sonic-net:master from vdahiya12:dev/vdahiya/minigraph_parser
Conversation 10
Commits 9
Checks 18
Files changed 5
Conversation
vdahiya12
@vdahiya12 vdahiya12 commented 2 weeks ago • 
On SONiC T1 cisco 8101 HwSku, the speed changes are done from 400G to 100G needs to be supported on 400G ports.
To enable this, along with speed change the port lanes need to be changed. This PR has the changes to update the port lanes when such speed change happens.
Basically if Banwidth in minigraph.xml intends to enable a 100G speed on a 400G port, then the appropriate lane change and speed change needs to be invoked in mingraph parser
Example if port_config.ini dicatates the speed to be 400G and minigraph has 100G speed, then this changeneeds to be accommodated

# name         lanes                                      alias   index  speed    channel
Ethernet96     1536,1537,1538,1539,1540,1541,1542,1543    etp12    12       400000     0
 <DeviceLinkBase>
        <ElementType>DeviceInterfaceLink</ElementType>
        <EndDevice>ARISTA01T2</EndDevice>
        <EndPort>Ethernet1</EndPort>
        <StartDevice>Device-8101-01</StartDevice>
        <StartPort>etp12</StartPort>
        <Bandwidth>100000</Bandwidth>
      </DeviceLinkBase>
These platforms today have 400g port with 8 serdes lines, and 100g will operate with 4 serdes lane. When the port speed changes from 400G to 100G the first 4 lanes will be used for 100G port.

Signed-off-by: vaibhav-dahiya <vdahiya@microsoft.com>
2023-04-19 01:23:19 -07:00
Neetha John
ab097788d5
[qos] Update RDMA-CENTRIC lossy profile to use static threshold for Th devices (#14372)
Why I did it
For better accounting purposes, updating the ingress lossy traffic profile to use static threshold. This change is only intended for Th devices using RDMA-CENTRIC profiles

How I did it
Update the buffer templates for Th devices in RDMA-CENTRIC folder to use the correct threshold

How to verify it
Verified the changes manually on a Th device.
Existing unit tests render Th template from the RDMA-CENTRIC folder. Updated the expected output to use the correct threshold
2023-03-23 09:31:06 -07:00
Dev Ojha
de17f72d9a
[Buffer] Added cable length config to buffer config template for EdgeZoneAggregator (#14280)
Why I did it
SONiC currently does not identify 'EdgeZoneAggregator' neighbor. As a result, the buffer profile attached to those interfaces uses the default cable length which could cause ingress packet drops due to insufficient headroom. Hence, there is a need to update the buffer templates to identify such neighbors and assign the same cable length as used by the T1.

How I did it
Modified the buffer template to identify EdgeZoneAggregator as a neighbor device type and assign it the same cable length as a T1/leaf router.

How to verify it
Unit tests pass, and manually checked on a 7260 to see the changes take effect.

Signed-off-by: dojha <devojha@microsoft.com>
2023-03-17 11:01:17 -07:00
Marty Y. Lok
836d65d616
[EVERFLOW][ACL_ATBLE] Fix for everflow ACL_TABLE in config_db not having the routed ports when no -ASIC in the asic_port_name (#13532)
Why I did it
After the renaming of the asic_port_name in port_config.ini file (PR: #13053 ), the asic_ifname in port_config.ini is changed from '-ASIC<asic_id>' to just port. Example: 'Eth0-ASIC0' to 'Eth0'.

However, with this change a config_db generated via config load_minigraph would cause the EVERFLOW and EVERFLOWV6 tables under ACL_TABLE to not have any of non-LAG front panel interfaces. This was causing the EVERFLOW suite to fail.

How I did it
In parse_asic_external_neigbhors in minigraph.py there was a check that the asic_name.lower() (like asic0) is present in the port_alias_asic_map. However with -ASIC removed from the asic_ifname, the port_alias_asic_map would not have the asic_name and thus any non-LAG neighbor would not be included.

Fix was the ignore the asic name change as the port_alias_asic_map is already only looking for ports in just the same asic as asic_name.

How to verify it
Execute "config load_minigraph" with the mingraph which is generated by sonic-mgmt gen-minigraph script. And confirm ono-lag interface are present in the Everfloe table in the config_dbs.

Signed-off-by: mlok <marty.lok@nokia.com>
2023-03-13 10:58:32 -07:00
Liu Shilong
dcce42c402
Check SONiC dependencies before installation. (#13850)
Why I did it
SONiC related packages shouldn't be intalled from Pypi.
It is security compliance requirement.

How I did it
Check SONiC related packages when using setup.py.

How to verify it
2023-03-02 08:20:39 +08:00
Arvindsrinivasan Lakshmi Narasimhan
da1526ce01
[chassis][voq] 400g to100g speed changes for chassis linecards (#13935)
On SONiC VoQ chassis, the speed changes are done from 400G to 100G needs to be supported on 400G linecards.
To enable this, along with speed change the port lanes need to be changed. This PR has the changes to update the port lanes when such speed change happens.

This PR is intended only for VoQ chassis linecards. These platforms today have 400g port with 8 serdes lines, and 100g will operate with 4 serdes lane. When the port speed changes from 400G to 100G the first 4 lanes will be used for 100G port.

Platforms which support 2x50g PAM4 or support 100G PAM4 serdes or other combinations are not handled in the PR.

Signed-off-by: Arvindsrinivasan Lakshmi Narasimhan <arlakshm@microsoft.com>
2023-02-23 21:41:58 -08:00
Saikrishna Arcot
3e316cbf24
Don't create the members@ array in config_db for PC when reading from minigraph (#13660)
Fixes #11873.

#### Why I did it

When loading from minigraph, for port channels, don't create the members@ array in config_db in the PORTCHANNEL table. This is no longer needed or used.

In addition, when adding a port channel member from the CLI, that member doesn't get added into the members@ array, resulting in a bit of inconsistency. This gets rid of that inconsistency.
2023-02-23 14:49:51 -08:00
judyjoseph
bc2cb46ec5
Voq Chassis: Add the Recirc ports to the INTERFACES table to make it routed intf (#13779)
* VOQ: Add the Recirc ports to the INTERFACES table to make it routed intf

* Add a test to cover Recir port generation in INTERFACE table
2023-02-21 11:35:38 -08:00
zhixzhu
f0f7639fa2
set cable length to 1m for backplane ports (#13572)
Signed-off-by: Zhixin Zhu zhixzhu@cisco.com

Why I did it
backplane ports cable length need to be specified.

How I did it
separated handling for the specific port name.
2023-02-10 19:01:49 -08:00
Stephen Sun
e3ff08833e
[Mellanox] Support DSCP remapping in dual ToR topo on T0 switch (#12605)
- Why I did it
Support DSCP remapping in dual ToR topo on T0 switch for SKU Mellanox-SN4600c-C64, Mellanox-SN4600c-D48C40, Mellanox-SN2700, Mellanox-SN2700-D48C8.

- How I did it
Regarding buffer settings, originally, there are two lossless PGs and queues 3, 4. In dual ToR scenario, the lossless traffic from the leaf switch to the uplink of the ToR switch can be bounced back.
To avoid PFC deadlock, we need to map the bounce-back lossless traffic to different PGs and queues. Therefore, 2 additional lossless PGs and queues are allocated on uplink ports on ToR switches.

On uplink ports, map DSCP 2/6 to TC 2/6 respectively
On downlink ports, both DSCP 2/6 are still mapped to TC 1
Buffer adjusted according to the ports information:
Mellanox-SN4600c-C64:
56 downlinks 50G + 8 uplinks 100G
Mellanox-SN4600c-D48C40, Mellanox-SN2700, Mellanox-SN2700-D48C8:
24 downlinks 50G + 8 uplinks 100G

- How to verify it
Unit test.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2023-02-07 16:21:59 +02:00
Stepan Blyshchak
68e1079202
[FRR] Switch to dplane_fpm_nl plugin instead of fpm (#12852)
Why I did it
dplane_fpm_nl is a new FPM implementation in FRR. The old plugin fpm will not have any new features implemented. Usage of the new plugin gives us ability to use BGP suppression feature and next hop groups in the future.

How I did it
Switch to dplane_fpm_nl zebra plugin from old fpm plugin which is not supported anymore
Remove stale patches for old fpm plugin and add similar patches for dplane_fpm_nl

How to verify it
Build and run on the switch.

Signed-off-by: Stepan Blyschak <stepanb@nvidia.com>
2023-02-06 09:38:39 -08:00
kenneth-arista
9d19ac92a3
[yang-models] Add YANG model for SYSTEM_PORT (#12689)
Add YANG model for SYSTEM_PORT.
Resolves https://github.com/sonic-net/sonic-buildimage/issues/12458

#### Why I did it
YANG model for SYSTEM_PORT in CONFIG_DB was missing. 

#### How I did it
Added new YANG model and associated unit tests.

#### How to verify it
Passing unit tests
2023-02-02 10:19:30 -08:00
bingwang-ms
b03a65f331
Support both port name and alias in ACL table AttachTo attribute (#13444)
Why I did it
This PR is an enhancement of PR #13105
Because the input string of AttachTo for ACL table can appear in both port name group and port alias group, I added a logic to determine whether the string should be port name or port alias

If all the input strings belong to port name group, then we treat all of them as port name
If all the input strings belong to port alias, then we treat all of them as port alias
If all the input string belongs to both port alias group and port name group, we prefer port alias. The behavior is as before.
How I did it
Walk through all port names/alias in the input to make a decision.

How to verify it
Verified by adding UT.
2023-01-20 10:11:39 -08:00
bingwang-ms
22fcc760c4
[minigraph]: Support port name in ACL table AttachTo attribute (#13105)
Why I did it
This PR is to update minigraph.py to support both port alias and port name as input of AttachTo attribute of ACL table.
Before this change, only port alias is supported.

How I did it
Add a global variable to store port names
Search both port names and port alias wheh parsing the value of AttachTo.

How to verify it
Verified by a new unit test case test_minigraph_acl_attach_to_ports
Verified by copying the new minigraph.py to a testbed and run conflg load_minigraph.
2023-01-12 23:54:25 -08:00
Arvindsrinivasan Lakshmi Narasimhan
a57fa16839
[Chassis][Voq]update to add buffer_queue config on system ports (#12156)
Why I did it
In the voq chassis the buffer_queue configuration needs to be applied on system_port instead of the sonic port.
This PR has the change to do this.

How I did it
Modify buffer_config.j2 to generate buffer_queue configuration on system_ports if the device is Voq Chassis

How to verify it
Verify the buffer_queue configuration is generated properly using sonic-cfggen

Signed-off-by: Arvindsrinivasan Lakshmi Narasimhan <arlakshm@microsoft.com>
2022-12-31 23:59:54 -08:00
Longxiang Lyu
d2ab55cc15
[dualtor] Let T0 delay 10 seconds before sending BGP updates (#12996)
Why I did it
To ensure, that after a BGP startup, dualtor T0 receives BGP updates before sending out BGP updates.
Please refer to sonic-net/SONiC#1161 for more details.

How I did it
add coalesce-time 10000 to the frr bgp startup config.

Signed-off-by: Longxiang Lyu <lolv@microsoft.com>
2022-12-15 22:14:46 +00:00
Neetha John
c323037815
Update ECN settings for storage backend (#12855)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
ECN parameters need to be updated for storage backend

How I did it
Included the check for storage backend devices to update qos configs

How to verify it
Verified that the new ecn settings are applied on storage backend device.
Verified that the old ecn settings are applied for storage frontend, non storage frontend/backend devices
2022-11-29 10:19:06 -08:00
bingwang-ms
f402e6b5c6
Apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP to uplink ports on dualtor (#12730)
Why I did it
The PR is to apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP to uplink ports on dualtor.
The traffic with DSCP 2 and DSCP 6 from T1 is treated as lossless traffic.

DSCP    TC    Queue
2      2     2
6      6     6
Traffic with DSCP 2 or DSCP 6 from downlink is still treated as lossy traffic as before.

How I did it
Define DSCP_TO_TC_MAP|AZURE_UPLINK and TC_TO_QUEUE_MAP|AZURE_UPLINK.

How to verify it
Verified by UT
Verified by coping the new template to a testbed, and rendering a config_db.json
2022-11-21 11:42:28 -08:00
Mai Bui
6f0b05978d
[sonic-config-engine] Replace os.system, replace yaml.load, remove subprocess with shell=True (#12607)
Signed-off-by: maipbui <maibui@microsoft.com>
#### Why I did it
Missing import statement in PR https://github.com/sonic-net/sonic-buildimage/pull/12533
#### How I did it
Revert [PR 12646](https://github.com/sonic-net/sonic-buildimage/pull/12616)
Add import statement
1. 31f7afa92e/src/sonic-config-engine/tests/test_j2files_t2_chassis_fe.py (L8)
2. 31f7afa92e/src/sonic-config-engine/tests/test_j2files.py (L8)
3. 31f7afa92e/src/sonic-config-engine/tests/test_multinpu_cfggen.py (L11)
#### How to verify it
Pass UT
2022-11-17 08:02:57 -05:00
abdosi
e1ba683635
Add lacp_key as auto in portchannel configuration when parsing minigraph (#12694)
Add lacp_key as auto in portchannel configuration when parsing minigraph
Needed as mention in issue: https://github.com/sonic-net/sonic-buildimage/issues/4009
2022-11-15 09:42:12 -08:00
EdenGri
b1102ad913
Remove LOGLEVEL DB since is no longer used (#12657)
This PR is part of the following HLD:
Persistent loglevel HLD: sonic-net/SONiC#1041

- Why I did it
After the Logger tables moved from the LOGLEVEL_DB to the CONFIG_DB and the jinja2_cache was deleted the LOGLEVEL_DB is not in use.

- How I did it
Removed the LOGLEVEL_DB from the SONiC code

- How to verify it
All tests were passed
2022-11-14 12:10:44 -08:00
StormLiangMS
661c467858
Revert "[sonic-config-engine] Replace os.system, replace yaml.load, remove subprocess with shell=True (#12533)" (#12616)
This reverts commit 934871cce1. 

Unblocking sync from github to internal
2022-11-07 09:32:42 +08:00
bingwang-ms
6169ae3ee3
Add lossy scheduler for queue 7 (#12596)
* Add lossy scheduler for queue 7
2022-11-04 08:12:00 +08:00
Mai Bui
934871cce1
[sonic-config-engine] Replace os.system, replace yaml.load, remove subprocess with shell=True (#12533)
Signed-off-by: maipbui <maibui@microsoft.com>
#### Why I did it
`subprocess` is used with `shell=True`, which is very dangerous for shell injection.
`os` - not secure against maliciously constructed input and dangerous if used to evaluate dynamic content
`yaml.load` can create arbitrary Python objects
#### How I did it
Replace `os` by `subprocess`, remove `shell=True`
Use `yaml.safe_load()`
#### How to verify it
Pass UT
2022-10-31 10:43:46 -04:00
isabelmsft
db7459787c
Add yang_config_validation to minigraph.py (#12504) 2022-10-27 20:57:06 -05:00
tjchadaga
0c68a43712
Add yang model definition for VOQ_INBAND_INTERFACE (#12306) 2022-10-13 10:18:53 -07:00