[201807][platform] Accton: As5712-54x. Fix sfputil and accton_util (#2002)
* [platform] accton as5712-54x, fixed 1. Check i2c buses, they may get fliped on every bootup. 2. QSFP's lp_mode and reset are out of port order. 3. Change QSFP is reset with 1 second period. Signed-off-by: roy_lee <roy_lee@accton.com> * [platform] accton as5712-54x. Fix util.py error about SFP/QSFP's tx_disable and present. Signed-off-by: roy_lee <roy_lee@accton.com>
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@ -2,9 +2,9 @@
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#
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# Platform-specific SFP transceiver interface for SONiC
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#
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try:
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import time
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import os
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from sonic_sfp.sfputilbase import SfpUtilBase
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except ImportError as e:
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raise ImportError("%s - required module not found" % str(e))
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@ -21,8 +21,14 @@ class SfpUtil(SfpUtilBase):
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BASE_VAL_PATH = "/sys/class/i2c-adapter/i2c-{0}/{1}-0050/"
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BASE_OOM_PATH = "/sys/bus/i2c/devices/{0}-0050/"
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BASE_CPLD2_PATH = "/sys/bus/i2c/devices/0-0061/"
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BASE_CPLD3_PATH = "/sys/bus/i2c/devices/0-0062/"
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BASE_CPLD2_PATH = "/sys/bus/i2c/devices/{0}-0061/"
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BASE_CPLD3_PATH = "/sys/bus/i2c/devices/{0}-0062/"
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I2C_BUS_ORDER = -1
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#The sidebands of QSFP is different.
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#present is in-order.
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#But lp_mode and reset are not.
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qsfp_sb_map = [1, 3, 5, 2, 4, 6]
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_port_to_is_present = {}
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_port_to_lp_mode = {}
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@ -137,18 +143,30 @@ class SfpUtil(SfpUtilBase):
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SfpUtilBase.__init__(self)
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#Two i2c buses might get flipped order, check them both.
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def update_i2c_order(self):
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if self.I2C_BUS_ORDER < 0:
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eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
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if os.path.exists(eeprom_path):
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self.I2C_BUS_ORDER = 0
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eeprom_path = "/sys/bus/i2c/devices/0-0057/eeprom"
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if os.path.exists(eeprom_path):
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self.I2C_BUS_ORDER = 1
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return self.I2C_BUS_ORDER
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def get_presence(self, port_num):
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# Check for invalid port_num
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if port_num < self.port_start or port_num > self.port_end:
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return False
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order = self.update_i2c_order()
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if port_num < 24:
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present_path = self.BASE_CPLD2_PATH + "module_present_" + str(self._port_to_i2c_mapping[port_num][0])
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present_path = self.BASE_CPLD2_PATH.format(order)
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else:
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present_path = self.BASE_CPLD3_PATH + "module_present_" + str(self._port_to_i2c_mapping[port_num][0])
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present_path = self.BASE_CPLD3_PATH.format(order)
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present_path = present_path + "module_present_" + str(self._port_to_i2c_mapping[port_num][0])
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self.__port_to_is_present = present_path
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try:
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val_file = open(self.__port_to_is_present)
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@ -165,11 +183,21 @@ class SfpUtil(SfpUtilBase):
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return False
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def qsfp_sb_remap(self, port_num):
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qsfp_start = self.qsfp_port_start
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qsfp_index = self._port_to_i2c_mapping[port_num][0] - qsfp_start
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qsfp_index = self.qsfp_sb_map[qsfp_index-1]
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return qsfp_start+qsfp_index
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def get_low_power_mode(self, port_num):
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if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
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return False
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lp_mode_path = self.BASE_CPLD3_PATH + "module_lp_mode_" + str(self._port_to_i2c_mapping[port_num][0])
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order = self.update_i2c_order()
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lp_mode_path = self.BASE_CPLD3_PATH.format(order)
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lp_mode_path = lp_mode_path + "module_lp_mode_"
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q = self.qsfp_sb_remap(port_num)
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lp_mode_path = lp_mode_path + str(q)
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try:
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val_file = open(lp_mode_path)
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@ -190,7 +218,11 @@ class SfpUtil(SfpUtilBase):
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if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
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return False
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lp_mode_path = self.BASE_CPLD3_PATH + "module_lp_mode_" + str(self._port_to_i2c_mapping[port_num][0])
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order = self.update_i2c_order()
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lp_mode_path = self.BASE_CPLD3_PATH.format(order)
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lp_mode_path = lp_mode_path + "module_lp_mode_"
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q = self.qsfp_sb_remap(port_num)
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lp_mode_path = lp_mode_path + str(q)
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try:
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reg_file = open(lp_mode_path, 'r+')
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@ -212,7 +244,11 @@ class SfpUtil(SfpUtilBase):
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if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
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return False
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mod_rst_path = lp_mode_path = self.BASE_CPLD3_PATH + "module_reset_" + str(self._port_to_i2c_mapping[port_num][0])
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order = self.update_i2c_order()
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lp_mode_path = self.BASE_CPLD3_PATH.format(order)
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mod_rst_path = lp_mode_path + "module_reset_"
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q = self.qsfp_sb_remap(port_num)
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mod_rst_path = mod_rst_path + str(q)
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try:
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reg_file = open(mod_rst_path, 'r+')
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@ -220,9 +256,13 @@ class SfpUtil(SfpUtilBase):
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print "Error: unable to open file: %s" % str(e)
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return False
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reg_value = '1'
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reg_file.write(reg_value)
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#toggle reset
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reg_file.seek(0)
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reg_file.write('0')
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time.sleep(1)
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reg_file.seek(0)
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reg_file.write('1')
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reg_file.close()
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return True
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return True
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return True
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@ -1 +1 @@
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Subproject commit 406c4e675ea73d52827b520958c9956551a94e8e
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Subproject commit 46908e3e9315ad7f0742ebfde3281236556f1526
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