From ee598deced21c6f8d0081c0b61e8fb94677e5bdc Mon Sep 17 00:00:00 2001 From: DavidZagury <32644413+DavidZagury@users.noreply.github.com> Date: Sun, 10 Dec 2023 16:18:11 +0200 Subject: [PATCH] [Mellanox][SKU] Adding Mellanox-SN4700-O8V48 SKU (#17425) - Why I did it To add new SKU Mellanox-SN4700-O8V48 with following requirements: - How I did it Create new SKU files based on the below definition: * Port Mapping: 1-12 2x200G, 13-20 1x400G, 21-32 2x200G T0 topology: 48x200G Downlinks 8x400G uplinks. Length of downlink: 5m Length of uplink: 40m * Auto-negotiation enable/disable: Yes * FEC mode: RS * Shared headroom: Enabled * Shared headroom pool factor: 2 * Warmboot enabled: yes - How to verify it SONiC build with new SKU finish init, all ports up, qos tests suite from sonic-mgmt --- .../Mellanox-SN4700-O8V48/buffers.json.j2 | 17 + .../buffers_defaults_objects.j2 | 1 + .../buffers_defaults_t0.j2 | 38 +++ .../buffers_defaults_t1.j2 | 38 +++ .../buffers_dynamic.json.j2 | 18 ++ .../Mellanox-SN4700-O8V48/hwsku.json | 172 ++++++++++ .../pg_profile_lookup.ini | 1 + .../Mellanox-SN4700-O8V48/port_config.ini | 74 +++++ .../Mellanox-SN4700-O8V48/qos.json.j2 | 1 + .../Mellanox-SN4700-O8V48/sai.profile | 5 + .../sai_4700_8x400g_48x200g.xml | 297 ++++++++++++++++++ 11 files changed, 662 insertions(+) create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers.json.j2 create mode 120000 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_objects.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t0.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t1.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_dynamic.json.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/hwsku.json create mode 120000 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/pg_profile_lookup.ini create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/port_config.ini create mode 120000 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/qos.json.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/sai.profile create mode 100644 device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/sai_4700_8x400g_48x200g.xml diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers.json.j2 b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers.json.j2 new file mode 100644 index 0000000000..07a5d9ef1c --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers.json.j2 @@ -0,0 +1,17 @@ +{# + Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{%- set default_topo = 't0' %} +{%- include 'buffers_config.j2' %} diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_objects.j2 b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_objects.j2 new file mode 120000 index 0000000000..c01aebb7ae --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_objects.j2 @@ -0,0 +1 @@ +../../x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_objects.j2 \ No newline at end of file diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t0.j2 new file mode 100644 index 0000000000..02de15759c --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t0.j2 @@ -0,0 +1,38 @@ +{# + Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{% set default_cable = '5m' %} +{% set ingress_lossless_pool_size = '49946624' %} +{% set ingress_lossless_pool_xoff = '4063232' %} +{% set egress_lossless_pool_size = '60817392' %} +{% set egress_lossy_pool_size = '49946624' %} + +{% import 'buffers_defaults_objects.j2' as defs with context %} + +{%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} +{{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} +{%- endmacro %} diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t1.j2 new file mode 100644 index 0000000000..2c183413df --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_defaults_t1.j2 @@ -0,0 +1,38 @@ +{# + Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{% set default_cable = '300m' %} +{% set ingress_lossless_pool_size = '47546368' %} +{% set ingress_lossless_pool_xoff = '6463488' %} +{% set egress_lossless_pool_size = '60817392' %} +{% set egress_lossy_pool_size = '47546368' %} + +{% import 'buffers_defaults_objects.j2' as defs with context %} + +{%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} +{{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} +{%- endmacro %} diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_dynamic.json.j2 b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_dynamic.json.j2 new file mode 100644 index 0000000000..eb46dffb8d --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/buffers_dynamic.json.j2 @@ -0,0 +1,18 @@ +{# + Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{%- set default_topo = 't0' %} +{%- set dynamic_mode = 'true' %} +{%- include 'buffers_config.j2' %} diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/hwsku.json b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/hwsku.json new file mode 100644 index 0000000000..62030cf191 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/hwsku.json @@ -0,0 +1,172 @@ +{ + "interfaces": { + "Ethernet0": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet4": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet8": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet12": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet16": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet20": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet24": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet28": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet32": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet36": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet40": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet44": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet48": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet52": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet56": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet60": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet64": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet68": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet72": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet76": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet80": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet84": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet88": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet92": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet96": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet104": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet112": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet120": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet128": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet136": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet144": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet152": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" + }, + "Ethernet160": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet164": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet168": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet172": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet176": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet180": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet184": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet188": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet192": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet196": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet200": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet204": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet208": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet212": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet216": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet220": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet224": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet228": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet232": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet236": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet240": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet244": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet248": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + }, + "Ethernet252": { + "default_brkout_mode": "2x200G[100G,50G,40G,25G,10G,1G]" + } + } +} diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/pg_profile_lookup.ini b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/pg_profile_lookup.ini new file mode 120000 index 0000000000..66cab04d2c --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/pg_profile_lookup.ini @@ -0,0 +1 @@ +../Mellanox-SN4700-C128/pg_profile_lookup.ini \ No newline at end of file diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/port_config.ini b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/port_config.ini new file mode 100644 index 0000000000..55ac271b98 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/port_config.ini @@ -0,0 +1,74 @@ +## +## Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. +## Apache-2.0 +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. +## + +# name lanes alias index speed +Ethernet0 0,1,2,3 etp1a 1 200000 +Ethernet4 4,5,6,7 etp1b 1 200000 +Ethernet8 8,9,10,11 etp2a 2 200000 +Ethernet12 12,13,14,15 etp2b 2 200000 +Ethernet16 16,17,18,19 etp3a 3 200000 +Ethernet20 20,21,22,23 etp3b 3 200000 +Ethernet24 24,25,26,27 etp4a 4 200000 +Ethernet28 28,29,30,31 etp4b 4 200000 +Ethernet32 32,33,34,35 etp5a 5 200000 +Ethernet36 36,37,38,39 etp5b 5 200000 +Ethernet40 40,41,42,43 etp6a 6 200000 +Ethernet44 44,45,46,47 etp6b 6 200000 +Ethernet48 48,49,50,51 etp7a 7 200000 +Ethernet52 52,53,54,55 etp7b 7 200000 +Ethernet56 56,57,58,59 etp8a 8 200000 +Ethernet60 60,61,62,63 etp8b 8 200000 +Ethernet64 64,65,66,67 etp9a 9 200000 +Ethernet68 68,69,70,71 etp9b 9 200000 +Ethernet72 72,73,74,75 etp10a 10 200000 +Ethernet76 76,77,78,79 etp10b 10 200000 +Ethernet80 80,81,82,83 etp11a 11 200000 +Ethernet84 84,85,86,87 etp11b 11 200000 +Ethernet88 88,89,90,91 etp12a 12 200000 +Ethernet92 92,93,94,95 etp12b 12 200000 +Ethernet96 96,97,98,99,100,101,102,103 etp13 13 400000 +Ethernet104 104,105,106,107,108,109,110,111 etp14 14 400000 +Ethernet112 112,113,114,115,116,117,118,119 etp15 15 400000 +Ethernet120 120,121,122,123,124,125,126,127 etp16 16 400000 +Ethernet128 128,129,130,131,132,133,134,135 etp17 17 400000 +Ethernet136 136,137,138,139,140,141,142,143 etp18 18 400000 +Ethernet144 144,145,146,147,148,149,150,151 etp19 19 400000 +Ethernet152 152,153,154,155,156,157,158,159 etp20 20 400000 +Ethernet160 160,161,162,163 etp21a 21 200000 +Ethernet164 164,165,166,167 etp21b 21 200000 +Ethernet168 168,169,170,171 etp22a 22 200000 +Ethernet172 172,173,174,175 etp22b 22 200000 +Ethernet176 176,177,178,179 etp23a 23 200000 +Ethernet180 180,181,182,183 etp23b 23 200000 +Ethernet184 184,185,186,187 etp24a 24 200000 +Ethernet188 188,189,190,191 etp24b 24 200000 +Ethernet192 192,193,194,195 etp25a 25 200000 +Ethernet196 196,197,198,199 etp25b 25 200000 +Ethernet200 200,201,202,203 etp26a 26 200000 +Ethernet204 204,205,206,207 etp26b 26 200000 +Ethernet208 208,209,210,211 etp27a 27 200000 +Ethernet212 212,213,214,215 etp27b 27 200000 +Ethernet216 216,217,218,219 etp28a 28 200000 +Ethernet220 220,221,222,223 etp28b 28 200000 +Ethernet224 224,225,226,227 etp29a 29 200000 +Ethernet228 228,229,230,231 etp29b 29 200000 +Ethernet232 232,233,234,235 etp30a 30 200000 +Ethernet236 236,237,238,239 etp30b 30 200000 +Ethernet240 240,241,242,243 etp31a 31 200000 +Ethernet244 244,245,246,247 etp31b 31 200000 +Ethernet248 248,249,250,251 etp32a 32 200000 +Ethernet252 252,253,254,255 etp32b 32 200000 diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/qos.json.j2 b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/qos.json.j2 new file mode 120000 index 0000000000..eccf286dc8 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/qos.json.j2 @@ -0,0 +1 @@ +../../x86_64-mlnx_msn2700-r0/ACS-MSN2700/qos.json.j2 \ No newline at end of file diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/sai.profile b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/sai.profile new file mode 100644 index 0000000000..e0109ecf26 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/sai.profile @@ -0,0 +1,5 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700_8x400g_48x200g.xml +SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps +SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/sonic/mft/fwtrace_cfg +SAI_DEFAULT_SWITCHING_MODE_STORE_FORWARD=1 diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/sai_4700_8x400g_48x200g.xml b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8V48/sai_4700_8x400g_48x200g.xml new file mode 100644 index 0000000000..bb1f8646b2 --- /dev/null +++ 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