[devices] Add DPB support for x86_64-dell_z9100_c2538-r0 (#16538)
Why I did it Added DPB support for x86_64-dell_z9100_c2538-r0 device How I did it Added new SKU folder Force10-Z9100 based on Force10-Z9100-C32 Added platform.json and hwsku.json Added generic th-z9100-flex-all.config.bcm How to verify it On x86_64-dell_z9100_c2538-r0 with changes from this PR change default SKU to Force10-Z9100 do factory reset reboot Signed-off-by: Myron Sosyak <myron.sosyak@plvision.eu> Co-authored-by: Andriy Kokhan <andriy.kokhan@gmail.com>
This commit is contained in:
parent
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commit
d35bf7ef57
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{%- set default_topo = 't1' %}
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{%- include 'buffers_config.j2' %}
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{%- set default_cable = '40m' %}
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{%- macro generate_port_lists(PORT_ALL) %}
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{# Generate list of ports #}
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{%- for port_idx in range(0,32) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx*4)) %}{%- endif %}
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{%- endfor %}
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{%- endmacro %}
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{%- macro generate_buffer_pool_and_profiles() %}
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"BUFFER_POOL": {
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"ingress_lossless_pool": {
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"size": "10875072",
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"type": "ingress",
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"mode": "dynamic",
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"xoff": "4194112"
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},
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"egress_lossy_pool": {
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"size": "9243812",
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"type": "egress",
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"mode": "dynamic"
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},
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"egress_lossless_pool": {
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"size": "15982720",
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"type": "egress",
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"mode": "static"
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}
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},
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"BUFFER_PROFILE": {
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"ingress_lossy_profile": {
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"pool":"ingress_lossless_pool",
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"size":"0",
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"dynamic_th":"3"
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},
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"egress_lossless_profile": {
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"pool":"egress_lossless_pool",
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"size":"1518",
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"static_th":"15982720"
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},
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"egress_lossy_profile": {
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"pool":"egress_lossy_pool",
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"size":"1518",
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"dynamic_th":"3"
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}
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},
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{%- endmacro %}
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device/dell/x86_64-dell_z9100_c2538-r0/Force10-Z9100/hwsku.json
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100
device/dell/x86_64-dell_z9100_c2538-r0/Force10-Z9100/hwsku.json
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{
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"interfaces": {
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"Ethernet0": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet4": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet8": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet12": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet16": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet20": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet24": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet28": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet32": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet36": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet40": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet44": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet48": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet52": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet56": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet60": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet64": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet68": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet72": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet76": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet80": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet84": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet88": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet92": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet96": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet100": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet104": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet108": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet112": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet116": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet120": {
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"default_brkout_mode": "1x100G[40G]"
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},
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"Ethernet124": {
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"default_brkout_mode": "1x100G[40G]"
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}
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}
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}
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# LED microprocessor initialization for Dell Z9100
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#
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#
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#Led0
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=3 REMAP_PORT_61=2 REMAP_PORT_62=1 REMAP_PORT_63=0
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=7 REMAP_PORT_57=6 REMAP_PORT_58=5 REMAP_PORT_59=4
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=11 REMAP_PORT_53=10 REMAP_PORT_54=9 REMAP_PORT_55=8
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=15 REMAP_PORT_49=14 REMAP_PORT_50=13 REMAP_PORT_51=12
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=19 REMAP_PORT_9=18 REMAP_PORT_10=17 REMAP_PORT_11=16
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=23 REMAP_PORT_13=22 REMAP_PORT_14=21 REMAP_PORT_15=20
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=27 REMAP_PORT_1=26 REMAP_PORT_2=25 REMAP_PORT_3=24
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=31 REMAP_PORT_5=30 REMAP_PORT_6=29 REMAP_PORT_7=28
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=35 REMAP_PORT_41=34 REMAP_PORT_42=33 REMAP_PORT_43=32
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=39 REMAP_PORT_45=38 REMAP_PORT_46=37 REMAP_PORT_47=36
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=43 REMAP_PORT_33=42 REMAP_PORT_34=41 REMAP_PORT_35=40
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=47 REMAP_PORT_37=46 REMAP_PORT_38=45 REMAP_PORT_39=44
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=51 REMAP_PORT_25=50 REMAP_PORT_26=49 REMAP_PORT_27=48
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=55 REMAP_PORT_29=54 REMAP_PORT_30=53 REMAP_PORT_31=52
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=59 REMAP_PORT_17=58 REMAP_PORT_18=57 REMAP_PORT_19=56
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modreg CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=63 REMAP_PORT_21=62 REMAP_PORT_22=61 REMAP_PORT_23=60
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#Led1
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=3 REMAP_PORT_17=2 REMAP_PORT_18=1 REMAP_PORT_19=0
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=7 REMAP_PORT_21=6 REMAP_PORT_22=5 REMAP_PORT_23=4
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=11 REMAP_PORT_25=10 REMAP_PORT_26=9 REMAP_PORT_27=8
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=15 REMAP_PORT_29=14 REMAP_PORT_30=13 REMAP_PORT_31=12
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=19 REMAP_PORT_33=18 REMAP_PORT_34=17 REMAP_PORT_35=16
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=23 REMAP_PORT_37=22 REMAP_PORT_38=21 REMAP_PORT_39=20
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=27 REMAP_PORT_41=26 REMAP_PORT_42=25 REMAP_PORT_43=24
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=31 REMAP_PORT_45=30 REMAP_PORT_46=29 REMAP_PORT_47=28
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=35 REMAP_PORT_5=34 REMAP_PORT_6=33 REMAP_PORT_7=32
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=39 REMAP_PORT_1=38 REMAP_PORT_2=37 REMAP_PORT_3=36
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=43 REMAP_PORT_13=42 REMAP_PORT_14=41 REMAP_PORT_15=40
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=47 REMAP_PORT_9=46 REMAP_PORT_10=45 REMAP_PORT_11=44
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=51 REMAP_PORT_49=50 REMAP_PORT_50=49 REMAP_PORT_51=48
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=55 REMAP_PORT_53=54 REMAP_PORT_54=53 REMAP_PORT_55=52
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=59 REMAP_PORT_57=58 REMAP_PORT_58=57 REMAP_PORT_59=56
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modreg CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=63 REMAP_PORT_61=62 REMAP_PORT_62=61 REMAP_PORT_63=60
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led 0 stop
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led 0 prog 02 A8 60 AA 02 00 60 A7 02 00 60 FE 02 00 60 AB 06 A7 D2 08 74 20 02 A9 60 AA 06 A7 E2 08 60 A7 06 FE 28 67 3D 86 FE 06 FE 86 AB 06 AB D2 04 71 10 86 A7 06 FE D2 40 71 0C 86 FF 3A 80 32 08 97 71 7C 77 4C 57 22 0E 87 22 0E 87 57 22 0F 87 22 0F 87 57 22 0F 87 22 0E 87 57 06 AA 61 A6 16 A7 49 27 16 A6 97 71 53 77 45 57 02 0A 50 95 75 74 85 75 5A 57 16 FF CA 05 74 4C 77 5A 06 FE 12 BC F8 32 00 32 01 B7 97 71 6A 77 5A
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led 0 auto on
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led 0 start
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led 1 stop
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led 1 prog 02 A8 60 AA 02 00 60 A7 02 00 60 FE 02 00 60 AB 06 A7 D2 08 74 20 02 A9 60 AA 06 A7 E2 08 60 A7 06 FE 28 67 3D 86 FE 06 FE 86 AB 06 AB D2 04 71 10 86 A7 06 FE D2 40 71 0C 86 FF 3A 80 32 08 97 71 7C 77 4C 57 22 0E 87 22 0E 87 57 22 0F 87 22 0F 87 57 22 0F 87 22 0E 87 57 06 AA 61 A6 16 A7 49 27 16 A6 97 71 53 77 45 57 02 0A 50 95 75 74 85 75 5A 57 16 FF CA 05 74 4C 77 5A 06 FE 12 BC F8 32 00 32 01 B7 97 71 6A 77 5A
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led 1 auto on
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led 1 start
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led 2 stop
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# PG lossless profiles.
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# speed cable size xon xoff threshold xon_offset
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10000 5m 1248 2288 35776 -3 2288
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25000 5m 1248 2288 53248 -3 2288
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40000 5m 1248 2288 66560 -3 2288
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50000 5m 1248 2288 90272 -3 2288
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100000 5m 1248 2288 165568 -3 2288
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10000 40m 1248 2288 37024 -3 2288
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25000 40m 1248 2288 53248 -3 2288
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40000 40m 1248 2288 71552 -3 2288
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50000 40m 1248 2288 96096 -3 2288
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100000 40m 1248 2288 177632 -3 2288
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10000 300m 1248 2288 46176 -3 2288
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25000 300m 1248 2288 79040 -3 2288
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40000 300m 1248 2288 108160 -3 2288
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50000 300m 1248 2288 141856 -3 2288
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100000 300m 1248 2288 268736 -3 2288
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{%- include 'qos_config.j2' %}
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/platform/th-z9100-flex-all.config.bcm
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SAI_NUM_ECMP_MEMBERS=64
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612
device/dell/x86_64-dell_z9100_c2538-r0/platform.json
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612
device/dell/x86_64-dell_z9100_c2538-r0/platform.json
Normal file
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{
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"interfaces": {
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"Ethernet0": {
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"index": "1,1,1,1",
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"lanes": "49,50,51,52",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet0"
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],
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"2x50G": [
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"Ethernet0",
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"Ethernet2"
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],
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"4x25G[10G]": [
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"Ethernet0",
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"Ethernet1",
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"Ethernet2",
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"Ethernet3"
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]
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}
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},
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"Ethernet4": {
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"index": "2,2,2,2",
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"lanes": "53,54,55,56",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet4"
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],
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"2x50G": [
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"Ethernet4",
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"Ethernet6"
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],
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"4x25G[10G]": [
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"Ethernet4",
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"Ethernet5",
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"Ethernet6",
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"Ethernet7"
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]
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}
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},
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"Ethernet8": {
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"index": "3,3,3,3",
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"lanes": "57,58,59,60",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet8"
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],
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"2x50G": [
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"Ethernet8",
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"Ethernet10"
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],
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"4x25G[10G]": [
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"Ethernet8",
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"Ethernet9",
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"Ethernet10",
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"Ethernet11"
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]
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}
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},
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"Ethernet12": {
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"index": "4,4,4,4",
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"lanes": "61,62,63,64",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet12"
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],
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"2x50G": [
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"Ethernet12",
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"Ethernet14"
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],
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"4x25G[10G]": [
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"Ethernet12",
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"Ethernet13",
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"Ethernet14",
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"Ethernet15"
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]
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}
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},
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"Ethernet16": {
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"index": "5,5,5,5",
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"lanes": "65,66,67,68",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet16"
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],
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"2x50G": [
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"Ethernet16",
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"Ethernet18"
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],
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"4x25G[10G]": [
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"Ethernet16",
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"Ethernet17",
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"Ethernet18",
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"Ethernet19"
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]
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}
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},
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"Ethernet20": {
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"index": "6,6,6,6",
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"lanes": "69,70,71,72",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet20"
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],
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"2x50G": [
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"Ethernet20",
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"Ethernet22"
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],
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"4x25G[10G]": [
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"Ethernet20",
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"Ethernet21",
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"Ethernet22",
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"Ethernet23"
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]
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}
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},
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"Ethernet24": {
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"index": "7,7,7,7",
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"lanes": "73,74,75,76",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet24"
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],
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"2x50G": [
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"Ethernet24",
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"Ethernet26"
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],
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"4x25G[10G]": [
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"Ethernet24",
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"Ethernet25",
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"Ethernet26",
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"Ethernet27"
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]
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}
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},
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"Ethernet28": {
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"index": "8,8,8,8",
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"lanes": "77,78,79,80",
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"breakout_modes": {
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"1x100G[40G]": [
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"Ethernet28"
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],
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"2x50G": [
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"Ethernet28",
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||||
"Ethernet30"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet28",
|
||||
"Ethernet29",
|
||||
"Ethernet30",
|
||||
"Ethernet31"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet32": {
|
||||
"index": "9,9,9,9",
|
||||
"lanes": "37,38,39,40",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet32"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet32",
|
||||
"Ethernet34"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet32",
|
||||
"Ethernet33",
|
||||
"Ethernet34",
|
||||
"Ethernet35"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet36": {
|
||||
"index": "10,10,10,10",
|
||||
"lanes": "33,34,35,36",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet36"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet36",
|
||||
"Ethernet38"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet36",
|
||||
"Ethernet37",
|
||||
"Ethernet38",
|
||||
"Ethernet39"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet40": {
|
||||
"index": "11,11,11,11",
|
||||
"lanes": "45,46,47,48",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet40"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet40",
|
||||
"Ethernet42"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet40",
|
||||
"Ethernet41",
|
||||
"Ethernet42",
|
||||
"Ethernet43"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet44": {
|
||||
"index": "12,12,12,12",
|
||||
"lanes": "41,42,43,44",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet44"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet44",
|
||||
"Ethernet46"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet44",
|
||||
"Ethernet45",
|
||||
"Ethernet46",
|
||||
"Ethernet47"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet48": {
|
||||
"index": "13,13,13,13",
|
||||
"lanes": "81,82,83,84",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet48"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet48",
|
||||
"Ethernet50"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet48",
|
||||
"Ethernet49",
|
||||
"Ethernet50",
|
||||
"Ethernet51"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet52": {
|
||||
"index": "14,14,14,14",
|
||||
"lanes": "85,86,87,88",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet52"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet52",
|
||||
"Ethernet54"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet52",
|
||||
"Ethernet53",
|
||||
"Ethernet54",
|
||||
"Ethernet55"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet56": {
|
||||
"index": "15,15,15,15",
|
||||
"lanes": "89,90,91,92",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet56"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet56",
|
||||
"Ethernet58"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet56",
|
||||
"Ethernet57",
|
||||
"Ethernet58",
|
||||
"Ethernet59"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet60": {
|
||||
"index": "16,16,16,16",
|
||||
"lanes": "93,94,95,96",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet60"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet60",
|
||||
"Ethernet62"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet60",
|
||||
"Ethernet61",
|
||||
"Ethernet62",
|
||||
"Ethernet63"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet64": {
|
||||
"index": "17,17,17,17",
|
||||
"lanes": "97,98,99,100",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet64"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet64",
|
||||
"Ethernet66"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet64",
|
||||
"Ethernet65",
|
||||
"Ethernet66",
|
||||
"Ethernet67"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet68": {
|
||||
"index": "18,18,18,18",
|
||||
"lanes": "101,102,103,104",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet68"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet68",
|
||||
"Ethernet70"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet68",
|
||||
"Ethernet69",
|
||||
"Ethernet70",
|
||||
"Ethernet71"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet72": {
|
||||
"index": "19,19,19,19",
|
||||
"lanes": "105,106,107,108",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet72"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet72",
|
||||
"Ethernet74"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet72",
|
||||
"Ethernet73",
|
||||
"Ethernet74",
|
||||
"Ethernet75"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet76": {
|
||||
"index": "20,20,20,20",
|
||||
"lanes": "109,110,111,112",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet76"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet76",
|
||||
"Ethernet78"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet76",
|
||||
"Ethernet77",
|
||||
"Ethernet78",
|
||||
"Ethernet79"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet80": {
|
||||
"index": "21,21,21,21",
|
||||
"lanes": "21,22,23,24",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet80"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet80",
|
||||
"Ethernet82"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet80",
|
||||
"Ethernet81",
|
||||
"Ethernet82",
|
||||
"Ethernet83"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet84": {
|
||||
"index": "22,22,22,22",
|
||||
"lanes": "17,18,19,20",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet84"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet84",
|
||||
"Ethernet86"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet84",
|
||||
"Ethernet85",
|
||||
"Ethernet86",
|
||||
"Ethernet87"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet88": {
|
||||
"index": "23,23,23,23",
|
||||
"lanes": "29,30,31,32",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet88"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet88",
|
||||
"Ethernet90"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet88",
|
||||
"Ethernet89",
|
||||
"Ethernet90",
|
||||
"Ethernet91"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet92": {
|
||||
"index": "24,24,24,24",
|
||||
"lanes": "25,26,27,28",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet92"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet92",
|
||||
"Ethernet94"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet92",
|
||||
"Ethernet93",
|
||||
"Ethernet94",
|
||||
"Ethernet95"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet96": {
|
||||
"index": "25,25,25,25",
|
||||
"lanes": "117,118,119,120",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet96"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet96",
|
||||
"Ethernet98"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet96",
|
||||
"Ethernet97",
|
||||
"Ethernet98",
|
||||
"Ethernet99"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet100": {
|
||||
"index": "26,26,26,26",
|
||||
"lanes": "113,114,115,116",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet100"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet100",
|
||||
"Ethernet102"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet100",
|
||||
"Ethernet101",
|
||||
"Ethernet102",
|
||||
"Ethernet103"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet104": {
|
||||
"index": "27,27,27,27",
|
||||
"lanes": "125,126,127,128",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet104"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet104",
|
||||
"Ethernet106"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet104",
|
||||
"Ethernet105",
|
||||
"Ethernet106",
|
||||
"Ethernet107"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet108": {
|
||||
"index": "28,28,28,28",
|
||||
"lanes": "121,122,123,124",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet108"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet108",
|
||||
"Ethernet110"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet108",
|
||||
"Ethernet109",
|
||||
"Ethernet110",
|
||||
"Ethernet111"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet112": {
|
||||
"index": "29,29,29,29",
|
||||
"lanes": "5,6,7,8",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet112"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet112",
|
||||
"Ethernet114"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet112",
|
||||
"Ethernet113",
|
||||
"Ethernet114",
|
||||
"Ethernet115"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet116": {
|
||||
"index": "30,30,30,30",
|
||||
"lanes": "1,2,3,4",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet116"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet116",
|
||||
"Ethernet118"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet116",
|
||||
"Ethernet117",
|
||||
"Ethernet118",
|
||||
"Ethernet119"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet120": {
|
||||
"index": "31,31,31,31",
|
||||
"lanes": "13,14,15,16",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet120"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet120",
|
||||
"Ethernet122"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet120",
|
||||
"Ethernet121",
|
||||
"Ethernet122",
|
||||
"Ethernet123"
|
||||
]
|
||||
}
|
||||
},
|
||||
"Ethernet124": {
|
||||
"index": "32,32,32,32",
|
||||
"lanes": "9,10,11,12",
|
||||
"breakout_modes": {
|
||||
"1x100G[40G]": [
|
||||
"Ethernet124"
|
||||
],
|
||||
"2x50G": [
|
||||
"Ethernet124",
|
||||
"Ethernet126"
|
||||
],
|
||||
"4x25G[10G]": [
|
||||
"Ethernet124",
|
||||
"Ethernet125",
|
||||
"Ethernet126",
|
||||
"Ethernet127"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
@ -0,0 +1,670 @@
|
||||
#TH Z9100 T0
|
||||
|
||||
l3_alpm_enable=2
|
||||
pfc_deadlock_seq_control=1
|
||||
bcm_stat_interval=2000000
|
||||
bcm_num_cos=10
|
||||
switch_bypass_mode=0
|
||||
mmu_lossless=0
|
||||
lpm_scaling_enable=0
|
||||
lpm_scaling_enable=0
|
||||
lpm_ipv6_128b_reserved=0
|
||||
ipv6_lpm_128b_enable=1
|
||||
l2xmsg_mode=1
|
||||
oversubscribe_mode=1
|
||||
os=unix
|
||||
|
||||
pbmp_oversubscribe=0x3ffffffffffffffffffffffffffffffffe
|
||||
pbmp_xport_xe=0x3ffffffffffffffffffffffffffffffffe
|
||||
|
||||
serdes_if_type_xe=14
|
||||
serdes_if_type_ce=14
|
||||
|
||||
#Parity
|
||||
parity_correction=1
|
||||
parity_enable=1
|
||||
|
||||
|
||||
#FP1
|
||||
dport_map_port_51.0=1
|
||||
dport_map_port_50.0=2
|
||||
dport_map_port_52.0=3
|
||||
dport_map_port_53.0=4
|
||||
portmap_50.0=49:100
|
||||
portmap_51.0=50:25:i
|
||||
portmap_52.0=51:25:50:i
|
||||
portmap_53.0=52:25:i
|
||||
xgxs_rx_lane_map_50.0=0x1023
|
||||
xgxs_tx_lane_map_50.0=0x132
|
||||
phy_xaui_rx_polarity_flip_50.0=0xc
|
||||
phy_xaui_rx_polarity_flip_51.0=0x6
|
||||
phy_xaui_rx_polarity_flip_52.0=0x3
|
||||
phy_xaui_rx_polarity_flip_53.0=0x1
|
||||
phy_xaui_tx_polarity_flip_50.0=0xe
|
||||
phy_xaui_tx_polarity_flip_51.0=0x7
|
||||
phy_xaui_tx_polarity_flip_52.0=0x3
|
||||
phy_xaui_tx_polarity_flip_53.0=0x1
|
||||
|
||||
#FP2
|
||||
dport_map_port_55.0=5
|
||||
dport_map_port_57.0=6
|
||||
dport_map_port_54.0=7
|
||||
dport_map_port_56.0=8
|
||||
portmap_54.0=53:100
|
||||
portmap_55.0=54:25:i
|
||||
portmap_56.0=55:25:50:i
|
||||
portmap_57.0=56:25:i
|
||||
xgxs_rx_lane_map_54.0=0x1302
|
||||
xgxs_tx_lane_map_54.0=0x2301
|
||||
phy_xaui_rx_polarity_flip_54.0=0xd
|
||||
phy_xaui_rx_polarity_flip_55.0=0x6
|
||||
phy_xaui_rx_polarity_flip_56.0=0x3
|
||||
phy_xaui_rx_polarity_flip_57.0=0x1
|
||||
phy_xaui_tx_polarity_flip_54.0=0x2
|
||||
phy_xaui_tx_polarity_flip_55.0=0x1
|
||||
phy_xaui_tx_polarity_flip_56.0=0x0
|
||||
phy_xaui_tx_polarity_flip_57.0=0x0
|
||||
|
||||
#FP3
|
||||
dport_map_port_59.0=9
|
||||
dport_map_port_60.0=10
|
||||
dport_map_port_58.0=11
|
||||
dport_map_port_61.0=12
|
||||
portmap_58.0=57:100
|
||||
portmap_59.0=58:25:i
|
||||
portmap_60.0=59:25:50:i
|
||||
portmap_61.0=60:25:i
|
||||
xgxs_rx_lane_map_58.0=0x1203
|
||||
xgxs_tx_lane_map_58.0=0x123
|
||||
phy_xaui_rx_polarity_flip_58.0=0x2
|
||||
phy_xaui_rx_polarity_flip_59.0=0x1
|
||||
phy_xaui_rx_polarity_flip_60.0=0x0
|
||||
phy_xaui_rx_polarity_flip_61.0=0x0
|
||||
phy_xaui_tx_polarity_flip_58.0=0xa
|
||||
phy_xaui_tx_polarity_flip_59.0=0x5
|
||||
phy_xaui_tx_polarity_flip_60.0=0x2
|
||||
phy_xaui_tx_polarity_flip_61.0=0x1
|
||||
|
||||
#FP4
|
||||
dport_map_port_63.0=13
|
||||
dport_map_port_65.0=14
|
||||
dport_map_port_62.0=15
|
||||
dport_map_port_64.0=16
|
||||
portmap_62.0=61:100
|
||||
portmap_63.0=62:25:i
|
||||
portmap_64.0=63:25:50:i
|
||||
portmap_65.0=64:25:i
|
||||
xgxs_rx_lane_map_62.0=0x1302
|
||||
xgxs_tx_lane_map_62.0=0x3201
|
||||
phy_xaui_rx_polarity_flip_62.0=0xf
|
||||
phy_xaui_rx_polarity_flip_63.0=0x7
|
||||
phy_xaui_rx_polarity_flip_64.0=0x3
|
||||
phy_xaui_rx_polarity_flip_65.0=0x1
|
||||
phy_xaui_tx_polarity_flip_62.0=0xb
|
||||
phy_xaui_tx_polarity_flip_63.0=0x5
|
||||
phy_xaui_tx_polarity_flip_64.0=0x2
|
||||
phy_xaui_tx_polarity_flip_65.0=0x1
|
||||
|
||||
#FP5
|
||||
dport_map_port_71.0=17
|
||||
dport_map_port_70.0=18
|
||||
dport_map_port_68.0=19
|
||||
dport_map_port_69.0=20
|
||||
portmap_68.0=65:100
|
||||
portmap_69.0=66:25:i
|
||||
portmap_70.0=67:25:50:i
|
||||
portmap_71.0=68:25:i
|
||||
xgxs_rx_lane_map_68.0=0x3201
|
||||
xgxs_tx_lane_map_68.0=0x3210
|
||||
phy_xaui_rx_polarity_flip_68.0=0xc
|
||||
phy_xaui_rx_polarity_flip_69.0=0x6
|
||||
phy_xaui_rx_polarity_flip_70.0=0x3
|
||||
phy_xaui_rx_polarity_flip_71.0=0x1
|
||||
phy_xaui_tx_polarity_flip_68.0=0x2
|
||||
phy_xaui_tx_polarity_flip_69.0=0x1
|
||||
phy_xaui_tx_polarity_flip_70.0=0x0
|
||||
phy_xaui_tx_polarity_flip_71.0=0x0
|
||||
|
||||
#FP6
|
||||
dport_map_port_73.0=21
|
||||
dport_map_port_75.0=22
|
||||
dport_map_port_72.0=23
|
||||
dport_map_port_74.0=24
|
||||
portmap_72.0=69:100
|
||||
portmap_73.0=70:25:i
|
||||
portmap_74.0=71:25:50:i
|
||||
portmap_75.0=72:25:i
|
||||
xgxs_rx_lane_map_72.0=0x1302
|
||||
xgxs_tx_lane_map_72.0=0x2301
|
||||
phy_xaui_rx_polarity_flip_72.0=0x2
|
||||
phy_xaui_rx_polarity_flip_73.0=0x1
|
||||
phy_xaui_rx_polarity_flip_74.0=0x0
|
||||
phy_xaui_rx_polarity_flip_75.0=0x0
|
||||
phy_xaui_tx_polarity_flip_72.0=0x0
|
||||
phy_xaui_tx_polarity_flip_73.0=0x0
|
||||
phy_xaui_tx_polarity_flip_74.0=0x0
|
||||
phy_xaui_tx_polarity_flip_75.0=0x0
|
||||
|
||||
#FP7
|
||||
dport_map_port_77.0=25
|
||||
dport_map_port_78.0=26
|
||||
dport_map_port_76.0=27
|
||||
dport_map_port_79.0=28
|
||||
portmap_76.0=73:100
|
||||
portmap_77.0=74:25:i
|
||||
portmap_78.0=75:25:50:i
|
||||
portmap_79.0=76:25:i
|
||||
xgxs_rx_lane_map_76.0=0x1203
|
||||
xgxs_tx_lane_map_76.0=0x123
|
||||
phy_xaui_rx_polarity_flip_76.0=0x2
|
||||
phy_xaui_rx_polarity_flip_77.0=0x1
|
||||
phy_xaui_rx_polarity_flip_78.0=0x0
|
||||
phy_xaui_rx_polarity_flip_79.0=0x0
|
||||
phy_xaui_tx_polarity_flip_76.0=0x0
|
||||
phy_xaui_tx_polarity_flip_77.0=0x0
|
||||
phy_xaui_tx_polarity_flip_78.0=0x0
|
||||
phy_xaui_tx_polarity_flip_79.0=0x0
|
||||
|
||||
#FP8
|
||||
dport_map_port_82.0=29
|
||||
dport_map_port_83.0=30
|
||||
dport_map_port_80.0=31
|
||||
dport_map_port_81.0=32
|
||||
portmap_80.0=77:100
|
||||
portmap_81.0=78:25:i
|
||||
portmap_82.0=79:25:50:i
|
||||
portmap_83.0=80:25:i
|
||||
xgxs_rx_lane_map_80.0=0x2301
|
||||
xgxs_tx_lane_map_80.0=0x1320
|
||||
phy_xaui_rx_polarity_flip_80.0=0xd
|
||||
phy_xaui_rx_polarity_flip_81.0=0x6
|
||||
phy_xaui_rx_polarity_flip_82.0=0x3
|
||||
phy_xaui_rx_polarity_flip_83.0=0x1
|
||||
phy_xaui_tx_polarity_flip_80.0=0xa
|
||||
phy_xaui_tx_polarity_flip_81.0=0x5
|
||||
phy_xaui_tx_polarity_flip_82.0=0x2
|
||||
phy_xaui_tx_polarity_flip_83.0=0x1
|
||||
|
||||
#FP9
|
||||
dport_map_port_38.0=33
|
||||
dport_map_port_41.0=34
|
||||
dport_map_port_39.0=35
|
||||
dport_map_port_40.0=36
|
||||
portmap_38.0=37:100
|
||||
portmap_39.0=38:25:i
|
||||
portmap_40.0=39:25:50:i
|
||||
portmap_41.0=40:25:i
|
||||
xgxs_rx_lane_map_38.0=0x0312
|
||||
xgxs_tx_lane_map_38.0=0x1032
|
||||
phy_xaui_rx_polarity_flip_38.0=0xd
|
||||
phy_xaui_rx_polarity_flip_39.0=0x6
|
||||
phy_xaui_rx_polarity_flip_40.0=0x3
|
||||
phy_xaui_rx_polarity_flip_41.0=0x1
|
||||
phy_xaui_tx_polarity_flip_38.0=0x0
|
||||
phy_xaui_tx_polarity_flip_39.0=0x0
|
||||
phy_xaui_tx_polarity_flip_40.0=0x0
|
||||
phy_xaui_tx_polarity_flip_41.0=0x0
|
||||
|
||||
#FP10
|
||||
dport_map_port_35.0=37
|
||||
dport_map_port_37.0=38
|
||||
dport_map_port_34.0=39
|
||||
dport_map_port_36.0=40
|
||||
portmap_34.0=33:100
|
||||
portmap_35.0=34:25:i
|
||||
portmap_36.0=35:25:50:i
|
||||
portmap_37.0=36:25:i
|
||||
xgxs_rx_lane_map_34.0=0x1302
|
||||
xgxs_tx_lane_map_34.0=0x2031
|
||||
phy_xaui_rx_polarity_flip_34.0=0xa
|
||||
phy_xaui_rx_polarity_flip_35.0=0x5
|
||||
phy_xaui_rx_polarity_flip_36.0=0x2
|
||||
phy_xaui_rx_polarity_flip_37.0=0x1
|
||||
phy_xaui_tx_polarity_flip_34.0=0xb
|
||||
phy_xaui_tx_polarity_flip_35.0=0x5
|
||||
phy_xaui_tx_polarity_flip_36.0=0x2
|
||||
phy_xaui_tx_polarity_flip_37.0=0x1
|
||||
|
||||
#FP11
|
||||
dport_map_port_48.0=41
|
||||
dport_map_port_47.0=42
|
||||
dport_map_port_46.0=43
|
||||
dport_map_port_49.0=44
|
||||
portmap_46.0=45:100
|
||||
portmap_47.0=46:25:i
|
||||
portmap_48.0=47:25:50:i
|
||||
portmap_49.0=48:25:i
|
||||
xgxs_rx_lane_map_46.0=0x2103
|
||||
xgxs_tx_lane_map_46.0=0x1023
|
||||
phy_xaui_rx_polarity_flip_46.0=0x7
|
||||
phy_xaui_rx_polarity_flip_47.0=0x3
|
||||
phy_xaui_rx_polarity_flip_48.0=0x1
|
||||
phy_xaui_rx_polarity_flip_49.0=0x0
|
||||
phy_xaui_tx_polarity_flip_46.0=0xe
|
||||
phy_xaui_tx_polarity_flip_47.0=0x7
|
||||
phy_xaui_tx_polarity_flip_48.0=0x3
|
||||
phy_xaui_tx_polarity_flip_49.0=0x1
|
||||
|
||||
#FP12
|
||||
dport_map_port_45.0=45
|
||||
dport_map_port_44.0=46
|
||||
dport_map_port_43.0=47
|
||||
dport_map_port_42.0=48
|
||||
portmap_42.0=41:100
|
||||
portmap_43.0=42:25:i
|
||||
portmap_44.0=43:25:50:i
|
||||
portmap_45.0=44:25:i
|
||||
xgxs_rx_lane_map_42.0=0x3210
|
||||
xgxs_tx_lane_map_42.0=0x132
|
||||
phy_xaui_rx_polarity_flip_42.0=0xf
|
||||
phy_xaui_rx_polarity_flip_43.0=0x7
|
||||
phy_xaui_rx_polarity_flip_44.0=0x3
|
||||
phy_xaui_rx_polarity_flip_45.0=0x1
|
||||
phy_xaui_tx_polarity_flip_42.0=0x6
|
||||
phy_xaui_tx_polarity_flip_43.0=0x3
|
||||
phy_xaui_tx_polarity_flip_44.0=0x1
|
||||
phy_xaui_tx_polarity_flip_45.0=0x0
|
||||
|
||||
#FP13
|
||||
dport_map_port_86.0=49
|
||||
dport_map_port_87.0=50
|
||||
dport_map_port_84.0=51
|
||||
dport_map_port_85.0=52
|
||||
portmap_84.0=81:100
|
||||
portmap_85.0=82:25:i
|
||||
portmap_86.0=83:25:50:i
|
||||
portmap_87.0=84:25:i
|
||||
xgxs_rx_lane_map_84.0=0x2301
|
||||
xgxs_tx_lane_map_84.0=0x213
|
||||
phy_xaui_rx_polarity_flip_84.0=0xf
|
||||
phy_xaui_rx_polarity_flip_85.0=0x7
|
||||
phy_xaui_rx_polarity_flip_86.0=0x3
|
||||
phy_xaui_rx_polarity_flip_87.0=0x1
|
||||
phy_xaui_tx_polarity_flip_84.0=0x6
|
||||
phy_xaui_tx_polarity_flip_85.0=0x3
|
||||
phy_xaui_tx_polarity_flip_86.0=0x1
|
||||
phy_xaui_tx_polarity_flip_87.0=0x0
|
||||
|
||||
#FP14
|
||||
dport_map_port_88.0=53
|
||||
dport_map_port_90.0=54
|
||||
dport_map_port_89.0=55
|
||||
dport_map_port_91.0=56
|
||||
portmap_88.0=85:100
|
||||
portmap_89.0=86:25:i
|
||||
portmap_90.0=87:25:50:i
|
||||
portmap_91.0=88:25:i
|
||||
xgxs_rx_lane_map_88.0=0x0213
|
||||
xgxs_tx_lane_map_88.0=0x1032
|
||||
phy_xaui_rx_polarity_flip_88.0=0xd
|
||||
phy_xaui_rx_polarity_flip_89.0=0x6
|
||||
phy_xaui_rx_polarity_flip_90.0=0x3
|
||||
phy_xaui_rx_polarity_flip_91.0=0x1
|
||||
phy_xaui_tx_polarity_flip_88.0=0xf
|
||||
phy_xaui_tx_polarity_flip_89.0=0x7
|
||||
phy_xaui_tx_polarity_flip_90.0=0x3
|
||||
phy_xaui_tx_polarity_flip_91.0=0x1
|
||||
|
||||
#FP15
|
||||
dport_map_port_95.0=57
|
||||
dport_map_port_94.0=58
|
||||
dport_map_port_93.0=59
|
||||
dport_map_port_92.0=60
|
||||
portmap_92.0=89:100
|
||||
portmap_93.0=90:25:i
|
||||
portmap_94.0=91:25:50:i
|
||||
portmap_95.0=92:25:i
|
||||
xgxs_rx_lane_map_92.0=0x3210
|
||||
xgxs_tx_lane_map_92.0=0x132
|
||||
phy_xaui_rx_polarity_flip_92.0=0x4
|
||||
phy_xaui_rx_polarity_flip_93.0=0x2
|
||||
phy_xaui_rx_polarity_flip_94.0=0x1
|
||||
phy_xaui_rx_polarity_flip_95.0=0x0
|
||||
phy_xaui_tx_polarity_flip_92.0=0x5
|
||||
phy_xaui_tx_polarity_flip_93.0=0x2
|
||||
phy_xaui_tx_polarity_flip_94.0=0x1
|
||||
phy_xaui_tx_polarity_flip_95.0=0x0
|
||||
|
||||
#FP16
|
||||
dport_map_port_99.0=61
|
||||
dport_map_port_98.0=62
|
||||
dport_map_port_97.0=63
|
||||
dport_map_port_96.0=64
|
||||
portmap_96.0=93:100
|
||||
portmap_97.0=94:25:i
|
||||
portmap_98.0=95:25:50:i
|
||||
portmap_99.0=96:25:i
|
||||
xgxs_rx_lane_map_96.0=0x3210
|
||||
xgxs_tx_lane_map_96.0=0x123
|
||||
phy_xaui_rx_polarity_flip_96.0=0xb
|
||||
phy_xaui_rx_polarity_flip_97.0=0x5
|
||||
phy_xaui_rx_polarity_flip_98.0=0x2
|
||||
phy_xaui_rx_polarity_flip_99.0=0x1
|
||||
phy_xaui_tx_polarity_flip_96.0=0x8
|
||||
phy_xaui_tx_polarity_flip_97.0=0x4
|
||||
phy_xaui_tx_polarity_flip_98.0=0x2
|
||||
phy_xaui_tx_polarity_flip_99.0=0x1
|
||||
|
||||
#FP17
|
||||
dport_map_port_105.0=65
|
||||
dport_map_port_104.0=66
|
||||
dport_map_port_102.0=67
|
||||
dport_map_port_103.0=68
|
||||
portmap_102.0=97:100
|
||||
portmap_103.0=98:25:i
|
||||
portmap_104.0=99:25:50:i
|
||||
portmap_105.0=100:25:i
|
||||
xgxs_rx_lane_map_102.0=0x3201
|
||||
xgxs_tx_lane_map_102.0=0x123
|
||||
phy_xaui_rx_polarity_flip_102.0=0x2
|
||||
phy_xaui_rx_polarity_flip_103.0=0x1
|
||||
phy_xaui_rx_polarity_flip_104.0=0x0
|
||||
phy_xaui_rx_polarity_flip_105.0=0x0
|
||||
phy_xaui_tx_polarity_flip_102.0=0xf
|
||||
phy_xaui_tx_polarity_flip_103.0=0x7
|
||||
phy_xaui_tx_polarity_flip_104.0=0x3
|
||||
phy_xaui_tx_polarity_flip_105.0=0x1
|
||||
|
||||
#FP18
|
||||
dport_map_port_106.0=69
|
||||
dport_map_port_108.0=70
|
||||
dport_map_port_107.0=71
|
||||
dport_map_port_109.0=72
|
||||
portmap_106.0=101:100
|
||||
portmap_107.0=102:25:i
|
||||
portmap_108.0=103:25:50:i
|
||||
portmap_109.0=104:25:i
|
||||
xgxs_rx_lane_map_106.0=0x0213
|
||||
xgxs_tx_lane_map_106.0=0x123
|
||||
phy_xaui_rx_polarity_flip_106.0=0xd
|
||||
phy_xaui_rx_polarity_flip_107.0=0x6
|
||||
phy_xaui_rx_polarity_flip_108.0=0x3
|
||||
phy_xaui_rx_polarity_flip_109.0=0x1
|
||||
phy_xaui_tx_polarity_flip_106.0=0xf
|
||||
phy_xaui_tx_polarity_flip_107.0=0x7
|
||||
phy_xaui_tx_polarity_flip_108.0=0x3
|
||||
phy_xaui_tx_polarity_flip_109.0=0x1
|
||||
|
||||
#FP19
|
||||
dport_map_port_113.0=73
|
||||
dport_map_port_112.0=74
|
||||
dport_map_port_111.0=75
|
||||
dport_map_port_110.0=76
|
||||
portmap_110.0=105:100
|
||||
portmap_111.0=106:25:i
|
||||
portmap_112.0=107:25:50:i
|
||||
portmap_113.0=108:25:i
|
||||
xgxs_rx_lane_map_110.0=0x3210
|
||||
xgxs_tx_lane_map_110.0=0x132
|
||||
phy_xaui_rx_polarity_flip_110.0=0xf
|
||||
phy_xaui_rx_polarity_flip_111.0=0x7
|
||||
phy_xaui_rx_polarity_flip_112.0=0x3
|
||||
phy_xaui_rx_polarity_flip_113.0=0x1
|
||||
phy_xaui_tx_polarity_flip_110.0=0xf
|
||||
phy_xaui_tx_polarity_flip_111.0=0x7
|
||||
phy_xaui_tx_polarity_flip_112.0=0x3
|
||||
phy_xaui_tx_polarity_flip_113.0=0x1
|
||||
|
||||
#FP20
|
||||
dport_map_port_117.0=77
|
||||
dport_map_port_116.0=78
|
||||
dport_map_port_115.0=79
|
||||
dport_map_port_114.0=80
|
||||
portmap_114.0=109:100
|
||||
portmap_115.0=110:25:i
|
||||
portmap_116.0=111:25:50:i
|
||||
portmap_117.0=112:25:i
|
||||
xgxs_rx_lane_map_114.0=0x3210
|
||||
xgxs_tx_lane_map_114.0=0x123
|
||||
phy_xaui_rx_polarity_flip_114.0=0x0
|
||||
phy_xaui_rx_polarity_flip_115.0=0x0
|
||||
phy_xaui_rx_polarity_flip_116.0=0x0
|
||||
phy_xaui_rx_polarity_flip_117.0=0x0
|
||||
phy_xaui_tx_polarity_flip_114.0=0xf
|
||||
phy_xaui_tx_polarity_flip_115.0=0x7
|
||||
phy_xaui_tx_polarity_flip_116.0=0x3
|
||||
phy_xaui_tx_polarity_flip_117.0=0x1
|
||||
|
||||
#FP21
|
||||
dport_map_port_24.0=81
|
||||
dport_map_port_22.0=82
|
||||
dport_map_port_21.0=83
|
||||
dport_map_port_23.0=84
|
||||
portmap_21.0=21:100
|
||||
portmap_22.0=22:25:i
|
||||
portmap_23.0=23:25:50:i
|
||||
portmap_24.0=24:25:i
|
||||
xgxs_rx_lane_map_21.0=0x3102
|
||||
xgxs_tx_lane_map_21.0=0x132
|
||||
phy_xaui_rx_polarity_flip_21.0=0x0
|
||||
phy_xaui_rx_polarity_flip_22.0=0x0
|
||||
phy_xaui_rx_polarity_flip_23.0=0x0
|
||||
phy_xaui_rx_polarity_flip_24.0=0x0
|
||||
phy_xaui_tx_polarity_flip_21.0=0xf
|
||||
phy_xaui_tx_polarity_flip_22.0=0x7
|
||||
phy_xaui_tx_polarity_flip_23.0=0x3
|
||||
phy_xaui_tx_polarity_flip_24.0=0x1
|
||||
|
||||
#FP22
|
||||
dport_map_port_19.0=85
|
||||
dport_map_port_18.0=86
|
||||
dport_map_port_17.0=87
|
||||
dport_map_port_20.0=88
|
||||
portmap_17.0=17:100
|
||||
portmap_18.0=18:25:i
|
||||
portmap_19.0=19:25:50:i
|
||||
portmap_20.0=20:25:i
|
||||
xgxs_rx_lane_map_17.0=0x2103
|
||||
xgxs_tx_lane_map_17.0=0x3102
|
||||
phy_xaui_rx_polarity_flip_17.0=0x5
|
||||
phy_xaui_rx_polarity_flip_18.0=0x2
|
||||
phy_xaui_rx_polarity_flip_19.0=0x1
|
||||
phy_xaui_rx_polarity_flip_20.0=0x0
|
||||
phy_xaui_tx_polarity_flip_17.0=0xf
|
||||
phy_xaui_tx_polarity_flip_18.0=0x7
|
||||
phy_xaui_tx_polarity_flip_19.0=0x3
|
||||
phy_xaui_tx_polarity_flip_20.0=0x1
|
||||
|
||||
#FP23
|
||||
dport_map_port_31.0=89
|
||||
dport_map_port_32.0=90
|
||||
dport_map_port_29.0=91
|
||||
dport_map_port_30.0=92
|
||||
portmap_29.0=29:100
|
||||
portmap_30.0=30:25:i
|
||||
portmap_31.0=31:25:50:i
|
||||
portmap_32.0=32:25:i
|
||||
xgxs_rx_lane_map_29.0=0x2301
|
||||
xgxs_tx_lane_map_29.0=0x1023
|
||||
phy_xaui_rx_polarity_flip_29.0=0x0
|
||||
phy_xaui_rx_polarity_flip_30.0=0x0
|
||||
phy_xaui_rx_polarity_flip_31.0=0x0
|
||||
phy_xaui_rx_polarity_flip_32.0=0x0
|
||||
phy_xaui_tx_polarity_flip_29.0=0xb
|
||||
phy_xaui_tx_polarity_flip_30.0=0x5
|
||||
phy_xaui_tx_polarity_flip_31.0=0x2
|
||||
phy_xaui_tx_polarity_flip_32.0=0x1
|
||||
|
||||
#FP24
|
||||
dport_map_port_27.0=93
|
||||
dport_map_port_28.0=94
|
||||
dport_map_port_26.0=95
|
||||
dport_map_port_25.0=96
|
||||
portmap_25.0=25:100
|
||||
portmap_26.0=26:25:i
|
||||
portmap_27.0=27:25:50:i
|
||||
portmap_28.0=28:25:i
|
||||
xgxs_rx_lane_map_25.0=0x2310
|
||||
xgxs_tx_lane_map_25.0=0x2130
|
||||
phy_xaui_rx_polarity_flip_25.0=0x2
|
||||
phy_xaui_rx_polarity_flip_26.0=0x1
|
||||
phy_xaui_rx_polarity_flip_27.0=0x0
|
||||
phy_xaui_rx_polarity_flip_28.0=0x0
|
||||
phy_xaui_tx_polarity_flip_25.0=0xa
|
||||
phy_xaui_tx_polarity_flip_26.0=0x5
|
||||
phy_xaui_tx_polarity_flip_27.0=0x2
|
||||
phy_xaui_tx_polarity_flip_28.0=0x1
|
||||
|
||||
#FP25
|
||||
dport_map_port_125.0=97
|
||||
dport_map_port_124.0=98
|
||||
dport_map_port_122.0=99
|
||||
dport_map_port_123.0=100
|
||||
portmap_122.0=117:100
|
||||
portmap_123.0=118:25:i
|
||||
portmap_124.0=119:25:50:i
|
||||
portmap_125.0=120:25:i
|
||||
xgxs_rx_lane_map_122.0=0x3201
|
||||
xgxs_tx_lane_map_122.0=0x2310
|
||||
phy_xaui_rx_polarity_flip_122.0=0xc
|
||||
phy_xaui_rx_polarity_flip_123.0=0x6
|
||||
phy_xaui_rx_polarity_flip_124.0=0x3
|
||||
phy_xaui_rx_polarity_flip_125.0=0x1
|
||||
phy_xaui_tx_polarity_flip_122.0=0xf
|
||||
phy_xaui_tx_polarity_flip_123.0=0x7
|
||||
phy_xaui_tx_polarity_flip_124.0=0x3
|
||||
phy_xaui_tx_polarity_flip_125.0=0x1
|
||||
|
||||
#FP26
|
||||
dport_map_port_118.0=101
|
||||
dport_map_port_119.0=102
|
||||
dport_map_port_120.0=103
|
||||
dport_map_port_121.0=104
|
||||
portmap_118.0=113:100
|
||||
portmap_119.0=114:25:i
|
||||
portmap_120.0=115:25:50:i
|
||||
portmap_121.0=116:25:i
|
||||
xgxs_rx_lane_map_118.0=0x0123
|
||||
xgxs_tx_lane_map_118.0=0x2013
|
||||
phy_xaui_rx_polarity_flip_118.0=0x8
|
||||
phy_xaui_rx_polarity_flip_119.0=0x4
|
||||
phy_xaui_rx_polarity_flip_120.0=0x2
|
||||
phy_xaui_rx_polarity_flip_121.0=0x1
|
||||
phy_xaui_tx_polarity_flip_118.0=0x0
|
||||
phy_xaui_tx_polarity_flip_119.0=0x0
|
||||
phy_xaui_tx_polarity_flip_120.0=0x0
|
||||
phy_xaui_tx_polarity_flip_121.0=0x0
|
||||
|
||||
#FP27
|
||||
dport_map_port_131.0=105
|
||||
dport_map_port_130.0=106
|
||||
dport_map_port_132.0=107
|
||||
dport_map_port_133.0=108
|
||||
portmap_130.0=125:100
|
||||
portmap_131.0=126:25:i
|
||||
portmap_132.0=127:25:50:i
|
||||
portmap_133.0=128:25:i
|
||||
xgxs_rx_lane_map_130.0=0x1023
|
||||
xgxs_tx_lane_map_130.0=0x132
|
||||
phy_xaui_rx_polarity_flip_130.0=0x4
|
||||
phy_xaui_rx_polarity_flip_131.0=0x2
|
||||
phy_xaui_rx_polarity_flip_132.0=0x1
|
||||
phy_xaui_rx_polarity_flip_133.0=0x0
|
||||
phy_xaui_tx_polarity_flip_130.0=0xb
|
||||
phy_xaui_tx_polarity_flip_131.0=0x5
|
||||
phy_xaui_tx_polarity_flip_132.0=0x2
|
||||
phy_xaui_tx_polarity_flip_133.0=0x1
|
||||
|
||||
#FP28
|
||||
dport_map_port_126.0=109
|
||||
dport_map_port_128.0=110
|
||||
dport_map_port_127.0=111
|
||||
dport_map_port_129.0=112
|
||||
portmap_126.0=121:100
|
||||
portmap_127.0=122:25:i
|
||||
portmap_128.0=123:25:50:i
|
||||
portmap_129.0=124:25:i
|
||||
xgxs_rx_lane_map_126.0=0x0213
|
||||
xgxs_tx_lane_map_126.0=0x123
|
||||
phy_xaui_rx_polarity_flip_126.0=0x7
|
||||
phy_xaui_rx_polarity_flip_127.0=0x3
|
||||
phy_xaui_rx_polarity_flip_128.0=0x1
|
||||
phy_xaui_rx_polarity_flip_129.0=0x0
|
||||
phy_xaui_tx_polarity_flip_126.0=0x7
|
||||
phy_xaui_tx_polarity_flip_127.0=0x3
|
||||
phy_xaui_tx_polarity_flip_128.0=0x1
|
||||
phy_xaui_tx_polarity_flip_129.0=0x0
|
||||
|
||||
#FP29
|
||||
dport_map_port_6.0=113
|
||||
dport_map_port_7.0=114
|
||||
dport_map_port_5.0=115
|
||||
dport_map_port_8.0=116
|
||||
portmap_5.0=5:100
|
||||
portmap_6.0=6:25:i
|
||||
portmap_7.0=7:25:50:i
|
||||
portmap_8.0=8:25:i
|
||||
xgxs_rx_lane_map_5.0=0x1203
|
||||
xgxs_tx_lane_map_5.0=0x213
|
||||
phy_xaui_rx_polarity_flip_5.0=0x7
|
||||
phy_xaui_rx_polarity_flip_6.0=0x3
|
||||
phy_xaui_rx_polarity_flip_7.0=0x1
|
||||
phy_xaui_rx_polarity_flip_8.0=0x0
|
||||
phy_xaui_tx_polarity_flip_5.0=0x8
|
||||
phy_xaui_tx_polarity_flip_6.0=0x4
|
||||
phy_xaui_tx_polarity_flip_7.0=0x2
|
||||
phy_xaui_tx_polarity_flip_8.0=0x1
|
||||
|
||||
#FP30
|
||||
dport_map_port_1.0=117
|
||||
dport_map_port_3.0=118
|
||||
dport_map_port_2.0=119
|
||||
dport_map_port_4.0=120
|
||||
portmap_1.0=1:100
|
||||
portmap_2.0=2:25:i
|
||||
portmap_3.0=3:25:50:i
|
||||
portmap_4.0=4:25:i
|
||||
xgxs_rx_lane_map_1.0=0x0213
|
||||
xgxs_tx_lane_map_1.0=0x123
|
||||
phy_xaui_rx_polarity_flip_1.0=0x9
|
||||
phy_xaui_rx_polarity_flip_2.0=0x4
|
||||
phy_xaui_rx_polarity_flip_3.0=0x2
|
||||
phy_xaui_rx_polarity_flip_4.0=0x1
|
||||
phy_xaui_tx_polarity_flip_1.0=0x3
|
||||
phy_xaui_tx_polarity_flip_2.0=0x1
|
||||
phy_xaui_tx_polarity_flip_3.0=0x0
|
||||
phy_xaui_tx_polarity_flip_4.0=0x0
|
||||
|
||||
#FP31
|
||||
dport_map_port_16.0=121
|
||||
dport_map_port_15.0=122
|
||||
dport_map_port_13.0=123
|
||||
dport_map_port_14.0=124
|
||||
portmap_13.0=13:100
|
||||
portmap_14.0=14:25:i
|
||||
portmap_15.0=15:25:50:i
|
||||
portmap_16.0=16:25:i
|
||||
xgxs_rx_lane_map_13.0=0x3201
|
||||
xgxs_tx_lane_map_13.0=0x2301
|
||||
phy_xaui_rx_polarity_flip_13.0=0xc
|
||||
phy_xaui_rx_polarity_flip_14.0=0x6
|
||||
phy_xaui_rx_polarity_flip_15.0=0x3
|
||||
phy_xaui_rx_polarity_flip_16.0=0x1
|
||||
phy_xaui_tx_polarity_flip_13.0=0xc
|
||||
phy_xaui_tx_polarity_flip_14.0=0x6
|
||||
phy_xaui_tx_polarity_flip_15.0=0x3
|
||||
phy_xaui_tx_polarity_flip_16.0=0x1
|
||||
|
||||
#FP32
|
||||
dport_map_port_9.0=125
|
||||
dport_map_port_11.0=126
|
||||
dport_map_port_10.0=127
|
||||
dport_map_port_12.0=128
|
||||
portmap_9.0=9:100
|
||||
portmap_10.0=10:25:i
|
||||
portmap_11.0=11:25:50:i
|
||||
portmap_12.0=12:25:i
|
||||
xgxs_rx_lane_map_9.0=0x0213
|
||||
xgxs_tx_lane_map_9.0=0x123
|
||||
phy_xaui_rx_polarity_flip_9.0=0x8
|
||||
phy_xaui_rx_polarity_flip_10.0=0x4
|
||||
phy_xaui_rx_polarity_flip_11.0=0x2
|
||||
phy_xaui_rx_polarity_flip_12.0=0x1
|
||||
phy_xaui_tx_polarity_flip_9.0=0x3
|
||||
phy_xaui_tx_polarity_flip_10.0=0x1
|
||||
phy_xaui_tx_polarity_flip_11.0=0x0
|
||||
phy_xaui_tx_polarity_flip_12.0=0x0
|
||||
|
||||
|
||||
mmu_init_config="MSFT-TH-Tier0"
|
||||
|
Loading…
Reference in New Issue
Block a user