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[platform/nephos] Upgrade nephos-modules from 1.0.0 to 1.0.1 (#4267) (#4297)

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simonJi2018 2020-03-24 15:04:59 +08:00 committed by GitHub
parent ee84dca683
commit cf1dd5bae3
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23 changed files with 1828 additions and 407 deletions
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2
platform/nephos/nephos-modules.mk
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@ -1,6 +1,6 @@
# Nephos Platform modules
VERSION = 1.0.0
VERSION = 1.0.1
ifneq ($(NEPHOS_SAI_DEB_LOCAL_URL), )
SDK_FROM_LOCAL = y

8
platform/nephos/nephos-modules/debian/changelog
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@ -1,5 +1,11 @@
nephos-modules (1.0.1) unstable; urgency=low
* Upgrade ko version to 3.0.0
-- Support <simon.ji@mediatek.com> Tue, 17 Mar 2020 15:54:00 +0800
nephos-modules (1.0.0) unstable; urgency=low
* Initial release
-- Support <simon.ji@nephosinc.com> Fri, 15 Mar 2019 15:54:00 +0800
-- Support <simon.ji@nephosinc.com> Fri, 15 Mar 2019 15:54:00 +0800

2
platform/nephos/nephos-modules/debian/control
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@ -1,7 +1,7 @@
Source: nephos-modules
Section: main
Priority: extra
Maintainer: support <simon.ji@nephosinc.com>
Maintainer: support <simon.ji@mediatek.com>
Build-Depends: debhelper (>= 8.0.0), bzip2
Standards-Version: 3.9.3

0
platform/nephos/nephos-modules/modules/init.d/nps-modules-4.9.0-9-2-amd64 → platform/nephos/nephos-modules/modules/init.d/nps-modules-4.9-amd64
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4
platform/nephos/nephos-modules/modules/service/nps-modules-4.9.0-9-2-amd64.service → platform/nephos/nephos-modules/modules/service/nps-modules-4.9-amd64.service
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@ -5,8 +5,8 @@ Before=syncd.service
[Service]
Type=oneshot
ExecStart=-/etc/init.d/nps-modules-4.9.0-11-2-amd64 start
ExecStop=-/etc/init.d/nps-modules-4.9.0-11-2-amd64 stop
ExecStart=-/etc/init.d/nps-modules-4.9-amd64 start
ExecStop=-/etc/init.d/nps-modules-4.9-amd64 stop
RemainAfterExit=yes
[Install]

822
platform/nephos/nephos-modules/modules/src/hal_tau_pkt_knl.c
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File diff suppressed because it is too large Load Diff

2
platform/nephos/nephos-modules/modules/src/inc/aml.h
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@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

2
platform/nephos/nephos-modules/modules/src/inc/hal_dev.h
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@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

273
platform/nephos/nephos-modules/modules/src/inc/hal_tau_pkt_knl.h
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@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public
@ -104,15 +104,15 @@ typedef enum
/* hal_tau_const.h */
#define HAL_TAU_PORT_NUM (128)
#define HAL_TAU_EXCPT_CPU_NUM (256)
#define HAL_TAU_INVALID_NVO3_ENCAP_IDX (0x3FFF)
#define HAL_TAU_INVALID_NVO3_ADJ_IDX (0xFF)
#define HAL_TAU_EXCPT_CPU_BASE_ID (28 * 1024)
#define HAL_TAU_EXCPT_CPU_NON_L3_MIN (0)
#define HAL_TAU_EXCPT_CPU_NON_L3_MAX (HAL_TAU_EXCPT_CPU_NON_L3_MIN + HAL_TAU_EXCPT_CPU_NUM - 1)
#define HAL_TAU_EXCPT_CPU_L3_MIN (HAL_TAU_EXCPT_CPU_NON_L3_MIN + HAL_TAU_EXCPT_CPU_NUM)
#define HAL_TAU_EXCPT_CPU_L3_MAX (HAL_TAU_EXCPT_CPU_L3_MIN + HAL_TAU_EXCPT_CPU_NUM - 1)
#define HAL_PORT_NUM (128)
#define HAL_EXCPT_CPU_NUM (256)
#define HAL_INVALID_NVO3_ENCAP_IDX (0x3FFF)
#define HAL_INVALID_NVO3_ADJ_IDX (0xFF)
#define HAL_EXCPT_CPU_BASE_ID (28 * 1024)
#define HAL_EXCPT_CPU_NON_L3_MIN (0)
#define HAL_EXCPT_CPU_NON_L3_MAX (HAL_EXCPT_CPU_NON_L3_MIN + HAL_EXCPT_CPU_NUM - 1)
#define HAL_EXCPT_CPU_L3_MIN (HAL_EXCPT_CPU_NON_L3_MIN + HAL_EXCPT_CPU_NUM)
#define HAL_EXCPT_CPU_L3_MAX (HAL_EXCPT_CPU_L3_MIN + HAL_EXCPT_CPU_NUM - 1)
/* hal_tau_pkt_rsrc.h */
#define HAL_TAU_PKT_IPP_EXCPT_LAST (256)
@ -238,7 +238,7 @@ typedef struct
HAL_TAU_PKT_IPP_COPY2CPU_BITMAP_T ipp_copy2cpu_bitmap;
HAL_TAU_PKT_EPP_COPY2CPU_BITMAP_T epp_copy2cpu_bitmap;
} HAL_TAU_PKT_RX_REASON_BITMAP_T;
} HAL_PKT_RX_REASON_BITMAP_T;
/* hal_tau_pkt.h */
@ -246,23 +246,23 @@ typedef struct
/* NAMING DECLARATIONS
*/
/* PKT related configurable parameters */
#define HAL_TAU_PKT_RX_FREE_STACK_SIZE (64 * 1024)
#define HAL_TAU_PKT_RX_FREE_THREAD_PRI (80)
#define HAL_DFLT_CFG_PKT_RX_FREE_STACK_SIZE (64 * 1024)
#define HAL_DFLT_CFG_PKT_RX_FREE_THREAD_PRI (80)
#define HAL_TAU_PKT_RX_ISR_STACK_SIZE (64 * 1024)
#define HAL_TAU_PKT_RX_ISR_THREAD_PRI (80)
#define HAL_DFLT_CFG_PKT_RX_ISR_THREAD_STACK (64 * 1024)
#define HAL_DFLT_CFG_PKT_RX_ISR_THREAD_PRI (80)
#define HAL_TAU_PKT_TX_FREE_STACK_SIZE (64 * 1024)
#define HAL_TAU_PKT_TX_FREE_THREAD_PRI (80)
#define HAL_DFLT_CFG_PKT_TX_FREE_STACK_SIZE (64 * 1024)
#define HAL_DFLT_CFG_PKT_TX_FREE_THREAD_PRI (80)
#define HAL_TAU_PKT_TX_ISR_STACK_SIZE (64 * 1024)
#define HAL_TAU_PKT_TX_ISR_THREAD_PRI (80)
#define HAL_DFLT_CFG_PKT_TX_ISR_THREAD_STACK (64 * 1024)
#define HAL_DFLT_CFG_PKT_TX_ISR_THREAD_PRI (80)
#define HAL_TAU_PKT_TX_NET_STACK_SIZE (64 * 1024)
#define HAL_TAU_PKT_TX_NET_THREAD_PRI (80)
#define HAL_DFLT_CFG_PKT_TX_NET_STACK_SIZE (64 * 1024)
#define HAL_DFLT_CFG_PKT_TX_NET_THREAD_PRI (80)
#define HAL_TAU_PKT_ERROR_ISR_STACK_SIZE (64 * 1024)
#define HAL_TAU_PKT_ERROR_ISR_THREAD_PRI (80)
#define HAL_DFLT_CFG_PKT_ERROR_ISR_THREAD_STACK (64 * 1024)
#define HAL_DFLT_CFG_PKT_ERROR_ISR_THREAD_PRI (80)
/* PKT definitions */
#define HAL_TAU_PKT_TX_MAX_LEN (9216)
@ -300,29 +300,29 @@ typedef struct
/* PDMA Definitions */
#define HAL_TAU_PKT_PDMA_MAX_GPD_PER_PKT (10) /* <= 256 */
#define HAL_TAU_PKT_PDMA_TX_GPD_NUM (1024) /* <= 65535 */
#define HAL_TAU_PKT_PDMA_RX_GPD_NUM (1024) /* <= 65535 */
#define HAL_DFLT_CFG_PKT_TX_GPD_NUM (1024) /* <= 65535 */
#define HAL_DFLT_CFG_PKT_RX_GPD_NUM (1024) /* <= 65535 */
#define HAL_TAU_PKT_PDMA_TX_INTR_TIMEOUT (10 * 1000) /* us */
#define HAL_TAU_PKT_PDMA_TX_POLL_MAX_LOOP (10 * 1000) /* int */
/* Mode */
#define HAL_TAU_PKT_TX_WAIT_MODE (HAL_TAU_PKT_TX_WAIT_ASYNC)
#define HAL_TAU_PKT_RX_SCHED_MODE (HAL_TAU_PKT_RX_SCHED_RR)
#define HAL_DFLT_CFG_PKT_RX_SCHED_MODE (HAL_TAU_PKT_RX_SCHED_RR)
/* TX Queue */
#define HAL_TAU_PKT_TX_QUEUE_LEN (HAL_TAU_PKT_PDMA_TX_GPD_NUM * 10)
#define HAL_TAU_PKT_TX_TASK_MAX_LOOP (HAL_TAU_PKT_TX_QUEUE_LEN)
#define HAL_DFLT_CFG_PKT_TX_QUEUE_LEN (HAL_DFLT_CFG_PKT_TX_GPD_NUM * 10)
#define HAL_TAU_PKT_TX_TASK_MAX_LOOP (HAL_DFLT_CFG_PKT_TX_QUEUE_LEN)
/* RX Queue */
#define HAL_TAU_PKT_RX_QUEUE_NUM (HAL_TAU_PKT_RX_CHANNEL_LAST)
#define HAL_TAU_PKT_RX_QUEUE_WEIGHT (10)
#define HAL_TAU_PKT_RX_QUEUE_LEN (HAL_TAU_PKT_PDMA_RX_GPD_NUM * 10)
#define HAL_TAU_PKT_RX_TASK_MAX_LOOP (HAL_TAU_PKT_RX_QUEUE_LEN)
#define HAL_DFLT_CFG_PKT_RX_QUEUE_WEIGHT (10)
#define HAL_DFLT_CFG_PKT_RX_QUEUE_LEN (HAL_DFLT_CFG_PKT_RX_GPD_NUM * 10)
#define HAL_TAU_PKT_RX_TASK_MAX_LOOP (HAL_DFLT_CFG_PKT_RX_QUEUE_LEN)
/* MACRO FUNCTION DECLARATIONS
*/
/*---------------------------------------------------------------------------*/
/* [Taurus] Alignment to 64-bytes */
/* [NP8360] Alignment to 64-bytes */
#if defined(NPS_EN_HOST_64_BIT_BIG_ENDIAN) || defined(NPS_EN_HOST_64_BIT_LITTLE_ENDIAN)
#define HAL_TAU_PKT_PDMA_ALIGN_ADDR(pdma_addr, align_sz) (((pdma_addr) + (align_sz)) & 0xFFFFFFFFFFFFFFC0)
#else
@ -1120,77 +1120,77 @@ typedef struct
/* ----------------------------------------------------------------------------------- Reg Type */
typedef enum
{
HAL_TAU_PKT_L2_ISR_RCH0 = (0x1 << 0),
HAL_TAU_PKT_L2_ISR_RCH1 = (0x1 << 1),
HAL_TAU_PKT_L2_ISR_RCH2 = (0x1 << 2),
HAL_TAU_PKT_L2_ISR_RCH3 = (0x1 << 3),
HAL_TAU_PKT_L2_ISR_TCH0 = (0x1 << 4),
HAL_TAU_PKT_L2_ISR_TCH1 = (0x1 << 5),
HAL_TAU_PKT_L2_ISR_TCH2 = (0x1 << 6),
HAL_TAU_PKT_L2_ISR_TCH3 = (0x1 << 7),
HAL_TAU_PKT_L2_ISR_RX_QID_MAP_ERR = (0x1 << 8),
HAL_TAU_PKT_L2_ISR_RX_FRAME_ERR = (0x1 << 9)
HAL_TAU_PKT_L2_ISR_RCH0 = (0x1UL << 0),
HAL_TAU_PKT_L2_ISR_RCH1 = (0x1UL << 1),
HAL_TAU_PKT_L2_ISR_RCH2 = (0x1UL << 2),
HAL_TAU_PKT_L2_ISR_RCH3 = (0x1UL << 3),
HAL_TAU_PKT_L2_ISR_TCH0 = (0x1UL << 4),
HAL_TAU_PKT_L2_ISR_TCH1 = (0x1UL << 5),
HAL_TAU_PKT_L2_ISR_TCH2 = (0x1UL << 6),
HAL_TAU_PKT_L2_ISR_TCH3 = (0x1UL << 7),
HAL_TAU_PKT_L2_ISR_RX_QID_MAP_ERR = (0x1UL << 8),
HAL_TAU_PKT_L2_ISR_RX_FRAME_ERR = (0x1UL << 9)
} HAL_TAU_PKT_L2_ISR_T;
typedef enum
{
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_HWO_ERROR = (0x1 << 0), /* Tx GPD.hwo = 0 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_CHKSM_ERROR = (0x1 << 1), /* Tx GPD.chksm is error */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_NO_OVFL_ERROR = (0x1 << 2), /* S/W push too much GPD */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_DMA_READ_ERROR = (0x1 << 3), /* AXI Rd Error when do GPD read */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_BUF_SIZE_ERROR = (0x1 << 4), /* Tx GPD.data_buf_size = 0 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_RUNT_ERROR = (0x1 << 5), /* Tx GPD.pkt_len < 64 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_OVSZ_ERROR = (0x1 << 6), /* Tx GPD.pkt_len = 9217 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_LEN_MISMATCH_ERROR = (0x1 << 7), /* Tx GPD.pkt_len != sum of data_buf_size */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_PKTPL_DMA_READ_ERROR = (0x1 << 8), /* AXI Rd Error when do Payload read */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_COS_ERROR = (0x1 << 9), /* Tx GPD.cos is not match cos_to_tch_map */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_GT255_ERROR = (0x1 << 10), /* Multi-GPD packet's GPD# > 255 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_PFC = (0x1 << 11), /* */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_CREDIT_UDFL_ERROR = (0x1 << 12), /* Credit Underflow (count down to 0) */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_DMA_WRITE_ERROR = (0x1 << 13), /* AXI Wr Error (GPD Write-Back) */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_STOP_CMD_CPLT = (0x1 << 14)
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_HWO_ERROR = (0x1UL << 0), /* Tx GPD.hwo = 0 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_CHKSM_ERROR = (0x1UL << 1), /* Tx GPD.chksm is error */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_NO_OVFL_ERROR = (0x1UL << 2), /* S/W push too much GPD */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_DMA_READ_ERROR = (0x1UL << 3), /* AXI Rd Error when do GPD read */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_BUF_SIZE_ERROR = (0x1UL << 4), /* Tx GPD.data_buf_size = 0 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_RUNT_ERROR = (0x1UL << 5), /* Tx GPD.pkt_len < 64 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_OVSZ_ERROR = (0x1UL << 6), /* Tx GPD.pkt_len = 9217 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_LEN_MISMATCH_ERROR = (0x1UL << 7), /* Tx GPD.pkt_len != sum of data_buf_size */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_PKTPL_DMA_READ_ERROR = (0x1UL << 8), /* AXI Rd Error when do Payload read */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_COS_ERROR = (0x1UL << 9), /* Tx GPD.cos is not match cos_to_tch_map */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_GPD_GT255_ERROR = (0x1UL << 10), /* Multi-GPD packet's GPD# > 255 */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_PFC = (0x1UL << 11), /* */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_CREDIT_UDFL_ERROR = (0x1UL << 12), /* Credit Underflow (count down to 0) */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_DMA_WRITE_ERROR = (0x1UL << 13), /* AXI Wr Error (GPD Write-Back) */
HAL_TAU_PKT_TX_CHANNEL_L2_ISR_STOP_CMD_CPLT = (0x1UL << 14)
} HAL_TAU_PKT_TX_CHANNEL_L2_ISR_T;
typedef enum
{
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_AVAIL_GPD_LOW = (0x1 << 0), /* Rx GPD.avbl_gpd_num < threshold */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_AVAIL_GPD_EMPTY = (0x1 << 1), /* Rx GPD.avbl_gpd_num = 0 */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_AVAIL_GPD_ERROR = (0x1 << 2), /* Rx GPD.hwo = 0 */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_GPD_CHKSM_ERROR = (0x1 << 3), /* Rx GPD.chksm is error */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_DMA_READ_ERROR = (0x1 << 4), /* DMAR error occurs in PCIE */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_DMA_WRITE_ERROR = (0x1 << 5), /* DMAW error occurs in PCIE */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_STOP_CMD_CPLT = (0x1 << 6), /* Stop Completion Acknowledge */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_GPD_GT255_ERROR = (0x1 << 7), /* Multi-GPD packet's GPD# > 255 */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_TOD_UNINIT = (0x1 << 8), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_PKT_ERROR_DROP = (0x1 << 9), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_UDSZ_DROP = (0x1 << 10), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_OVSZ_DROP = (0x1 << 11), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_CMDQ_OVF_DROP = (0x1 << 12), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_FIFO_OVF_DROP = (0x1 << 13)
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_AVAIL_GPD_LOW = (0x1UL << 0), /* Rx GPD.avbl_gpd_num < threshold */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_AVAIL_GPD_EMPTY = (0x1UL << 1), /* Rx GPD.avbl_gpd_num = 0 */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_AVAIL_GPD_ERROR = (0x1UL << 2), /* Rx GPD.hwo = 0 */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_GPD_CHKSM_ERROR = (0x1UL << 3), /* Rx GPD.chksm is error */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_DMA_READ_ERROR = (0x1UL << 4), /* DMAR error occurs in PCIE */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_DMA_WRITE_ERROR = (0x1UL << 5), /* DMAW error occurs in PCIE */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_STOP_CMD_CPLT = (0x1UL << 6), /* Stop Completion Acknowledge */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_GPD_GT255_ERROR = (0x1UL << 7), /* Multi-GPD packet's GPD# > 255 */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_TOD_UNINIT = (0x1UL << 8), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_PKT_ERROR_DROP = (0x1UL << 9), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_UDSZ_DROP = (0x1UL << 10), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_OVSZ_DROP = (0x1UL << 11), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_CMDQ_OVF_DROP = (0x1UL << 12), /* */
HAL_TAU_PKT_RX_CHANNEL_L2_ISR_FIFO_OVF_DROP = (0x1UL << 13)
} HAL_TAU_PKT_RX_CHANNEL_L2_ISR_T;
typedef enum
{
HAL_TAU_PKT_TX_CHANNEL_CFG_IOC = (0x1 << 0),
HAL_TAU_PKT_TX_CHANNEL_CFG_CHKSUM = (0x1 << 1),
HAL_TAU_PKT_TX_CHANNEL_CFG_PFC = (0x1 << 2),
HAL_TAU_PKT_TX_CHANNEL_CFG_PKT_LEN_CHK = (0x1 << 3),
HAL_TAU_PKT_TX_CHANNEL_CFG_EARLY_DONE_IRQ = (0x1 << 4),
HAL_TAU_PKT_TX_CHANNEL_CFG_CHK_COS = (0x1 << 5),
HAL_TAU_PKT_TX_CHANNEL_CFG_ADV_GPD_WRBK = (0x1 << 6),
HAL_TAU_PKT_TX_CHANNEL_CFG_GPD_WRBK_FULL_PKT_LEN = (0x1 << 7),
HAL_TAU_PKT_TX_CHANNEL_CFG_LAST = (0x1 << 8)
HAL_TAU_PKT_TX_CHANNEL_CFG_IOC = (0x1UL << 0),
HAL_TAU_PKT_TX_CHANNEL_CFG_CHKSUM = (0x1UL << 1),
HAL_TAU_PKT_TX_CHANNEL_CFG_PFC = (0x1UL << 2),
HAL_TAU_PKT_TX_CHANNEL_CFG_PKT_LEN_CHK = (0x1UL << 3),
HAL_TAU_PKT_TX_CHANNEL_CFG_EARLY_DONE_IRQ = (0x1UL << 4),
HAL_TAU_PKT_TX_CHANNEL_CFG_CHK_COS = (0x1UL << 5),
HAL_TAU_PKT_TX_CHANNEL_CFG_ADV_GPD_WRBK = (0x1UL << 6),
HAL_TAU_PKT_TX_CHANNEL_CFG_GPD_WRBK_FULL_PKT_LEN = (0x1UL << 7),
HAL_TAU_PKT_TX_CHANNEL_CFG_LAST = (0x1UL << 8)
} HAL_TAU_PKT_TX_CHANNEL_CFG_T;
typedef enum
{
HAL_TAU_PKT_RX_CHANNEL_CFG_IOC = (0x1 << 0),
HAL_TAU_PKT_RX_CHANNEL_CFG_CHKSUM = (0x1 << 1),
HAL_TAU_PKT_RX_CHANNEL_CFG_LAST = (0x1 << 2)
HAL_TAU_PKT_RX_CHANNEL_CFG_IOC = (0x1UL << 0),
HAL_TAU_PKT_RX_CHANNEL_CFG_CHKSUM = (0x1UL << 1),
HAL_TAU_PKT_RX_CHANNEL_CFG_LAST = (0x1UL << 2)
} HAL_TAU_PKT_RX_CHANNEL_CFG_T;
@ -2079,34 +2079,56 @@ typedef struct
/* metadata */
UI8_T mac[6];
#define HAL_TAU_PKT_NETIF_INTF_FLAGS_MAC (1 << 0)
#define HAL_TAU_PKT_NETIF_INTF_FLAGS_MAC (1UL << 0)
UI32_T flags;
} HAL_TAU_PKT_NETIF_INTF_T;
#if defined(NETIF_EN_NETLINK)
typedef struct
{
C8_T name[NPS_NETIF_NAME_LEN];
C8_T mc_group_name[NPS_NETIF_NAME_LEN];
} HAL_TAU_PKT_NETIF_RX_DST_NETLINK_T;
#endif
typedef enum
{
HAL_TAU_PKT_NETIF_RX_DST_SDK = 0,
#if defined(NETIF_EN_NETLINK)
HAL_TAU_PKT_NETIF_RX_DST_NETLINK,
#endif
HAL_TAU_PKT_NETIF_RX_DST_LAST
} HAL_TAU_PKT_NETIF_RX_DST_TYPE_T;
typedef struct
{
/* unique key */
UI32_T id;
C8_T name[NPS_NETIF_NAME_LEN];
UI32_T priority;
UI32_T id;
C8_T name[NPS_NETIF_NAME_LEN];
UI32_T priority;
/* match fields */
UI32_T port; /* only support unit port and local port */
HAL_TAU_PKT_RX_REASON_BITMAP_T reason_bitmap;
UI8_T pattern[NPS_NETIF_PROFILE_PATTERN_NUM][NPS_NETIF_PROFILE_PATTERN_LEN];
UI8_T mask[NPS_NETIF_PROFILE_PATTERN_NUM][NPS_NETIF_PROFILE_PATTERN_LEN];
UI32_T offset[NPS_NETIF_PROFILE_PATTERN_NUM];
UI32_T port; /* only support unit port and local port */
HAL_PKT_RX_REASON_BITMAP_T reason_bitmap;
UI8_T pattern[NPS_NETIF_PROFILE_PATTERN_NUM][NPS_NETIF_PROFILE_PATTERN_LEN];
UI8_T mask[NPS_NETIF_PROFILE_PATTERN_NUM][NPS_NETIF_PROFILE_PATTERN_LEN];
UI32_T offset[NPS_NETIF_PROFILE_PATTERN_NUM];
/* for each flag 1:must hit, 0:don't care */
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PORT (1 << 0)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_REASON (1 << 1)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_0 (1 << 2)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_1 (1 << 3)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_2 (1 << 4)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_3 (1 << 5)
UI32_T flags;
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PORT (1UL << 0)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_REASON (1UL << 1)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_0 (1UL << 2)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_1 (1UL << 3)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_2 (1UL << 4)
#define HAL_TAU_PKT_NETIF_PROFILE_FLAGS_PATTERN_3 (1UL << 5)
UI32_T flags;
HAL_TAU_PKT_NETIF_RX_DST_TYPE_T dst_type;
#if defined(NETIF_EN_NETLINK)
HAL_TAU_PKT_NETIF_RX_DST_NETLINK_T netlink;
#endif
} HAL_TAU_PKT_NETIF_PROFILE_T;
@ -2141,6 +2163,13 @@ typedef enum
HAL_TAU_PKT_IOCTL_TYPE_CLEAR_RX_CNT,
/* port attribute */
HAL_TAU_PKT_IOCTL_TYPE_SET_PORT_ATTR,
#if defined(NETIF_EN_NETLINK)
HAL_TAU_PKT_IOCTL_TYPE_NL_SET_INTF_PROPERTY,
HAL_TAU_PKT_IOCTL_TYPE_NL_GET_INTF_PROPERTY,
HAL_TAU_PKT_IOCTL_TYPE_NL_CREATE_NETLINK,
HAL_TAU_PKT_IOCTL_TYPE_NL_DESTROY_NETLINK,
HAL_TAU_PKT_IOCTL_TYPE_NL_GET_NETLINK,
#endif
HAL_TAU_PKT_IOCTL_TYPE_LAST
} HAL_TAU_PKT_IOCTL_TYPE_T;
@ -2219,6 +2248,51 @@ typedef struct
} HAL_TAU_PKT_IOCTL_PORT_COOKIE_T;
#if defined(NETIF_EN_NETLINK)
#define NPS_NETIF_NETLINK_NUM_MAX (256)
#define NPS_NETIF_NETLINK_MC_GROUP_NUM_MAX (32)
typedef enum
{
NPS_NETIF_INTF_PROPERTY_IGR_SAMPLING_RATE,
NPS_NETIF_INTF_PROPERTY_EGR_SAMPLING_RATE,
NPS_NETIF_INTF_PROPERTY_LAST
} NPS_NETIF_INTF_PROPERTY_T;
typedef struct
{
C8_T name[NPS_NETIF_NAME_LEN];
} NPS_NETIF_NETLINK_MC_GROUP_T;
typedef struct
{
UI32_T id;
C8_T name[NPS_NETIF_NAME_LEN];
NPS_NETIF_NETLINK_MC_GROUP_T mc_group[NPS_NETIF_NETLINK_MC_GROUP_NUM_MAX];
UI32_T mc_group_num;
} NPS_NETIF_NETLINK_T;
typedef struct
{
/* intf property */
UI32_T intf_id;
NPS_NETIF_INTF_PROPERTY_T property;
UI32_T param0;
UI32_T param1;
/* netlink */
NPS_NETIF_NETLINK_T netlink;
NPS_ERROR_NO_T rc;
} HAL_TAU_PKT_NL_IOCTL_COOKIE_T;
#endif /* End of NETIF_EN_NETLINK */
typedef union
{
UI32_T value;
@ -2231,6 +2305,7 @@ typedef union
} HAL_TAU_PKT_IOCTL_CMD_T;
#endif /* End of NPS_EN_NETIF */
NPS_ERROR_NO_T

104
platform/nephos/nephos-modules/modules/src/inc/netif_nl.h Executable file
View File

@ -0,0 +1,104 @@
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program.
*/
/* FILE NAME: netif_nl.h
* PURPOSE:
* It provide xxx API.
* NOTES:
*/
#ifndef NETIF_NL_H
#define NETIF_NL_H
#include <linux/skbuff.h>
#define NETIF_NL_NETLINK_MC_GROUP_NUM (32)
#define NETIF_NL_NETLINK_NAME_LEN (16)
typedef enum
{
NETIF_NL_INTF_PROPERTY_IGR_SAMPLING_RATE,
NETIF_NL_INTF_PROPERTY_EGR_SAMPLING_RATE,
NETIF_NL_INTF_PROPERTY_LAST
} NETIF_NL_INTF_PROPERTY_T;
/* must be the same with NPS_NETIF_RX_DST_NETLINK_T */
typedef struct
{
C8_T name[NETIF_NL_NETLINK_NAME_LEN];
C8_T mc_group_name[NETIF_NL_NETLINK_NAME_LEN];
} NETIF_NL_RX_DST_NETLINK_T;
/* must be the same with NPS_NETIF_NETLINK_MC_GROUP_T */
typedef struct
{
C8_T name[NETIF_NL_NETLINK_NAME_LEN];
} NETIF_NL_NETLINK_MC_GROUP_T;
/* must be the same with NPS_NETIF_NETLINK_T */
typedef struct
{
UI32_T id;
C8_T name[NETIF_NL_NETLINK_NAME_LEN];
NETIF_NL_NETLINK_MC_GROUP_T mc_group[NETIF_NL_NETLINK_MC_GROUP_NUM];
UI32_T mc_group_num;
} NETIF_NL_NETLINK_T;
NPS_ERROR_NO_T
netif_nl_rxSkb(
const UI32_T unit,
struct sk_buff *ptr_skb,
void *ptr_cookie);
NPS_ERROR_NO_T
netif_nl_setIntfProperty(
const UI32_T unit,
const UI32_T id,
const NETIF_NL_INTF_PROPERTY_T property,
const UI32_T param0,
const UI32_T param1);
NPS_ERROR_NO_T
netif_nl_getIntfProperty(
const UI32_T unit,
const UI32_T port,
const NETIF_NL_INTF_PROPERTY_T property,
UI32_T *ptr_param0,
UI32_T *ptr_param1);
NPS_ERROR_NO_T
netif_nl_createNetlink(
const UI32_T unit,
NETIF_NL_NETLINK_T *ptr_netlink,
UI32_T *ptr_netlink_id);
NPS_ERROR_NO_T
netif_nl_destroyNetlink(
const UI32_T unit,
const UI32_T group_id);
NPS_ERROR_NO_T
netif_nl_getNetlink(
const UI32_T unit,
const UI32_T netlink_id,
NETIF_NL_NETLINK_T *ptr_netlink);
NPS_ERROR_NO_T
netif_nl_init(void);
#endif /* end of NETIF_NL_H */

2
platform/nephos/nephos-modules/modules/src/inc/netif_osal.h
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

2
platform/nephos/nephos-modules/modules/src/inc/netif_perf.h
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

2
platform/nephos/nephos-modules/modules/src/inc/nps_cfg.h
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

2
platform/nephos/nephos-modules/modules/src/inc/nps_error.h
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

2
platform/nephos/nephos-modules/modules/src/inc/nps_types.h
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

12
platform/nephos/nephos-modules/modules/src/inc/osal_mdc.h
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public
@ -134,6 +134,8 @@ typedef enum
OSAL_MDC_IOCTL_TYPE_MDC_FREE_SYS_DMA_MEM,
OSAL_MDC_IOCTL_TYPE_MDC_CONNECT_ISR,
OSAL_MDC_IOCTL_TYPE_MDC_DISCONNECT_ISR,
OSAL_MDC_IOCTL_TYPE_MDC_SAVE_PCI_CONFIG,
OSAL_MDC_IOCTL_TYPE_MDC_RESTORE_PCI_CONFIG,
OSAL_MDC_IOCTL_TYPE_LAST
} OSAL_MDC_IOCTL_TYPE_T;
@ -238,4 +240,12 @@ osal_mdc_invalidateCache(
void *ptr_virt_addr,
const UI32_T size);
NPS_ERROR_NO_T
osal_mdc_savePciConfig(
const UI32_T unit);
NPS_ERROR_NO_T
osal_mdc_restorePciConfig(
const UI32_T unit);
#endif /* OSAL_MDC_H */

2
platform/nephos/nephos-modules/modules/src/inc/osal_types.h
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

4
platform/nephos/nephos-modules/modules/src/make.mk
View File

@ -1,5 +1,5 @@
################################################################################
# Copyright (C) 2019 Nephos, Inc.
# Copyright (C) 2020 MediaTek, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of version 2 of the GNU General Public
@ -17,7 +17,7 @@ DEV_MODULE_NAME := nps_dev
NETIF_MODULE_NAME := nps_netif
################################################################################
DEV_OBJS_TOTAL := ./src/osal_mdc.o ./src/osal_isymbol.o
NETIF_OBJS_TOTAL := ./src/hal_tau_pkt_knl.o ./src/netif_perf.o ./src/netif_osal.o
NETIF_OBJS_TOTAL := ./src/hal_tau_pkt_knl.o ./src/netif_perf.o ./src/netif_osal.o ./src/netif_nl.o
obj-m := $(DEV_MODULE_NAME).o $(NETIF_MODULE_NAME).o
$(DEV_MODULE_NAME)-objs := $(DEV_OBJS_TOTAL)

811
platform/nephos/nephos-modules/modules/src/netif_nl.c Executable file
View File

@ -0,0 +1,811 @@
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program.
*/
/* FILE NAME: netif_xxx.c
* PURPOSE:
* It provide xxx API.
* NOTES:
*/
#include <nps_error.h>
#include <nps_types.h>
#include <netif_osal.h>
#include <netif_perf.h>
#include <netif_nl.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/version.h>
#include <net/genetlink.h>
extern UI32_T ext_dbg_flag;
#define NETIF_NL_DBG(__flag__, ...) do \
{ \
if (0 != ((__flag__) & (ext_dbg_flag))) \
{ \
osal_printf(__VA_ARGS__); \
} \
}while (0)
#define NETIF_NL_DBG_NETLINK (0x1UL << 6)
#define NETIF_NL_FAMILY_NUM_MAX (256)
#define NETIF_NL_INTF_NUM_MAX (256)
#define NETIF_NL_GET_FAMILY_META(__idx__) &(_netif_nl_cb.fam_entry[__idx__].meta)
#define NETIF_NL_GET_INTF_IGR_SAMPLE_RATE(__inft_id__) (_netif_nl_cb.intf_entry[__inft_id__].igr_sample_rate)
#define NETIF_NL_FAMILY_IS_PSAMPLE(__ptr_family__) (0 == strncmp(__ptr_family__->name, \
NETIF_NL_PSAMPLE_FAMILY_NAME, \
NETIF_NL_NETLINK_NAME_LEN)) ? 1 : 0
/* porting part */
#define NETIF_NL_VER_NUM (1)
#define NETIF_NL_PSAMPLE_MAX_ATTR_NUM (NETIF_NL_PSAMPLE_ATTR_LAST)
#define NETIF_NL_REGISTER_FAMILY(__family__) genl_register_family(__family__)
#define NETIF_NL_UNREGISTER_FAMILY(__family__) genl_unregister_family(__family__)
#define NETIF_NL_ALLOC_SKB(__len__) genlmsg_new(__len__, GFP_ATOMIC)
#define NETIF_NL_FREE_SKB(__ptr_skb__) nlmsg_free(__ptr_skb__)
#define NETIF_NL_SEND_PKT(__ptr_family__, __mcgrp_id__, __ptr_skb__) \
genlmsg_multicast_netns(__ptr_family__, \
&init_net, \
__ptr_skb__, \
0, /* pid, avoid loop */ \
__mcgrp_id__, \
GFP_ATOMIC)
#define NETIF_NL_SET_SKB_ATTR_HDR(__skb__, __family__, __hdr_len__, __cmd__) \
genlmsg_put(__skb__, 0, 0, __family__, \
__hdr_len__, __cmd__)
#define NETIF_NL_END_SKB_ATTR_HDR(__skb__, __hdr__) genlmsg_end(__skb__, __hdr__)
#define NETIF_NL_SET_16_BIT_ATTR(__skb__, __attr__, __data__) nla_put_u16(__skb__, __attr__, __data__)
#define NETIF_NL_SET_32_BIT_ATTR(__skb__, __attr__, __data__) nla_put_u32(__skb__, __attr__, __data__)
/*
* <----------- nla_total_size(payload) ------------->
* +------------------+- - -+- - - - - - - - - +- - -+
* | Attribute Header | Pad | Payload | Pad |
* +------------------+- - -+- - - - - - - - - +- - -+
*
*
* <-------- nla_attr_size(payload) ---------->
* +------------------+- - -+- - - - - - - - - +- - -+
* | Attribute Header | Pad | Payload | Pad |
* +------------------+- - -+- - - - - - - - - +- - -+
*
*/
/* total size = attr data size + attr header size */
#define NETIF_NL_GET_ATTR_TOTAL_SIZE(__data_size__) nla_total_size(__data_size__)
#define NETIF_NL_GET_ATTR_SIZE(__data_size__) nla_attr_size(__data_size__) /* without padding */
/* psample's family and group parameter */
#define NETIF_NL_PSAMPLE_FAMILY_NAME "psample"
#define NETIF_NL_PSAMPLE_MC_GROUP_NAME_DATA "packets"
#define NETIF_NL_PSAMPLE_MC_GROUP_NAME_CFG "config"
#define NETIF_NL_PSAMPLE_MC_GROUP_NUM (NETIF_NL_PSAMPLE_MC_GROUP_ID_LAST)
#define NETIF_NL_DEFAULT_MC_GROUP_NUM (1)
#define NETIF_NL_PSAMPLE_PKT_LEN_MAX (9216)
#define NETIF_NL_PSAMPLE_DFLT_USR_GROUP_ID (1)
typedef enum
{
NETIF_NL_PSAMPLE_MC_GROUP_ID_CONFIG = 0,
NETIF_NL_PSAMPLE_MC_GROUP_ID_SAMPLE,
NETIF_NL_PSAMPLE_MC_GROUP_ID_LAST,
} NETIF_NL_PSAMPLE_MC_GROUP_ID_T;
typedef enum
{
NETIF_NL_PSAMPLE_ATTR_IIFINDEX = 0,
NETIF_NL_PSAMPLE_ATTR_OIFINDEX,
NETIF_NL_PSAMPLE_ATTR_ORIGSIZE,
NETIF_NL_PSAMPLE_ATTR_SAMPLE_GROUP,
NETIF_NL_PSAMPLE_ATTR_GROUP_SEQ,
NETIF_NL_PSAMPLE_ATTR_SAMPLE_RATE,
NETIF_NL_PSAMPLE_ATTR_DATA,
NETIF_NL_PSAMPLE_ATTR_LAST
} NETIF_NL_PSAMPLE_ATTR_ID_T;
typedef struct genl_multicast_group NETIF_NL_MC_GROUP_T;
typedef struct genl_family NETIF_NL_FAMILY_T;
static NETIF_NL_MC_GROUP_T _netif_nl_psample_mc_group[NETIF_NL_PSAMPLE_MC_GROUP_ID_LAST];
static C8_T *_ptr_netif_nl_psample_mc_group_name[NETIF_NL_PSAMPLE_MC_GROUP_ID_LAST] =
{
NETIF_NL_PSAMPLE_MC_GROUP_NAME_CFG,
NETIF_NL_PSAMPLE_MC_GROUP_NAME_DATA
};
static NETIF_NL_MC_GROUP_T _netif_nl_default_mc_group[NETIF_NL_DEFAULT_MC_GROUP_NUM];
static C8_T *_ptr_netif_nl_default_mc_group_name[NETIF_NL_DEFAULT_MC_GROUP_NUM] =
{
"default",
};
typedef struct
{
NETIF_NL_FAMILY_T meta;
BOOL_T valid;
} NETIF_NL_FAMILY_ENTRY_T;
typedef struct
{
UI32_T igr_sample_rate;
UI32_T egr_sample_rate;
UI32_T trunc_size;
} NETIF_NL_INTF_ENTRY_T;
typedef struct
{
NETIF_NL_FAMILY_ENTRY_T fam_entry[NETIF_NL_FAMILY_NUM_MAX];
NETIF_NL_INTF_ENTRY_T intf_entry[NETIF_NL_INTF_NUM_MAX]; /* sorted in intf_id */
UI32_T seq_num;
} NETIF_NL_CB_T;
static NETIF_NL_CB_T _netif_nl_cb;
/* should extract to common */
struct net_device_priv
{
struct net_device *ptr_net_dev;
struct net_device_stats stats;
UI32_T unit;
UI32_T id;
UI32_T port;
UI16_T vlan;
UI32_T speed;
};
static NPS_ERROR_NO_T
_netif_nl_setIntfIgrSampleRate(
const UI32_T unit,
const UI32_T id,
const UI32_T rate)
{
NETIF_NL_CB_T *ptr_cb = &_netif_nl_cb;
ptr_cb->intf_entry[id].igr_sample_rate = rate;
return (NPS_E_OK);
}
static NPS_ERROR_NO_T
_netif_nl_setIntfEgrSampleRate(
const UI32_T unit,
const UI32_T id,
const UI32_T rate)
{
NETIF_NL_CB_T *ptr_cb = &_netif_nl_cb;
ptr_cb->intf_entry[id].egr_sample_rate = rate;
return (NPS_E_OK);
}
NPS_ERROR_NO_T
netif_nl_setIntfProperty(
const UI32_T unit,
const UI32_T id,
const NETIF_NL_INTF_PROPERTY_T property,
const UI32_T param0,
const UI32_T param1)
{
NPS_ERROR_NO_T rc = NPS_E_BAD_PARAMETER;
if (NETIF_NL_INTF_PROPERTY_IGR_SAMPLING_RATE == property)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"receive set igr sample rate req, id=%d, property=%d, param0=%d, param=%d\n",
id, property, param0, param1);
rc = _netif_nl_setIntfIgrSampleRate(unit, id, param0);
}
else if (NETIF_NL_INTF_PROPERTY_EGR_SAMPLING_RATE == property)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"receive set egr sample rate req, id=%d, property=%d, param0=%d, param=%d\n",
id, property, param0, param1);
rc = _netif_nl_setIntfEgrSampleRate(unit, id, param0);
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[error] unknown property, property=%d\n", property);
}
return (rc);
}
static NPS_ERROR_NO_T
_netif_nl_getIntfIgrSampleRate(
const UI32_T unit,
const UI32_T id,
UI32_T *ptr_rate)
{
NETIF_NL_CB_T *ptr_cb = &_netif_nl_cb;
*ptr_rate = ptr_cb->intf_entry[id].igr_sample_rate;
return (NPS_E_OK);
}
static NPS_ERROR_NO_T
_netif_nl_getIntfEgrSampleRate(
const UI32_T unit,
const UI32_T id,
UI32_T *ptr_rate)
{
NETIF_NL_CB_T *ptr_cb = &_netif_nl_cb;
*ptr_rate = ptr_cb->intf_entry[id].egr_sample_rate;
return (NPS_E_OK);
}
NPS_ERROR_NO_T
netif_nl_getIntfProperty(
const UI32_T unit,
const UI32_T id,
const NETIF_NL_INTF_PROPERTY_T property,
UI32_T *ptr_param0,
UI32_T *ptr_param1)
{
NPS_ERROR_NO_T rc = NPS_E_BAD_PARAMETER;
if (NETIF_NL_INTF_PROPERTY_IGR_SAMPLING_RATE == property)
{
rc = _netif_nl_getIntfIgrSampleRate(unit, id, ptr_param0);
}
else if (NETIF_NL_INTF_PROPERTY_EGR_SAMPLING_RATE == property)
{
rc = _netif_nl_getIntfEgrSampleRate(unit, id, ptr_param0);
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[error] unknown property, property=%d\n",
property);
}
return (rc);
}
NPS_ERROR_NO_T
_netif_nl_allocNlFamilyEntry(
NETIF_NL_CB_T *ptr_cb,
UI32_T *ptr_index)
{
UI32_T idx;
NPS_ERROR_NO_T rc = NPS_E_TABLE_FULL;
for (idx = 0; idx < NETIF_NL_FAMILY_NUM_MAX; idx++)
{
if (FALSE == ptr_cb->fam_entry[idx].valid)
{
*ptr_index = idx;
ptr_cb->fam_entry[idx].valid = TRUE;
rc = NPS_E_OK;
break;
}
}
return (rc);
}
void
_netif_nl_freeNlFamilyEntry(
NETIF_NL_CB_T *ptr_cb,
const UI32_T index)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] free netlink family entry, idx=%d\n",
index);
ptr_cb->fam_entry[index].valid = FALSE;
}
NPS_ERROR_NO_T
_netif_nl_setNlMcgroupPsample(
NETIF_NL_FAMILY_T *ptr_nl_family)
{
NETIF_NL_MC_GROUP_T *ptr_nl_mc_group = _netif_nl_psample_mc_group;
UI32_T idx;
/* init the mc group and hook the group to family */
osal_memset(ptr_nl_mc_group, 0x0,
(NETIF_NL_PSAMPLE_MC_GROUP_NUM * sizeof(NETIF_NL_MC_GROUP_T)));
for (idx = 0; idx < NETIF_NL_PSAMPLE_MC_GROUP_ID_LAST; idx++)
{
osal_memcpy(ptr_nl_mc_group[idx].name,
_ptr_netif_nl_psample_mc_group_name[idx],
osal_strlen(_ptr_netif_nl_psample_mc_group_name[idx]));
}
ptr_nl_family->n_mcgrps = NETIF_NL_PSAMPLE_MC_GROUP_NUM;
ptr_nl_family->mcgrps = ptr_nl_mc_group;
return (NPS_E_OK);
}
NPS_ERROR_NO_T
_netif_nl_setNlMcgroupDefault(
NETIF_NL_FAMILY_T *ptr_nl_family)
{
NETIF_NL_MC_GROUP_T *ptr_nl_mc_group = _netif_nl_default_mc_group;
UI32_T idx;
/* init the mc group and hook the group to family */
osal_memset(ptr_nl_mc_group, 0x0,
(NETIF_NL_DEFAULT_MC_GROUP_NUM * sizeof(NETIF_NL_MC_GROUP_T)));
for (idx = 0; idx < NETIF_NL_DEFAULT_MC_GROUP_NUM; idx++)
{
osal_memcpy(ptr_nl_mc_group[idx].name,
_ptr_netif_nl_default_mc_group_name[idx],
osal_strlen(_ptr_netif_nl_default_mc_group_name[idx]));
}
ptr_nl_family->n_mcgrps = NETIF_NL_DEFAULT_MC_GROUP_NUM;
ptr_nl_family->mcgrps = ptr_nl_mc_group;
return (NPS_E_OK);
}
#define NETIF_NL_IS_FAMILY_ENTRY_VALID(__idx__) \
(TRUE == _netif_nl_cb.fam_entry[__idx__].valid) ? (TRUE) : (FALSE)
NPS_ERROR_NO_T
netif_nl_createNetlink(
const UI32_T unit,
NETIF_NL_NETLINK_T *ptr_netlink,
UI32_T *ptr_netlink_id)
{
NETIF_NL_CB_T *ptr_cb = &_netif_nl_cb;
UI32_T entry_id;
NETIF_NL_FAMILY_T *ptr_nl_family;
NETIF_NL_MC_GROUP_T *ptr_nl_mcgrp;
UI32_T idx;
int ret;
NPS_ERROR_NO_T rc;
rc = _netif_nl_allocNlFamilyEntry(ptr_cb, &entry_id);
if (NPS_E_OK == rc)
{
ptr_nl_family = NETIF_NL_GET_FAMILY_META(entry_id);
/* fill in the meta data for that netlink family */
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)
ptr_nl_family->id = GENL_ID_GENERATE; /* family id can be ignored since linux 4.10 */
#endif
ptr_nl_family->version = NETIF_NL_VER_NUM;
ptr_nl_family->maxattr = NETIF_NL_PSAMPLE_MAX_ATTR_NUM;
ptr_nl_family->netnsok = true;
osal_memcpy(ptr_nl_family->name, ptr_netlink->name, NETIF_NL_NETLINK_NAME_LEN);
/* fill in the mc group info */
ptr_nl_mcgrp = osal_alloc(sizeof(NETIF_NL_MC_GROUP_T)*ptr_netlink->mc_group_num);
if (NULL != ptr_nl_mcgrp)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK, "[DBG] create mc group:\n");
for (idx = 0; idx < ptr_netlink->mc_group_num; idx++)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] - mcgrp%d: %s\n", idx, ptr_netlink->mc_group[idx].name);
osal_memcpy(ptr_nl_mcgrp[idx].name, ptr_netlink->mc_group[idx].name,
NETIF_NL_NETLINK_NAME_LEN);
}
ptr_nl_family->n_mcgrps = ptr_netlink->mc_group_num;
ptr_nl_family->mcgrps = ptr_nl_mcgrp;
/* register the family to kernel */
ret = NETIF_NL_REGISTER_FAMILY(ptr_nl_family);
if (0 == ret)
{
*ptr_netlink_id = entry_id;
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] create netlink family, name=%s, entry_idx=%d, mcgrp_num=%d\n",
ptr_netlink->name, entry_id, ptr_nl_family->n_mcgrps);
rc = NPS_E_OK;
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] register netlink family failed, name=%s, ret=%d\n",
ptr_netlink->name, ret);
osal_free(ptr_nl_mcgrp);
_netif_nl_freeNlFamilyEntry(ptr_cb, entry_id);
rc = NPS_E_OTHERS;
}
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK, "[DBG] alloc mcgrp failed\n");
rc = NPS_E_NO_MEMORY;
}
}
return (rc);
}
NPS_ERROR_NO_T
netif_nl_destroyNetlink(
const UI32_T unit,
const UI32_T netlink_id)
{
NETIF_NL_CB_T *ptr_cb = &_netif_nl_cb;
UI32_T entry_idx = netlink_id;
NETIF_NL_FAMILY_T *ptr_nl_family;
int ret;
NPS_ERROR_NO_T rc;
if (TRUE == NETIF_NL_IS_FAMILY_ENTRY_VALID(entry_idx))
{
ptr_nl_family = NETIF_NL_GET_FAMILY_META(entry_idx);
ret = NETIF_NL_UNREGISTER_FAMILY(ptr_nl_family);
if (0 == ret)
{
osal_free(ptr_nl_family->mcgrps);
_netif_nl_freeNlFamilyEntry(ptr_cb, entry_idx);
rc = NPS_E_OK;
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] unregister netlink family failed, name=%s, ret=%d\n",
ptr_nl_family->name, ret);
rc = NPS_E_OTHERS;
}
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] destroy netlink failed, invalid netlink_id %d\n",
netlink_id);
rc = NPS_E_ENTRY_NOT_FOUND;
}
return (rc);
}
NPS_ERROR_NO_T
netif_nl_getNetlink(
const UI32_T unit,
const UI32_T netlink_id,
NETIF_NL_NETLINK_T *ptr_netlink)
{
UI32_T entry_idx = netlink_id;
NETIF_NL_FAMILY_T *ptr_meta;
UI32_T grp_idx;
NPS_ERROR_NO_T rc = NPS_E_OK;
if (TRUE == NETIF_NL_IS_FAMILY_ENTRY_VALID(entry_idx))
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] get valid netlink, id=%d\n", netlink_id);
ptr_netlink->id = netlink_id;
ptr_meta = NETIF_NL_GET_FAMILY_META(entry_idx);
ptr_netlink->mc_group_num = ptr_meta->n_mcgrps;
osal_memcpy(ptr_netlink->name, ptr_meta->name, NETIF_NL_NETLINK_NAME_LEN);
for (grp_idx = 0; grp_idx < ptr_meta->n_mcgrps; grp_idx++)
{
osal_memcpy(ptr_netlink->mc_group[grp_idx].name,
ptr_meta->mcgrps[grp_idx].name,
NETIF_NL_NETLINK_NAME_LEN);
}
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] get netlink failed, invalid netlink_id %d\n",
netlink_id);
rc = NPS_E_ENTRY_NOT_FOUND;
}
return (rc);
}
NPS_ERROR_NO_T
_netif_nl_getFamilyByName(
NETIF_NL_CB_T *ptr_cb,
const C8_T *ptr_name,
NETIF_NL_FAMILY_T **pptr_nl_family)
{
UI32_T idx;
NPS_ERROR_NO_T rc = NPS_E_ENTRY_NOT_FOUND;
for (idx = 0; idx < NETIF_NL_FAMILY_NUM_MAX; idx++)
{
if ((TRUE == ptr_cb->fam_entry[idx].valid) &&
(0 == strncmp(ptr_cb->fam_entry[idx].meta.name,
ptr_name,
NETIF_NL_NETLINK_NAME_LEN)))
{
*pptr_nl_family = &(ptr_cb->fam_entry[idx].meta);
rc = NPS_E_OK;
break;
}
}
if (NPS_E_ENTRY_NOT_FOUND == rc)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] find family failed, name=%s\n",
ptr_name);
}
return (rc);
}
NPS_ERROR_NO_T
_netif_nl_getMcgrpIdByName(
NETIF_NL_FAMILY_T *ptr_nl_family,
const C8_T *ptr_mcgrp_name,
UI32_T *ptr_mcgrp_id)
{
UI32_T idx;
NPS_ERROR_NO_T rc = NPS_E_ENTRY_NOT_FOUND;
for (idx = 0; idx < ptr_nl_family->n_mcgrps; idx++)
{
if ((0 == strncmp(ptr_nl_family->mcgrps[idx].name,
ptr_mcgrp_name,
NETIF_NL_NETLINK_NAME_LEN)))
{
*ptr_mcgrp_id = idx;
rc = NPS_E_OK;
break;
}
}
if (NPS_E_OK != rc)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] find mcgrp %s failed in family %s\n",
ptr_mcgrp_name, ptr_nl_family->name);
}
return (rc);
}
NPS_ERROR_NO_T
_netif_nl_allocPsampleSkb(
NETIF_NL_CB_T *ptr_cb,
NETIF_NL_FAMILY_T *ptr_nl_family,
struct sk_buff *ptr_ori_skb,
struct sk_buff **pptr_nl_skb)
{
UI32_T msg_hdr_len;
UI32_T data_len;
struct sk_buff *ptr_nl_skb;
UI16_T igr_intf_idx;
struct net_device_priv *ptr_priv;
UI32_T rate;
UI32_T intf_id;
void *ptr_nl_hdr = NULL;
struct nlattr *ptr_nl_attr;
NPS_ERROR_NO_T rc = NPS_E_OK;
/* make sure the total len (original pkt len + hdr msg) < PSAMPLE_MAX_PACKET_SIZE */
msg_hdr_len = NETIF_NL_GET_ATTR_TOTAL_SIZE(sizeof(UI16_T)) + /* PSAMPLE_ATTR_IIFINDEX */
NETIF_NL_GET_ATTR_TOTAL_SIZE(sizeof(UI32_T)) + /* PSAMPLE_ATTR_SAMPLE_RATE */
NETIF_NL_GET_ATTR_TOTAL_SIZE(sizeof(UI32_T)) + /* PSAMPLE_ATTR_ORIGSIZE */
NETIF_NL_GET_ATTR_TOTAL_SIZE(sizeof(UI32_T)) + /* PSAMPLE_ATTR_SAMPLE_GROUP */
NETIF_NL_GET_ATTR_TOTAL_SIZE(sizeof(UI32_T)); /* PSAMPLE_ATTR_GROUP_SEQ */
data_len = NETIF_NL_GET_ATTR_TOTAL_SIZE(ptr_ori_skb->len);
if ((msg_hdr_len + NETIF_NL_GET_ATTR_TOTAL_SIZE(ptr_ori_skb->len)) > NETIF_NL_PSAMPLE_PKT_LEN_MAX)
{
data_len = NETIF_NL_PSAMPLE_PKT_LEN_MAX - msg_hdr_len - NLA_HDRLEN - NLA_ALIGNTO;
}
else
{
data_len = ptr_ori_skb->len;
}
ptr_nl_skb = NETIF_NL_ALLOC_SKB(NETIF_NL_GET_ATTR_TOTAL_SIZE(data_len) + msg_hdr_len);
if (NULL != ptr_nl_skb)
{
/* to create a netlink msg header (cmd=0) */
ptr_nl_hdr = NETIF_NL_SET_SKB_ATTR_HDR(ptr_nl_skb, ptr_nl_family, 0, 0);
if (NULL != ptr_nl_hdr)
{
/* obtain the intf index for the igr_port */
igr_intf_idx = ptr_ori_skb->dev->ifindex;
NETIF_NL_SET_16_BIT_ATTR(ptr_nl_skb, NETIF_NL_PSAMPLE_ATTR_IIFINDEX,
(UI16_T)igr_intf_idx);
/* meta header */
/* use the igr port id as the index for the database to get sample rate */
ptr_priv = netdev_priv(ptr_ori_skb->dev);
intf_id = ptr_priv->port;
rate = NETIF_NL_GET_INTF_IGR_SAMPLE_RATE(intf_id);
NETIF_NL_SET_32_BIT_ATTR(ptr_nl_skb, NETIF_NL_PSAMPLE_ATTR_SAMPLE_RATE, rate);
NETIF_NL_SET_32_BIT_ATTR(ptr_nl_skb, NETIF_NL_PSAMPLE_ATTR_ORIGSIZE, data_len);
NETIF_NL_SET_32_BIT_ATTR(ptr_nl_skb, NETIF_NL_PSAMPLE_ATTR_SAMPLE_GROUP,
NETIF_NL_PSAMPLE_DFLT_USR_GROUP_ID);
NETIF_NL_SET_32_BIT_ATTR(ptr_nl_skb, NETIF_NL_PSAMPLE_ATTR_GROUP_SEQ, ptr_cb->seq_num);
ptr_cb->seq_num++;
/* data */
ptr_nl_attr = (struct nlattr *)skb_put(ptr_nl_skb, NETIF_NL_GET_ATTR_TOTAL_SIZE(data_len));
ptr_nl_attr->nla_type = NETIF_NL_PSAMPLE_ATTR_DATA;
/* get the attr size without padding, since it's the last one */
ptr_nl_attr->nla_len = NETIF_NL_GET_ATTR_SIZE(data_len);
skb_copy_bits(ptr_ori_skb, 0, nla_data(ptr_nl_attr), data_len);
NETIF_NL_END_SKB_ATTR_HDR(ptr_nl_skb, ptr_nl_hdr);
}
else
{
rc = NPS_E_OTHERS;
}
}
else
{
rc = NPS_E_OTHERS;
}
*pptr_nl_skb = ptr_nl_skb;
return (rc);
}
NPS_ERROR_NO_T
_netif_nl_allocNetlinkSkb(
NETIF_NL_CB_T *ptr_cb,
NETIF_NL_FAMILY_T *ptr_nl_family,
struct sk_buff *ptr_ori_skb,
struct sk_buff **pptr_nl_skb)
{
NPS_ERROR_NO_T rc = NPS_E_OK;
/* need to fill specific skb header format */
if (NETIF_NL_FAMILY_IS_PSAMPLE(ptr_nl_family))
{
rc = _netif_nl_allocPsampleSkb(ptr_cb, ptr_nl_family,
ptr_ori_skb, pptr_nl_skb);
if (NPS_E_OK != rc)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] alloc netlink skb failed\n");
}
}
else
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"[DBG] unknown netlink family\n");
rc = NPS_E_OTHERS;
}
return (rc);
}
NPS_ERROR_NO_T
_netif_nl_sendNetlinkSkb(
NETIF_NL_FAMILY_T *ptr_nl_family,
UI32_T nl_mcgrp_id,
struct sk_buff *ptr_nl_skb)
{
int ret;
NPS_ERROR_NO_T rc;
ret = NETIF_NL_SEND_PKT(ptr_nl_family, nl_mcgrp_id, ptr_nl_skb);
if (0 == ret)
{
rc = NPS_E_OK;
}
else
{
/* in errno_base.h, #define ESRCH 3 : No such process */
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK,
"send skb to mc group failed, ret=%d\n", ret);
rc = NPS_E_OTHERS;
}
return (rc);
}
void
_netif_nl_freeNetlinkSkb(
struct sk_buff *ptr_nl_skb)
{
NETIF_NL_DBG(NETIF_NL_DBG_NETLINK, "[DBG] free nl skb\n");
NETIF_NL_FREE_SKB(ptr_nl_skb);
}
NPS_ERROR_NO_T
_netif_nl_forwardPkt(
NETIF_NL_CB_T *ptr_cb,
NETIF_NL_RX_DST_NETLINK_T *ptr_nl_dest,
struct sk_buff *ptr_ori_skb)
{
struct sk_buff *ptr_nl_skb = NULL;
NETIF_NL_FAMILY_T *ptr_nl_family;
UI32_T nl_mcgrp_id;
NPS_ERROR_NO_T rc;
rc = _netif_nl_getFamilyByName(ptr_cb, ptr_nl_dest->name,
&ptr_nl_family);
if (NPS_E_OK == rc)
{
rc = _netif_nl_getMcgrpIdByName(ptr_nl_family, ptr_nl_dest->mc_group_name,
&nl_mcgrp_id);
if (NPS_E_OK == rc)
{
rc = _netif_nl_allocNetlinkSkb(ptr_cb, ptr_nl_family,
ptr_ori_skb, &ptr_nl_skb);
if (NPS_E_OK == rc)
{
rc = _netif_nl_sendNetlinkSkb(ptr_nl_family, nl_mcgrp_id,
ptr_nl_skb);
if (NPS_E_OK != rc)
{
/* _netif_nl_freeNetlinkSkb(ptr_nl_skb); */
}
}
}
}
return (rc);
}
NPS_ERROR_NO_T
netif_nl_rxSkb(
const UI32_T unit,
struct sk_buff *ptr_skb,
void *ptr_cookie)
{
NETIF_NL_CB_T *ptr_cb = &_netif_nl_cb;
NETIF_NL_RX_DST_NETLINK_T *ptr_nl_dest;
NPS_ERROR_NO_T rc;
ptr_nl_dest = (NETIF_NL_RX_DST_NETLINK_T *)ptr_cookie;
/* send the packet to netlink mcgroup */
rc = _netif_nl_forwardPkt(ptr_cb, ptr_nl_dest, ptr_skb);
/* need to free the original skb anyway */
osal_skb_free(ptr_skb);
return (rc);
}
NPS_ERROR_NO_T
netif_nl_init(void)
{
osal_memset(&_netif_nl_cb, 0x0, sizeof(NETIF_NL_CB_T));
return (NPS_E_OK);
}
NPS_ERROR_NO_T
netif_nl_deinit(void)
{
return (NPS_E_OK);
}

2
platform/nephos/nephos-modules/modules/src/netif_osal.c
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

2
platform/nephos/nephos-modules/modules/src/netif_perf.c
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

2
platform/nephos/nephos-modules/modules/src/osal_isymbol.c
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public

171
platform/nephos/nephos-modules/modules/src/osal_mdc.c
View File

@ -1,4 +1,4 @@
/* Copyright (C) 2019 Nephos, Inc.
/* Copyright (C) 2020 MediaTek, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public
@ -37,7 +37,7 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <nps_error.h>
#include <nps_types.h>
@ -685,6 +685,7 @@ _osal_mdc_removePciCallback(
iounmap(ptr_dev->ptr_mmio_virt_addr);
pci_release_region(pdev, OSAL_MDC_PCI_BAR0_OFFSET);
pci_disable_device(pdev);
_osal_mdc_cb.dev_num--;
}
static struct pci_device_id _osal_mdc_id_table[] =
@ -708,6 +709,7 @@ _osal_mdc_probePciDevice(void)
if (pci_register_driver(&_osal_mdc_pci_driver) < 0)
{
OSAL_MDC_ERR("Cannot find PCI device\n");
rc = NPS_E_OTHERS;
}
return (rc);
@ -720,6 +722,119 @@ _osal_mdc_removePciDevice(void)
return (NPS_E_OK);
}
static NPS_ERROR_NO_T
_osal_mdc_maskStatus(
const UI32_T unit)
{
struct pci_dev *ptr_ep_dev = _osal_mdc_cb.dev[unit].ptr_pci_dev;
struct pci_dev *ptr_rc_dev = ptr_ep_dev->bus->self;
int ext_cap = 0;
UI32_T data_32 = 0;
ext_cap = pci_find_ext_capability(ptr_rc_dev, 0x1);
if (0 != ext_cap)
{
/* Mask */
pci_read_config_dword(ptr_rc_dev, ext_cap + 0x8, &data_32);
data_32 |= 0x20;
pci_write_config_dword(ptr_rc_dev, ext_cap + 0x8, data_32);
}
return NPS_E_OK;
}
static NPS_ERROR_NO_T
_osal_mdc_clearStatus(
const UI32_T unit)
{
struct pci_dev *ptr_ep_dev = _osal_mdc_cb.dev[unit].ptr_pci_dev;
struct pci_dev *ptr_rc_dev = ptr_ep_dev->bus->self;
int ext_cap = 0;
UI32_T data_32 = 0;
ext_cap = pci_find_ext_capability(ptr_rc_dev, 0x1);
if (0 != ext_cap)
{
/* Clear */
pci_write_config_word(ptr_rc_dev, ptr_rc_dev->pcie_cap + 0xa, 0x04);
pci_write_config_word(ptr_rc_dev, ptr_rc_dev->pcie_cap + 0x12, 0x8000);
pci_write_config_dword(ptr_rc_dev, ext_cap + 0x4, 0x20);
/* UnMask */
pci_read_config_dword(ptr_rc_dev, ext_cap + 0x8, &data_32);
data_32 &= ~0x20;
pci_write_config_dword(ptr_rc_dev, ext_cap + 0x8, data_32);
}
return NPS_E_OK;
}
static NPS_ERROR_NO_T
_osal_mdc_savePciConfig(
const UI32_T unit)
{
struct pci_dev *ptr_dev = _osal_mdc_cb.dev[unit].ptr_pci_dev;
NPS_ERROR_NO_T rc = NPS_E_OK;
rc = _osal_mdc_maskStatus(unit);
if (NPS_E_OK == rc)
{
pci_save_state(ptr_dev);
}
return rc;
}
static NPS_ERROR_NO_T
_osal_mdc_restorePciConfig(
const UI32_T unit)
{
#define OSAL_MDC_PCI_PRESENT_POLL_CNT (100)
#define OSAL_MDC_PCI_PRESENT_POLL_INTERVAL (10) /* ms */
struct pci_dev *ptr_dev = _osal_mdc_cb.dev[unit].ptr_pci_dev;
UI32_T poll_cnt = 0;
NPS_ERROR_NO_T rc = NPS_E_OK;
/* standard: at least 100ms for link recovery */
msleep(100);
/* make sure pci device is there before restoring the config space */
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
while ((0 == pci_device_is_present(ptr_dev)) &&
#else
while ((0 == pci_dev_present(_osal_mdc_id_table)) &&
#endif
(poll_cnt < OSAL_MDC_PCI_PRESENT_POLL_CNT))
{
msleep(OSAL_MDC_PCI_PRESENT_POLL_INTERVAL);
poll_cnt++;
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
if (1 == pci_device_is_present(ptr_dev))
#else
if (1 == pci_dev_present(_osal_mdc_id_table))
#endif
{
pci_restore_state(ptr_dev);
rc = NPS_E_OK;
}
else
{
OSAL_MDC_ERR("detect pci device failed\n");
rc = NPS_E_OTHERS;
}
if (NPS_E_OK == rc)
{
rc = _osal_mdc_clearStatus(unit);
}
return (rc);
}
#endif /* End of AML_EN_I2C */
/* --------------------------------------------------------------------------- DMA */
@ -1415,6 +1530,20 @@ osal_mdc_invalidateCache(
return (NPS_E_OK);
}
NPS_ERROR_NO_T
osal_mdc_savePciConfig(
const UI32_T unit)
{
return _osal_mdc_savePciConfig(unit);
}
NPS_ERROR_NO_T
osal_mdc_restorePciConfig(
const UI32_T unit)
{
return _osal_mdc_restorePciConfig(unit);
}
#endif /* End of NPS_LINUX_KERNEL_MODE */
/* --------------------------------------------------------------------------- Interrupt */
@ -1458,7 +1587,7 @@ _osal_mdc_notifyUserProcess(
/* set the device bitmap. */
spin_lock_irqsave(&_osal_mdc_isr_dev_bitmap_lock, flags);
_osal_mdc_isr_dev_bitmap |= (1 << unit);
_osal_mdc_isr_dev_bitmap |= (1U << unit);
spin_unlock_irqrestore(&_osal_mdc_isr_dev_bitmap_lock, flags);
/* notify user process. */
@ -2045,12 +2174,12 @@ _osal_mdc_ioctl_connectIsrCallback(
{
NPS_ERROR_NO_T rc = NPS_E_OK;
if (0 == (_osal_mdc_isr_init_bitmap & (1 << unit)))
if (0 == (_osal_mdc_isr_init_bitmap & (1U << unit)))
{
rc = osal_mdc_connectIsr(unit, NULL, ptr_data);
if (NPS_E_OK == rc)
{
_osal_mdc_isr_init_bitmap |= (1 << unit);
_osal_mdc_isr_init_bitmap |= (1U << unit);
}
}
return (rc);
@ -2065,11 +2194,27 @@ _osal_mdc_ioctl_disconnectIsrCallback(
_osal_mdc_notifyUserProcess(unit);
osal_mdc_disconnectIsr(unit);
_osal_mdc_isr_init_bitmap &= ~(1 << unit);
_osal_mdc_isr_init_bitmap &= ~(1U << unit);
return (NPS_E_OK);
}
static NPS_ERROR_NO_T
_osal_mdc_ioctl_savePciConfigCallback(
const UI32_T unit,
void *ptr_data)
{
return _osal_mdc_savePciConfig(unit);
}
static NPS_ERROR_NO_T
_osal_mdc_ioctl_restorePciConfigCallback(
const UI32_T unit,
void *ptr_data)
{
return _osal_mdc_restorePciConfig(unit);
}
static NPS_ERROR_NO_T
_osal_mdc_registerIoctlCallback(
const OSAL_MDC_IOCTL_TYPE_T type,
@ -2126,6 +2271,12 @@ _osal_mdc_initIoctl(void)
_osal_mdc_registerIoctlCallback(OSAL_MDC_IOCTL_TYPE_MDC_DISCONNECT_ISR,
_osal_mdc_ioctl_disconnectIsrCallback);
_osal_mdc_registerIoctlCallback(OSAL_MDC_IOCTL_TYPE_MDC_SAVE_PCI_CONFIG,
_osal_mdc_ioctl_savePciConfigCallback);
_osal_mdc_registerIoctlCallback(OSAL_MDC_IOCTL_TYPE_MDC_RESTORE_PCI_CONFIG,
_osal_mdc_ioctl_restorePciConfigCallback);
return (NPS_E_OK);
}
@ -2221,6 +2372,8 @@ _osal_mdc_ioctl(
/* type: DEINIT_DEV
* DEINIT_RSRV_DMA_MEM
* DISCONNECT_ISR
* SAVE_PCI_CONFIG
* RESTORE_PCI_CONFIG
*/
if (NPS_E_OK != ptr_cb->callback[type](unit, (void *)ptr_temp_buf))
{
@ -2308,10 +2461,10 @@ osal_mdc_module_exit(void)
/* ref: _osal_mdc_ioctl_disconnectIsrCallback */
for (unit = 0; unit < NPS_CFG_MAXIMUM_CHIPS_PER_SYSTEM; unit++)
{
if (0 != (_osal_mdc_isr_init_bitmap & (1 << unit)))
if (0 != (_osal_mdc_isr_init_bitmap & (1U << unit)))
{
osal_mdc_disconnectIsr(unit);
_osal_mdc_isr_init_bitmap &= ~(1 << unit);
_osal_mdc_isr_init_bitmap &= ~(1U << unit);
}
}
@ -2355,5 +2508,5 @@ osal_mdc_module_exit(void)
module_init(osal_mdc_module_init);
module_exit(osal_mdc_module_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Nephos");
MODULE_AUTHOR("MediaTek");
MODULE_DESCRIPTION("SDK Kernel Module");