Add new device data for dx010 (Celestica-DX010-C32,Celestica-DX010-D48C8) (#3492)
* add config.bcm for hlx * modify config.bcm path for hlx * Delete hx4-cel-hbtn-48x1G+4x10G.config.bcm * add config.bcm and path * update led for cxp * Add new device data for dx010
This commit is contained in:
bbinxie
Ying Xie
parent
2fc617fcd9
commit
c74822a1a4
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{%- set default_topo = 't1' %}
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{%- include 'buffers_config.j2' %}
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{%- set default_cable = '5m' %}
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{%- set ports2cable = {
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'torrouter_server' : '300m',
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'leafrouter_torrouter' : '300m',
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'spinerouter_leafrouter' : '300m'
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}
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-%}
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{%- macro generate_port_lists(PORT_ALL) %}
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{# Generate list of ports #}
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{%- for port_idx in range(0,32) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
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{%- endfor %}
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{%- endmacro %}
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{%- macro generate_buffer_pool_and_profiles() %}
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"BUFFER_POOL": {
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"ingress_lossless_pool": {
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"size": "10875072",
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"type": "ingress",
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"mode": "dynamic",
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"xoff": "4194112"
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},
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"egress_lossy_pool": {
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"size": "9243812",
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"type": "egress",
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"mode": "dynamic"
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},
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"egress_lossless_pool": {
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"size": "15982720",
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"type": "egress",
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"mode": "static"
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}
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},
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"BUFFER_PROFILE": {
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"ingress_lossy_profile": {
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"pool":"[BUFFER_POOL|ingress_lossless_pool]",
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"size":"0",
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"dynamic_th":"3"
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},
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"egress_lossless_profile": {
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"pool":"[BUFFER_POOL|egress_lossless_pool]",
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"size":"1518",
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"static_th":"3995680"
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},
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"egress_lossy_profile": {
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"pool":"[BUFFER_POOL|egress_lossy_pool]",
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"size":"1518",
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"dynamic_th":"3"
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}
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},
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{%- endmacro %}
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{%- set default_cable = '40m' %}
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{%- set ports2cable = {
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'torrouter_server' : '300m',
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'leafrouter_torrouter' : '300m',
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'spinerouter_leafrouter' : '300m'
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}
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-%}
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{%- macro generate_port_lists(PORT_ALL) %}
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{# Generate list of ports #}
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{%- for port_idx in range(0,32) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
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{%- endfor %}
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{%- endmacro %}
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{%- macro generate_buffer_pool_and_profiles() %}
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"BUFFER_POOL": {
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"ingress_lossless_pool": {
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"size": "10875072",
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"type": "ingress",
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"mode": "dynamic",
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"xoff": "4194112"
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},
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"egress_lossy_pool": {
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"size": "9243812",
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"type": "egress",
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"mode": "dynamic"
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},
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"egress_lossless_pool": {
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"size": "15982720",
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"type": "egress",
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"mode": "static"
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}
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},
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"BUFFER_PROFILE": {
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"ingress_lossy_profile": {
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"pool":"[BUFFER_POOL|ingress_lossless_pool]",
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"size":"0",
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"dynamic_th":"3"
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},
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"egress_lossless_profile": {
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"pool":"[BUFFER_POOL|egress_lossless_pool]",
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"size":"1518",
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"static_th":"3995680"
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},
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"egress_lossy_profile": {
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"pool":"[BUFFER_POOL|egress_lossy_pool]",
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"size":"1518",
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"dynamic_th":"3"
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}
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},
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{%- endmacro %}
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# PG lossless profiles.
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# speed cable size xon xoff threshold xon_offset
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10000 5m 1248 2288 35776 -3 2288
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25000 5m 1248 2288 53248 -3 2288
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40000 5m 1248 2288 66560 -3 2288
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50000 5m 1248 2288 90272 -3 2288
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100000 5m 1248 2288 165568 -3 2288
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10000 40m 1248 2288 37024 -3 2288
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25000 40m 1248 2288 53248 -3 2288
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40000 40m 1248 2288 71552 -3 2288
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50000 40m 1248 2288 96096 -3 2288
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100000 40m 1248 2288 177632 -3 2288
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10000 300m 1248 2288 46176 -3 2288
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25000 300m 1248 2288 79040 -3 2288
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40000 300m 1248 2288 108160 -3 2288
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50000 300m 1248 2288 141856 -3 2288
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100000 300m 1248 2288 268736 -3 2288
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# name lanes alias speed index
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Ethernet0 65,66,67,68 etp1 100000 1
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Ethernet4 69,70,71,72 etp2 100000 2
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Ethernet8 73,74,75,76 etp3 100000 3
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Ethernet12 77,78,79,80 etp4 100000 4
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Ethernet16 33,34,35,36 etp5 100000 5
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Ethernet20 37,38,39,40 etp6 100000 6
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Ethernet24 41,42,43,44 etp7 100000 7
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Ethernet28 45,46,47,48 etp8 100000 8
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Ethernet32 49,50,51,52 etp9 100000 9
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Ethernet36 53,54,55,56 etp10 100000 10
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Ethernet40 57,58,59,60 etp11 100000 11
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Ethernet44 61,62,63,64 etp12 100000 12
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Ethernet48 81,82,83,84 etp13 100000 13
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Ethernet52 85,86,87,88 etp14 100000 14
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Ethernet56 89,90,91,92 etp15 100000 15
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Ethernet60 93,94,95,96 etp16 100000 16
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Ethernet64 97,98,99,100 etp17 100000 17
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Ethernet68 101,102,103,104 etp18 100000 18
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Ethernet72 105,106,107,108 etp19 100000 19
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Ethernet76 109,110,111,112 etp20 100000 20
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Ethernet80 1,2,3,4 etp21 100000 21
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Ethernet84 5,6,7,8 etp22 100000 22
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Ethernet88 9,10,11,12 etp23 100000 23
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Ethernet92 13,14,15,16 etp24 100000 24
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Ethernet96 17,18,19,20 etp25 100000 25
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Ethernet100 21,22,23,24 etp26 100000 26
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Ethernet104 25,26,27,28 etp27 100000 27
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Ethernet108 29,30,31,32 etp28 100000 28
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Ethernet112 113,114,115,116 etp29 100000 29
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Ethernet116 117,118,119,120 etp30 100000 30
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Ethernet120 121,122,123,124 etp31 100000 31
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Ethernet124 125,126,127,128 etp32 100000 32
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{%- include 'qos_config.j2' %}
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{# Get sai.profile based on switch_role #}
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{%- if DEVICE_METADATA is defined and DEVICE_METADATA['localhost'] is defined and DEVICE_METADATA['localhost']['type'] is defined -%}
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{%- set switch_role = DEVICE_METADATA['localhost']['type'] -%}
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{%- if switch_role.lower() == 'torrouter' %}
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{% set sai_profile_contents = 'SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-seastone-dx010-32x100G-t0.config.bcm' -%}
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{%- else %}
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{% set sai_profile_contents = 'SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-seastone-dx010-32x100G-t1.config.bcm' -%}
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{%- endif %}
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{%- else %}
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{% set sai_profile_contents = 'SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-seastone-dx010-32x100G-t1.config.bcm' -%}
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{%- endif %}
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{# Write the contents of sai_ profile_filename to sai.profile file #}
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{{ sai_profile_contents }}
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# Define default OS / SAL
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os=unix
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# all XPORTs to XE ports
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#pbmp_xport_xe=0x1fffffffe
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pbmp_xport_xe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
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pbmp_oversubscribe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
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# Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or
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# L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification.
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l2xmsg_mode=1
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# Memory table size configs
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l2_mem_entries=8192
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l3_mem_entries=8192
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l3_alpm_enable=2
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ipv6_lpm_128b_enable=1
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mmu_lossless=0
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###################################################################################
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# Celestica Customize for SeaStone
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###################################################################################
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#ext mdio frequency to 495/0x80/2(1.933Mhz) or 415/0x80/2(1.62MHz)
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# default is 40
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# Set external MDIO freq to 6.19MHz (495MHz) or 5.19MHz (415MHz)
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#* target_freq is core_clock_freq * DIVIDEND / DIVISOR / 2
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#
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rate_ext_mdio_divisor=0x80
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# use internal rom boot
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phy_ext_rom_boot=0
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#fpem_mem_entries=32768
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oversubscribe_mode=1
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#pbmp_xport_xe=0x3fd000000ff4000003fc000001fe
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dport_map_enable=1
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dport_map_port_68=1
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dport_map_port_72=5
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dport_map_port_76=9
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dport_map_port_80=13
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dport_map_port_34=17
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dport_map_port_38=21
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dport_map_port_42=25
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dport_map_port_46=29
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dport_map_port_50=33
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dport_map_port_54=37
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dport_map_port_58=41
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dport_map_port_62=45
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dport_map_port_84=49
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dport_map_port_88=53
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dport_map_port_92=57
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dport_map_port_96=61
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dport_map_port_102=65
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dport_map_port_106=69
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dport_map_port_110=73
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dport_map_port_114=77
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dport_map_port_1=81
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dport_map_port_5=85
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dport_map_port_9=89
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dport_map_port_13=93
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dport_map_port_17=97
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dport_map_port_21=101
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dport_map_port_25=105
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dport_map_port_29=109
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dport_map_port_118=113
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dport_map_port_122=117
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dport_map_port_126=121
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dport_map_port_130=125
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# port mapping
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portmap_68=65:100:4
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portmap_72=69:100:4
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portmap_76=73:100:4
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portmap_80=77:100:4
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portmap_34=33:100:4
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portmap_38=37:100:4
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portmap_42=41:100:4
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portmap_46=45:100:4
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portmap_50=49:100:4
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portmap_54=53:100:4
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portmap_58=57:100:4
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portmap_62=61:100:4
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portmap_84=81:100:4
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portmap_88=85:100:4
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portmap_92=89:100:4
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portmap_96=93:100:4
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portmap_102=97:100:4
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portmap_106=101:100:4
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portmap_110=105:100:4
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portmap_114=109:100:4
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portmap_1=1:100:4
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portmap_5=5:100:4
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portmap_9=9:100:4
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portmap_13=13:100:4
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portmap_17=17:100:4
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portmap_21=21:100:4
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portmap_25=25:100:4
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portmap_29=29:100:4
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portmap_118=113:100:4
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portmap_122=117:100:4
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portmap_126=121:100:4
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portmap_130=125:100:4
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#portmap_66=129:10
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#portmap_100=131:10
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#WC16
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xgxs_tx_lane_map_68=0x3201
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xgxs_rx_lane_map_68=0x2310
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#WC17
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xgxs_tx_lane_map_72=0x3201
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xgxs_rx_lane_map_72=0x2301
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#WC18
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xgxs_tx_lane_map_76=0x0132
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xgxs_rx_lane_map_76=0x0123
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#WC19
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xgxs_tx_lane_map_80=0x2031
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xgxs_rx_lane_map_80=0x1320
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#WC8
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xgxs_tx_lane_map_34=0x3021
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xgxs_rx_lane_map_34=0x0213
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#WC9
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xgxs_tx_lane_map_38=0x3210
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xgxs_rx_lane_map_38=0x1023
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#WC10
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xgxs_tx_lane_map_42=0x2310
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xgxs_rx_lane_map_42=0x3210
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#WC11
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xgxs_tx_lane_map_46=0x1032
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xgxs_rx_lane_map_46=0x1302
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#WC12
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xgxs_tx_lane_map_50=0x3201
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xgxs_rx_lane_map_50=0x0213
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#WC13
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xgxs_tx_lane_map_54=0x2301
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xgxs_rx_lane_map_54=0x2310
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#WC14
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xgxs_tx_lane_map_58=0x3201
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xgxs_rx_lane_map_58=0x0213
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#WC15
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xgxs_tx_lane_map_62=0x1302
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xgxs_rx_lane_map_62=0x2310
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#WC20
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xgxs_tx_lane_map_84=0x0213
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xgxs_rx_lane_map_84=0x2301
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#WC21
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xgxs_tx_lane_map_88=0x0132
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xgxs_rx_lane_map_88=0x3210
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#WC22
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xgxs_tx_lane_map_92=0x0132
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xgxs_rx_lane_map_92=0x2031
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#WC23
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xgxs_tx_lane_map_96=0x2031
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xgxs_rx_lane_map_96=0x3201
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#WC24
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xgxs_tx_lane_map_102=0x0132
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xgxs_rx_lane_map_102=0x2301
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#WC25
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xgxs_tx_lane_map_106=0x0132
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xgxs_rx_lane_map_106=0x3201
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#WC26
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xgxs_tx_lane_map_110=0x0132
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xgxs_rx_lane_map_110=0x2031
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#WC27
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xgxs_tx_lane_map_114=0x2031
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xgxs_rx_lane_map_114=0x2301
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#WC0
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xgxs_tx_lane_map_1=0x3210
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xgxs_rx_lane_map_1=0x3120
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#WC1
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xgxs_tx_lane_map_5=0x0132
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xgxs_rx_lane_map_5=0x1023
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#WC2
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xgxs_tx_lane_map_9=0x3201
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xgxs_rx_lane_map_9=0x3120
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#WC3
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xgxs_tx_lane_map_13=0x2031
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xgxs_rx_lane_map_13=0x1032
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#WC4
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xgxs_tx_lane_map_17=0x2310
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xgxs_rx_lane_map_17=0x3210
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#WC5
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xgxs_tx_lane_map_21=0x2301
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xgxs_rx_lane_map_21=0x3120
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#WC6
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xgxs_tx_lane_map_25=0x3201
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xgxs_rx_lane_map_25=0x0213
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#WC7
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xgxs_tx_lane_map_29=0x1302
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xgxs_rx_lane_map_29=0x1023
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#WC28
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xgxs_tx_lane_map_118=0x1320
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xgxs_rx_lane_map_118=0x1302
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#WC29
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xgxs_tx_lane_map_122=0x1032
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xgxs_rx_lane_map_122=0x1023
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#WC30
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xgxs_tx_lane_map_126=0x3120
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xgxs_rx_lane_map_126=0x3120
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#WC31
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xgxs_tx_lane_map_130=0x1302
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xgxs_rx_lane_map_130=0x2310
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#PN
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#WC16
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phy_xaui_tx_polarity_flip_68=0x0000
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phy_xaui_rx_polarity_flip_68=0x0000
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#WC17
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phy_xaui_tx_polarity_flip_72=0x000D
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phy_xaui_rx_polarity_flip_72=0x0002
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#WC18
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phy_xaui_tx_polarity_flip_76=0x000F
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||||
phy_xaui_rx_polarity_flip_76=0x0000
|
||||
|
||||
#WC19
|
||||
phy_xaui_tx_polarity_flip_80=0x000F
|
||||
phy_xaui_rx_polarity_flip_80=0x000F
|
||||
|
||||
|
||||
#WC8
|
||||
phy_xaui_tx_polarity_flip_34=0x000E
|
||||
phy_xaui_rx_polarity_flip_34=0x0000
|
||||
|
||||
#WC9
|
||||
phy_xaui_tx_polarity_flip_38=0x0008
|
||||
phy_xaui_rx_polarity_flip_38=0x0000
|
||||
|
||||
#WC10
|
||||
phy_xaui_tx_polarity_flip_42=0x000D
|
||||
phy_xaui_rx_polarity_flip_42=0x0000
|
||||
|
||||
#WC11
|
||||
phy_xaui_tx_polarity_flip_46=0x0000
|
||||
phy_xaui_rx_polarity_flip_46=0x0000
|
||||
|
||||
|
||||
#WC12
|
||||
phy_xaui_tx_polarity_flip_50=0x0002
|
||||
phy_xaui_rx_polarity_flip_50=0x0000
|
||||
|
||||
#WC13
|
||||
phy_xaui_tx_polarity_flip_54=0x0002
|
||||
phy_xaui_rx_polarity_flip_54=0x0000
|
||||
|
||||
#WC14
|
||||
phy_xaui_tx_polarity_flip_58=0x0000
|
||||
phy_xaui_rx_polarity_flip_58=0x0000
|
||||
|
||||
#WC15
|
||||
phy_xaui_tx_polarity_flip_62=0x000A
|
||||
phy_xaui_rx_polarity_flip_62=0x000F
|
||||
|
||||
|
||||
#WC20
|
||||
phy_xaui_tx_polarity_flip_84=0x0007
|
||||
phy_xaui_rx_polarity_flip_84=0x000E
|
||||
|
||||
#WC21
|
||||
phy_xaui_tx_polarity_flip_88=0x000D
|
||||
phy_xaui_rx_polarity_flip_88=0x000D
|
||||
|
||||
#WC22
|
||||
phy_xaui_tx_polarity_flip_92=0x000F
|
||||
phy_xaui_rx_polarity_flip_92=0x0008
|
||||
|
||||
#WC23
|
||||
phy_xaui_tx_polarity_flip_96=0x0005
|
||||
phy_xaui_rx_polarity_flip_96=0x0000
|
||||
|
||||
#WC24
|
||||
phy_xaui_tx_polarity_flip_102=0x0000
|
||||
phy_xaui_rx_polarity_flip_102=0x000F
|
||||
|
||||
#WC25
|
||||
phy_xaui_tx_polarity_flip_106=0x000F
|
||||
phy_xaui_rx_polarity_flip_106=0x0000
|
||||
|
||||
#WC26
|
||||
phy_xaui_tx_polarity_flip_110=0x000F
|
||||
phy_xaui_rx_polarity_flip_110=0x000F
|
||||
|
||||
#WC27
|
||||
phy_xaui_tx_polarity_flip_114=0x000F
|
||||
phy_xaui_rx_polarity_flip_114=0x0007
|
||||
|
||||
#WC0
|
||||
phy_xaui_tx_polarity_flip_1=0x0003
|
||||
phy_xaui_rx_polarity_flip_1=0x000F
|
||||
|
||||
#WC1
|
||||
phy_xaui_tx_polarity_flip_5=0x0007
|
||||
phy_xaui_rx_polarity_flip_5=0x0000
|
||||
|
||||
#WC2
|
||||
phy_xaui_tx_polarity_flip_9=0x0002
|
||||
phy_xaui_rx_polarity_flip_9=0x0008
|
||||
|
||||
#WC3
|
||||
phy_xaui_tx_polarity_flip_13=0x000F
|
||||
phy_xaui_rx_polarity_flip_13=0x0000
|
||||
|
||||
#WC4
|
||||
phy_xaui_tx_polarity_flip_17=0x0007
|
||||
phy_xaui_rx_polarity_flip_17=0x0000
|
||||
|
||||
#WC5
|
||||
phy_xaui_tx_polarity_flip_21=0x0000
|
||||
phy_xaui_rx_polarity_flip_21=0x0000
|
||||
|
||||
#WC6
|
||||
phy_xaui_tx_polarity_flip_25=0x0002
|
||||
phy_xaui_rx_polarity_flip_25=0x0005
|
||||
|
||||
#WC7
|
||||
phy_xaui_tx_polarity_flip_29=0x0002
|
||||
phy_xaui_rx_polarity_flip_29=0x0000
|
||||
|
||||
#WC28
|
||||
phy_xaui_tx_polarity_flip_118=0x000F
|
||||
phy_xaui_rx_polarity_flip_118=0x000F
|
||||
|
||||
#WC29
|
||||
phy_xaui_tx_polarity_flip_122=0x0004
|
||||
phy_xaui_rx_polarity_flip_122=0x0000
|
||||
|
||||
#WC30
|
||||
phy_xaui_tx_polarity_flip_126=0x000F
|
||||
phy_xaui_rx_polarity_flip_126=0x0000
|
||||
|
||||
#WC31
|
||||
phy_xaui_tx_polarity_flip_130=0x0006
|
||||
phy_xaui_rx_polarity_flip_130=0x0000
|
||||
|
||||
mmu_init_config="MSFT-TH-Tier0"
|
||||
@ -0,0 +1,696 @@
|
||||
# Define default OS / SAL
|
||||
os=unix
|
||||
|
||||
# all XPORTs to XE ports
|
||||
#pbmp_xport_xe=0x1fffffffe
|
||||
pbmp_xport_xe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
|
||||
pbmp_oversubscribe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
|
||||
|
||||
# Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or
|
||||
# L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification.
|
||||
l2xmsg_mode=1
|
||||
|
||||
# Memory table size configs
|
||||
l2_mem_entries=8192
|
||||
l3_mem_entries=8192
|
||||
l3_alpm_enable=2
|
||||
ipv6_lpm_128b_enable=1
|
||||
mmu_lossless=0
|
||||
|
||||
###################################################################################
|
||||
# Celestica Customize for SeaStone
|
||||
###################################################################################
|
||||
|
||||
#ext mdio frequency to 495/0x80/2(1.933Mhz) or 415/0x80/2(1.62MHz)
|
||||
# default is 40
|
||||
# Set external MDIO freq to 6.19MHz (495MHz) or 5.19MHz (415MHz)
|
||||
#* target_freq is core_clock_freq * DIVIDEND / DIVISOR / 2
|
||||
#
|
||||
rate_ext_mdio_divisor=0x80
|
||||
|
||||
# use internal rom boot
|
||||
phy_ext_rom_boot=0
|
||||
|
||||
#fpem_mem_entries=32768
|
||||
oversubscribe_mode=1
|
||||
#pbmp_xport_xe=0x3fd000000ff4000003fc000001fe
|
||||
|
||||
|
||||
dport_map_enable=1
|
||||
|
||||
dport_map_port_68=1
|
||||
dport_map_port_72=5
|
||||
dport_map_port_76=9
|
||||
dport_map_port_80=13
|
||||
dport_map_port_34=17
|
||||
dport_map_port_38=21
|
||||
dport_map_port_42=25
|
||||
dport_map_port_46=29
|
||||
dport_map_port_50=33
|
||||
dport_map_port_54=37
|
||||
dport_map_port_58=41
|
||||
dport_map_port_62=45
|
||||
dport_map_port_84=49
|
||||
dport_map_port_88=53
|
||||
dport_map_port_92=57
|
||||
dport_map_port_96=61
|
||||
dport_map_port_102=65
|
||||
dport_map_port_106=69
|
||||
dport_map_port_110=73
|
||||
dport_map_port_114=77
|
||||
dport_map_port_1=81
|
||||
dport_map_port_5=85
|
||||
dport_map_port_9=89
|
||||
dport_map_port_13=93
|
||||
dport_map_port_17=97
|
||||
dport_map_port_21=101
|
||||
dport_map_port_25=105
|
||||
dport_map_port_29=109
|
||||
dport_map_port_118=113
|
||||
dport_map_port_122=117
|
||||
dport_map_port_126=121
|
||||
dport_map_port_130=125
|
||||
|
||||
|
||||
# port mapping
|
||||
portmap_68=65:100:4
|
||||
portmap_72=69:100:4
|
||||
portmap_76=73:100:4
|
||||
portmap_80=77:100:4
|
||||
portmap_34=33:100:4
|
||||
portmap_38=37:100:4
|
||||
portmap_42=41:100:4
|
||||
portmap_46=45:100:4
|
||||
portmap_50=49:100:4
|
||||
portmap_54=53:100:4
|
||||
portmap_58=57:100:4
|
||||
portmap_62=61:100:4
|
||||
portmap_84=81:100:4
|
||||
portmap_88=85:100:4
|
||||
portmap_92=89:100:4
|
||||
portmap_96=93:100:4
|
||||
portmap_102=97:100:4
|
||||
portmap_106=101:100:4
|
||||
portmap_110=105:100:4
|
||||
portmap_114=109:100:4
|
||||
portmap_1=1:100:4
|
||||
portmap_5=5:100:4
|
||||
portmap_9=9:100:4
|
||||
portmap_13=13:100:4
|
||||
portmap_17=17:100:4
|
||||
portmap_21=21:100:4
|
||||
portmap_25=25:100:4
|
||||
portmap_29=29:100:4
|
||||
portmap_118=113:100:4
|
||||
portmap_122=117:100:4
|
||||
portmap_126=121:100:4
|
||||
portmap_130=125:100:4
|
||||
#portmap_66=129:10
|
||||
#portmap_100=131:10
|
||||
|
||||
#WC16
|
||||
xgxs_tx_lane_map_68=0x3201
|
||||
xgxs_rx_lane_map_68=0x2310
|
||||
|
||||
|
||||
#WC17
|
||||
xgxs_tx_lane_map_72=0x3201
|
||||
xgxs_rx_lane_map_72=0x2301
|
||||
|
||||
#WC18
|
||||
xgxs_tx_lane_map_76=0x0132
|
||||
xgxs_rx_lane_map_76=0x0123
|
||||
|
||||
#WC19
|
||||
xgxs_tx_lane_map_80=0x2031
|
||||
xgxs_rx_lane_map_80=0x1320
|
||||
|
||||
#WC8
|
||||
xgxs_tx_lane_map_34=0x3021
|
||||
xgxs_rx_lane_map_34=0x0213
|
||||
|
||||
#WC9
|
||||
xgxs_tx_lane_map_38=0x3210
|
||||
xgxs_rx_lane_map_38=0x1023
|
||||
|
||||
#WC10
|
||||
xgxs_tx_lane_map_42=0x2310
|
||||
xgxs_rx_lane_map_42=0x3210
|
||||
|
||||
#WC11
|
||||
xgxs_tx_lane_map_46=0x1032
|
||||
xgxs_rx_lane_map_46=0x1302
|
||||
|
||||
#WC12
|
||||
xgxs_tx_lane_map_50=0x3201
|
||||
xgxs_rx_lane_map_50=0x0213
|
||||
|
||||
|
||||
#WC13
|
||||
xgxs_tx_lane_map_54=0x2301
|
||||
xgxs_rx_lane_map_54=0x2310
|
||||
|
||||
#WC14
|
||||
xgxs_tx_lane_map_58=0x3201
|
||||
xgxs_rx_lane_map_58=0x0213
|
||||
|
||||
#WC15
|
||||
xgxs_tx_lane_map_62=0x1302
|
||||
xgxs_rx_lane_map_62=0x2310
|
||||
|
||||
#WC20
|
||||
xgxs_tx_lane_map_84=0x0213
|
||||
xgxs_rx_lane_map_84=0x2301
|
||||
|
||||
#WC21
|
||||
xgxs_tx_lane_map_88=0x0132
|
||||
xgxs_rx_lane_map_88=0x3210
|
||||
|
||||
#WC22
|
||||
xgxs_tx_lane_map_92=0x0132
|
||||
xgxs_rx_lane_map_92=0x2031
|
||||
|
||||
#WC23
|
||||
xgxs_tx_lane_map_96=0x2031
|
||||
xgxs_rx_lane_map_96=0x3201
|
||||
|
||||
#WC24
|
||||
xgxs_tx_lane_map_102=0x0132
|
||||
xgxs_rx_lane_map_102=0x2301
|
||||
|
||||
#WC25
|
||||
xgxs_tx_lane_map_106=0x0132
|
||||
xgxs_rx_lane_map_106=0x3201
|
||||
|
||||
#WC26
|
||||
xgxs_tx_lane_map_110=0x0132
|
||||
xgxs_rx_lane_map_110=0x2031
|
||||
|
||||
#WC27
|
||||
xgxs_tx_lane_map_114=0x2031
|
||||
xgxs_rx_lane_map_114=0x2301
|
||||
|
||||
|
||||
#WC0
|
||||
xgxs_tx_lane_map_1=0x3210
|
||||
xgxs_rx_lane_map_1=0x3120
|
||||
|
||||
#WC1
|
||||
xgxs_tx_lane_map_5=0x0132
|
||||
xgxs_rx_lane_map_5=0x1023
|
||||
|
||||
#WC2
|
||||
xgxs_tx_lane_map_9=0x3201
|
||||
xgxs_rx_lane_map_9=0x3120
|
||||
|
||||
#WC3
|
||||
xgxs_tx_lane_map_13=0x2031
|
||||
xgxs_rx_lane_map_13=0x1032
|
||||
|
||||
#WC4
|
||||
xgxs_tx_lane_map_17=0x2310
|
||||
xgxs_rx_lane_map_17=0x3210
|
||||
|
||||
#WC5
|
||||
xgxs_tx_lane_map_21=0x2301
|
||||
xgxs_rx_lane_map_21=0x3120
|
||||
|
||||
#WC6
|
||||
xgxs_tx_lane_map_25=0x3201
|
||||
xgxs_rx_lane_map_25=0x0213
|
||||
|
||||
#WC7
|
||||
xgxs_tx_lane_map_29=0x1302
|
||||
xgxs_rx_lane_map_29=0x1023
|
||||
|
||||
#WC28
|
||||
xgxs_tx_lane_map_118=0x1320
|
||||
xgxs_rx_lane_map_118=0x1302
|
||||
|
||||
#WC29
|
||||
xgxs_tx_lane_map_122=0x1032
|
||||
xgxs_rx_lane_map_122=0x1023
|
||||
|
||||
#WC30
|
||||
xgxs_tx_lane_map_126=0x3120
|
||||
xgxs_rx_lane_map_126=0x3120
|
||||
|
||||
#WC31
|
||||
xgxs_tx_lane_map_130=0x1302
|
||||
xgxs_rx_lane_map_130=0x2310
|
||||
|
||||
#PN
|
||||
|
||||
#WC16
|
||||
phy_xaui_tx_polarity_flip_68=0x0000
|
||||
phy_xaui_rx_polarity_flip_68=0x0000
|
||||
|
||||
#WC17
|
||||
phy_xaui_tx_polarity_flip_72=0x000D
|
||||
phy_xaui_rx_polarity_flip_72=0x0002
|
||||
|
||||
|
||||
#WC18
|
||||
phy_xaui_tx_polarity_flip_76=0x000F
|
||||
phy_xaui_rx_polarity_flip_76=0x0000
|
||||
|
||||
#WC19
|
||||
phy_xaui_tx_polarity_flip_80=0x000F
|
||||
phy_xaui_rx_polarity_flip_80=0x000F
|
||||
|
||||
|
||||
#WC8
|
||||
phy_xaui_tx_polarity_flip_34=0x000E
|
||||
phy_xaui_rx_polarity_flip_34=0x0000
|
||||
|
||||
#WC9
|
||||
phy_xaui_tx_polarity_flip_38=0x0008
|
||||
phy_xaui_rx_polarity_flip_38=0x0000
|
||||
|
||||
#WC10
|
||||
phy_xaui_tx_polarity_flip_42=0x000D
|
||||
phy_xaui_rx_polarity_flip_42=0x0000
|
||||
|
||||
#WC11
|
||||
phy_xaui_tx_polarity_flip_46=0x0000
|
||||
phy_xaui_rx_polarity_flip_46=0x0000
|
||||
|
||||
|
||||
#WC12
|
||||
phy_xaui_tx_polarity_flip_50=0x0002
|
||||
phy_xaui_rx_polarity_flip_50=0x0000
|
||||
|
||||
#WC13
|
||||
phy_xaui_tx_polarity_flip_54=0x0002
|
||||
phy_xaui_rx_polarity_flip_54=0x0000
|
||||
|
||||
#WC14
|
||||
phy_xaui_tx_polarity_flip_58=0x0000
|
||||
phy_xaui_rx_polarity_flip_58=0x0000
|
||||
|
||||
#WC15
|
||||
phy_xaui_tx_polarity_flip_62=0x000A
|
||||
phy_xaui_rx_polarity_flip_62=0x000F
|
||||
|
||||
|
||||
#WC20
|
||||
phy_xaui_tx_polarity_flip_84=0x0007
|
||||
phy_xaui_rx_polarity_flip_84=0x000E
|
||||
|
||||
#WC21
|
||||
phy_xaui_tx_polarity_flip_88=0x000D
|
||||
phy_xaui_rx_polarity_flip_88=0x000D
|
||||
|
||||
#WC22
|
||||
phy_xaui_tx_polarity_flip_92=0x000F
|
||||
phy_xaui_rx_polarity_flip_92=0x0008
|
||||
|
||||
#WC23
|
||||
phy_xaui_tx_polarity_flip_96=0x0005
|
||||
phy_xaui_rx_polarity_flip_96=0x0000
|
||||
|
||||
#WC24
|
||||
phy_xaui_tx_polarity_flip_102=0x0000
|
||||
phy_xaui_rx_polarity_flip_102=0x000F
|
||||
|
||||
#WC25
|
||||
phy_xaui_tx_polarity_flip_106=0x000F
|
||||
phy_xaui_rx_polarity_flip_106=0x0000
|
||||
|
||||
#WC26
|
||||
phy_xaui_tx_polarity_flip_110=0x000F
|
||||
phy_xaui_rx_polarity_flip_110=0x000F
|
||||
|
||||
#WC27
|
||||
phy_xaui_tx_polarity_flip_114=0x000F
|
||||
phy_xaui_rx_polarity_flip_114=0x0007
|
||||
|
||||
#WC0
|
||||
phy_xaui_tx_polarity_flip_1=0x0003
|
||||
phy_xaui_rx_polarity_flip_1=0x000F
|
||||
|
||||
#WC1
|
||||
phy_xaui_tx_polarity_flip_5=0x0007
|
||||
phy_xaui_rx_polarity_flip_5=0x0000
|
||||
|
||||
#WC2
|
||||
phy_xaui_tx_polarity_flip_9=0x0002
|
||||
phy_xaui_rx_polarity_flip_9=0x0008
|
||||
|
||||
#WC3
|
||||
phy_xaui_tx_polarity_flip_13=0x000F
|
||||
phy_xaui_rx_polarity_flip_13=0x0000
|
||||
|
||||
#WC4
|
||||
phy_xaui_tx_polarity_flip_17=0x0007
|
||||
phy_xaui_rx_polarity_flip_17=0x0000
|
||||
|
||||
#WC5
|
||||
phy_xaui_tx_polarity_flip_21=0x0000
|
||||
phy_xaui_rx_polarity_flip_21=0x0000
|
||||
|
||||
#WC6
|
||||
phy_xaui_tx_polarity_flip_25=0x0002
|
||||
phy_xaui_rx_polarity_flip_25=0x0005
|
||||
|
||||
#WC7
|
||||
phy_xaui_tx_polarity_flip_29=0x0002
|
||||
phy_xaui_rx_polarity_flip_29=0x0000
|
||||
|
||||
#WC28
|
||||
phy_xaui_tx_polarity_flip_118=0x000F
|
||||
phy_xaui_rx_polarity_flip_118=0x000F
|
||||
|
||||
#WC29
|
||||
phy_xaui_tx_polarity_flip_122=0x0004
|
||||
phy_xaui_rx_polarity_flip_122=0x0000
|
||||
|
||||
#WC30
|
||||
phy_xaui_tx_polarity_flip_126=0x000F
|
||||
phy_xaui_rx_polarity_flip_126=0x0000
|
||||
|
||||
#WC31
|
||||
phy_xaui_tx_polarity_flip_130=0x0006
|
||||
phy_xaui_rx_polarity_flip_130=0x0000
|
||||
|
||||
#ce0
|
||||
serdes_driver_current_lane0_68=0x0b
|
||||
serdes_driver_current_lane1_68=0x0b
|
||||
serdes_driver_current_lane2_68=0x0b
|
||||
serdes_driver_current_lane3_68=0x0b
|
||||
serdes_preemphasis_lane0_68=0x2d3f04
|
||||
serdes_preemphasis_lane1_68=0x2b4104
|
||||
serdes_preemphasis_lane2_68=0x2b4104
|
||||
serdes_preemphasis_lane3_68=0x2d3f04
|
||||
|
||||
#ce1
|
||||
serdes_driver_current_lane0_72=0x0b
|
||||
serdes_driver_current_lane1_72=0x0a
|
||||
serdes_driver_current_lane2_72=0x0a
|
||||
serdes_driver_current_lane3_72=0x0b
|
||||
serdes_preemphasis_lane0_72=0x2b4104
|
||||
serdes_preemphasis_lane1_72=0x294403
|
||||
serdes_preemphasis_lane2_72=0x294403
|
||||
serdes_preemphasis_lane3_72=0x2b4104
|
||||
|
||||
#ce2
|
||||
serdes_driver_current_lane0_76=0x0a
|
||||
serdes_driver_current_lane1_76=0x0a
|
||||
serdes_driver_current_lane2_76=0x0a
|
||||
serdes_driver_current_lane3_76=0x0a
|
||||
serdes_preemphasis_lane0_76=0x294403
|
||||
serdes_preemphasis_lane1_76=0x294403
|
||||
serdes_preemphasis_lane2_76=0x294403
|
||||
serdes_preemphasis_lane3_76=0x294403
|
||||
|
||||
#ce3
|
||||
serdes_driver_current_lane0_80=0x0a
|
||||
serdes_driver_current_lane1_80=0x0a
|
||||
serdes_driver_current_lane2_80=0x0a
|
||||
serdes_driver_current_lane3_80=0x0a
|
||||
serdes_preemphasis_lane0_80=0x254902
|
||||
serdes_preemphasis_lane1_80=0x254902
|
||||
serdes_preemphasis_lane2_80=0x294403
|
||||
serdes_preemphasis_lane3_80=0x294403
|
||||
|
||||
#ce4
|
||||
serdes_driver_current_lane0_34=0x0b
|
||||
serdes_driver_current_lane1_34=0x0b
|
||||
serdes_driver_current_lane2_34=0x0b
|
||||
serdes_driver_current_lane3_34=0x0b
|
||||
serdes_preemphasis_lane0_34=0x2b4104
|
||||
serdes_preemphasis_lane1_34=0x2d3f04
|
||||
serdes_preemphasis_lane2_34=0x2d3f04
|
||||
serdes_preemphasis_lane3_34=0x2b4104
|
||||
|
||||
#ce5
|
||||
serdes_driver_current_lane0_38=0x0a
|
||||
serdes_driver_current_lane1_38=0x0b
|
||||
serdes_driver_current_lane2_38=0x0b
|
||||
serdes_driver_current_lane3_38=0x0b
|
||||
serdes_preemphasis_lane0_38=0x294403
|
||||
serdes_preemphasis_lane1_38=0x2b4104
|
||||
serdes_preemphasis_lane2_38=0x2b4104
|
||||
serdes_preemphasis_lane3_38=0x2b4104
|
||||
|
||||
#ce6
|
||||
serdes_driver_current_lane0_42=0x0a
|
||||
serdes_driver_current_lane1_42=0x0b
|
||||
serdes_driver_current_lane2_42=0x0a
|
||||
serdes_driver_current_lane3_42=0x0a
|
||||
serdes_preemphasis_lane0_42=0x294403
|
||||
serdes_preemphasis_lane1_42=0x2b4104
|
||||
serdes_preemphasis_lane2_42=0x294403
|
||||
serdes_preemphasis_lane3_42=0x294403
|
||||
|
||||
#ce7
|
||||
serdes_driver_current_lane0_46=0x0a
|
||||
serdes_driver_current_lane1_46=0x0a
|
||||
serdes_driver_current_lane2_46=0x0a
|
||||
serdes_driver_current_lane3_46=0x0a
|
||||
serdes_preemphasis_lane0_46=0x254902
|
||||
serdes_preemphasis_lane1_46=0x294403
|
||||
serdes_preemphasis_lane2_46=0x254902
|
||||
serdes_preemphasis_lane3_46=0x294403
|
||||
|
||||
#ce8
|
||||
serdes_driver_current_lane0_50=0x0a
|
||||
serdes_driver_current_lane1_50=0x0a
|
||||
serdes_driver_current_lane2_50=0x0a
|
||||
serdes_driver_current_lane3_50=0x0a
|
||||
serdes_preemphasis_lane0_50=0x294403
|
||||
serdes_preemphasis_lane1_50=0x254902
|
||||
serdes_preemphasis_lane2_50=0x254902
|
||||
serdes_preemphasis_lane3_50=0x254902
|
||||
|
||||
#ce9
|
||||
serdes_driver_current_lane0_54=0x0a
|
||||
serdes_driver_current_lane1_54=0x09
|
||||
serdes_driver_current_lane2_54=0x0a
|
||||
serdes_driver_current_lane3_54=0x09
|
||||
serdes_preemphasis_lane0_54=0x254902
|
||||
serdes_preemphasis_lane1_54=0x244a02
|
||||
serdes_preemphasis_lane2_54=0x254902
|
||||
serdes_preemphasis_lane3_54=0x244a02
|
||||
|
||||
#ce10
|
||||
serdes_driver_current_lane0_58=0x0a
|
||||
serdes_driver_current_lane1_58=0x09
|
||||
serdes_driver_current_lane2_58=0x09
|
||||
serdes_driver_current_lane3_58=0x0a
|
||||
serdes_preemphasis_lane0_58=0x254902
|
||||
serdes_preemphasis_lane1_58=0x244a02
|
||||
serdes_preemphasis_lane2_58=0x244a02
|
||||
serdes_preemphasis_lane3_58=0x254902
|
||||
|
||||
#ce11
|
||||
serdes_driver_current_lane0_62=0x09
|
||||
serdes_driver_current_lane1_62=0x0a
|
||||
serdes_driver_current_lane2_62=0x09
|
||||
serdes_driver_current_lane3_62=0x09
|
||||
serdes_preemphasis_lane0_62=0x244a02
|
||||
serdes_preemphasis_lane1_62=0x254902
|
||||
serdes_preemphasis_lane2_62=0x244a02
|
||||
serdes_preemphasis_lane3_62=0x244a02
|
||||
|
||||
#ce12
|
||||
serdes_driver_current_lane0_84=0x09
|
||||
serdes_driver_current_lane1_84=0x09
|
||||
serdes_driver_current_lane2_84=0x09
|
||||
serdes_driver_current_lane3_84=0x09
|
||||
serdes_preemphasis_lane0_84=0x204e02
|
||||
serdes_preemphasis_lane1_84=0x204e02
|
||||
serdes_preemphasis_lane2_84=0x204e02
|
||||
serdes_preemphasis_lane3_84=0x204e02
|
||||
|
||||
#ce13
|
||||
serdes_driver_current_lane0_88=0x09
|
||||
serdes_driver_current_lane1_88=0x08
|
||||
serdes_driver_current_lane2_88=0x08
|
||||
serdes_driver_current_lane3_88=0x09
|
||||
serdes_preemphasis_lane0_88=0x204e02
|
||||
serdes_preemphasis_lane1_88=0x1d5102
|
||||
serdes_preemphasis_lane2_88=0x1d5102
|
||||
serdes_preemphasis_lane3_88=0x204e02
|
||||
|
||||
#ce14
|
||||
serdes_driver_current_lane0_92=0x09
|
||||
serdes_driver_current_lane1_92=0x08
|
||||
serdes_driver_current_lane2_92=0x08
|
||||
serdes_driver_current_lane3_92=0x09
|
||||
serdes_preemphasis_lane0_92=0x204e02
|
||||
serdes_preemphasis_lane1_92=0x1d5102
|
||||
serdes_preemphasis_lane2_92=0x1d5102
|
||||
serdes_preemphasis_lane3_92=0x204e02
|
||||
|
||||
#ce15
|
||||
serdes_driver_current_lane0_96=0x08
|
||||
serdes_driver_current_lane1_96=0x08
|
||||
serdes_driver_current_lane2_96=0x09
|
||||
serdes_driver_current_lane3_96=0x09
|
||||
serdes_preemphasis_lane0_96=0x1d5102
|
||||
serdes_preemphasis_lane1_96=0x1d5102
|
||||
serdes_preemphasis_lane2_96=0x204e02
|
||||
serdes_preemphasis_lane3_96=0x204e02
|
||||
|
||||
#ce16
|
||||
serdes_driver_current_lane0_102=0x09
|
||||
serdes_driver_current_lane1_102=0x08
|
||||
serdes_driver_current_lane2_102=0x08
|
||||
serdes_driver_current_lane3_102=0x09
|
||||
serdes_preemphasis_lane0_102=0x204e02
|
||||
serdes_preemphasis_lane1_102=0x1d5102
|
||||
serdes_preemphasis_lane2_102=0x1d5102
|
||||
serdes_preemphasis_lane3_102=0x224c02
|
||||
|
||||
#ce17
|
||||
serdes_driver_current_lane0_106=0x09
|
||||
serdes_driver_current_lane1_106=0x08
|
||||
serdes_driver_current_lane2_106=0x08
|
||||
serdes_driver_current_lane3_106=0x09
|
||||
serdes_preemphasis_lane0_106=0x204e02
|
||||
serdes_preemphasis_lane1_106=0x1d5102
|
||||
serdes_preemphasis_lane2_106=0x1d5102
|
||||
serdes_preemphasis_lane3_106=0x204e02
|
||||
|
||||
#ce18
|
||||
serdes_driver_current_lane0_110=0x09
|
||||
serdes_driver_current_lane1_110=0x08
|
||||
serdes_driver_current_lane2_110=0x08
|
||||
serdes_driver_current_lane3_110=0x09
|
||||
serdes_preemphasis_lane0_110=0x204e02
|
||||
serdes_preemphasis_lane1_110=0x1d5102
|
||||
serdes_preemphasis_lane2_110=0x1d5102
|
||||
serdes_preemphasis_lane3_110=0x204e02
|
||||
|
||||
#ce19
|
||||
serdes_driver_current_lane0_114=0x09
|
||||
serdes_driver_current_lane1_114=0x08
|
||||
serdes_driver_current_lane2_114=0x09
|
||||
serdes_driver_current_lane3_114=0x09
|
||||
serdes_preemphasis_lane0_114=0x204e02
|
||||
serdes_preemphasis_lane1_114=0x1d5102
|
||||
serdes_preemphasis_lane2_114=0x224c02
|
||||
serdes_preemphasis_lane3_114=0x224c02
|
||||
|
||||
#ce20
|
||||
serdes_driver_current_lane0_1=0x09
|
||||
serdes_driver_current_lane1_1=0x0a
|
||||
serdes_driver_current_lane2_1=0x09
|
||||
serdes_driver_current_lane3_1=0x0a
|
||||
serdes_preemphasis_lane0_1=0x244a02
|
||||
serdes_preemphasis_lane1_1=0x254902
|
||||
serdes_preemphasis_lane2_1=0x244a02
|
||||
serdes_preemphasis_lane3_1=0x254902
|
||||
|
||||
#ce21
|
||||
serdes_driver_current_lane0_5=0x09
|
||||
serdes_driver_current_lane1_5=0x09
|
||||
serdes_driver_current_lane2_5=0x09
|
||||
serdes_driver_current_lane3_5=0x0a
|
||||
serdes_preemphasis_lane0_5=0x244a02
|
||||
serdes_preemphasis_lane1_5=0x244a02
|
||||
serdes_preemphasis_lane2_5=0x244a02
|
||||
serdes_preemphasis_lane3_5=0x254902
|
||||
|
||||
#ce22
|
||||
serdes_driver_current_lane0_9=0x0a
|
||||
serdes_driver_current_lane1_9=0x0a
|
||||
serdes_driver_current_lane2_9=0x0a
|
||||
serdes_driver_current_lane3_9=0x0a
|
||||
serdes_preemphasis_lane0_9=0x254902
|
||||
serdes_preemphasis_lane1_9=0x254902
|
||||
serdes_preemphasis_lane2_9=0x254902
|
||||
serdes_preemphasis_lane3_9=0x294403
|
||||
|
||||
#ce23
|
||||
serdes_driver_current_lane0_13=0x09
|
||||
serdes_driver_current_lane1_13=0x0a
|
||||
serdes_driver_current_lane2_13=0x0a
|
||||
serdes_driver_current_lane3_13=0x0a
|
||||
serdes_preemphasis_lane0_13=0x244a02
|
||||
serdes_preemphasis_lane1_13=0x254902
|
||||
serdes_preemphasis_lane2_13=0x294403
|
||||
serdes_preemphasis_lane3_13=0x294403
|
||||
|
||||
#ce24
|
||||
serdes_driver_current_lane0_17=0x0a
|
||||
serdes_driver_current_lane1_17=0x0a
|
||||
serdes_driver_current_lane2_17=0x0a
|
||||
serdes_driver_current_lane3_17=0x0a
|
||||
serdes_preemphasis_lane0_17=0x254902
|
||||
serdes_preemphasis_lane1_17=0x294403
|
||||
serdes_preemphasis_lane2_17=0x294403
|
||||
serdes_preemphasis_lane3_17=0x294403
|
||||
|
||||
#ce25
|
||||
serdes_driver_current_lane0_21=0x0a
|
||||
serdes_driver_current_lane1_21=0x0a
|
||||
serdes_driver_current_lane2_21=0x0a
|
||||
serdes_driver_current_lane3_21=0x0a
|
||||
serdes_preemphasis_lane0_21=0x294403
|
||||
serdes_preemphasis_lane1_21=0x294403
|
||||
serdes_preemphasis_lane2_21=0x294403
|
||||
serdes_preemphasis_lane3_21=0x254902
|
||||
|
||||
#ce26
|
||||
serdes_driver_current_lane0_25=0x0b
|
||||
serdes_driver_current_lane1_25=0x0b
|
||||
serdes_driver_current_lane2_25=0x0b
|
||||
serdes_driver_current_lane3_25=0x0b
|
||||
serdes_preemphasis_lane0_25=0x2b4104
|
||||
serdes_preemphasis_lane1_25=0x2b4104
|
||||
serdes_preemphasis_lane2_25=0x2b4104
|
||||
serdes_preemphasis_lane3_25=0x2d3f04
|
||||
|
||||
#ce27
|
||||
serdes_driver_current_lane0_29=0x0b
|
||||
serdes_driver_current_lane1_29=0x0b
|
||||
serdes_driver_current_lane2_29=0x0b
|
||||
serdes_driver_current_lane3_29=0x0a
|
||||
serdes_preemphasis_lane0_29=0x2d3f04
|
||||
serdes_preemphasis_lane1_29=0x2d3f04
|
||||
serdes_preemphasis_lane2_29=0x2b4104
|
||||
serdes_preemphasis_lane3_29=0x294403
|
||||
|
||||
#ce28
|
||||
serdes_driver_current_lane0_118=0x0a
|
||||
serdes_driver_current_lane1_118=0x0a
|
||||
serdes_driver_current_lane2_118=0x0a
|
||||
serdes_driver_current_lane3_118=0x0a
|
||||
serdes_preemphasis_lane0_118=0x254902
|
||||
serdes_preemphasis_lane1_118=0x294403
|
||||
serdes_preemphasis_lane2_118=0x294403
|
||||
serdes_preemphasis_lane3_118=0x254902
|
||||
|
||||
#ce29
|
||||
serdes_driver_current_lane0_122=0x0a
|
||||
serdes_driver_current_lane1_122=0x0a
|
||||
serdes_driver_current_lane2_122=0x0a
|
||||
serdes_driver_current_lane3_122=0x0a
|
||||
serdes_preemphasis_lane0_122=0x294403
|
||||
serdes_preemphasis_lane1_122=0x294403
|
||||
serdes_preemphasis_lane2_122=0x294403
|
||||
serdes_preemphasis_lane3_122=0x294403
|
||||
|
||||
#ce30
|
||||
serdes_driver_current_lane0_126=0x0a
|
||||
serdes_driver_current_lane1_126=0x0a
|
||||
serdes_driver_current_lane2_126=0x0b
|
||||
serdes_driver_current_lane3_126=0x0b
|
||||
serdes_preemphasis_lane0_126=0x294403
|
||||
serdes_preemphasis_lane1_126=0x294403
|
||||
serdes_preemphasis_lane2_126=0x2b4104
|
||||
serdes_preemphasis_lane3_126=0x2b4104
|
||||
|
||||
#ce31
|
||||
serdes_driver_current_lane0_130=0x0b
|
||||
serdes_driver_current_lane1_130=0x0b
|
||||
serdes_driver_current_lane2_130=0x0b
|
||||
serdes_driver_current_lane3_130=0x0b
|
||||
serdes_preemphasis_lane0_130=0x2d3f04
|
||||
serdes_preemphasis_lane1_130=0x2d3f04
|
||||
serdes_preemphasis_lane2_130=0x2b4104
|
||||
serdes_preemphasis_lane3_130=0x2b4104
|
||||
|
||||
mmu_init_config="MSFT-TH-Tier1"
|
||||
@ -0,0 +1,2 @@
|
||||
{%- set default_topo = 't0' %}
|
||||
{%- include 'buffers_config.j2' %}
|
||||
@ -0,0 +1,69 @@
|
||||
|
||||
{%- set default_cable = '5m' %}
|
||||
|
||||
{%- set ports2cable = {
|
||||
'torrouter_server' : '300m',
|
||||
'leafrouter_torrouter' : '300m',
|
||||
'spinerouter_leafrouter' : '300m'
|
||||
}
|
||||
-%}
|
||||
|
||||
{%- macro generate_port_lists(PORT_ALL) %}
|
||||
{# Generate list of ports #}
|
||||
{%- for port_idx in range(0,9) %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4 + 2)) %}{%- endif %}
|
||||
{%- endfor %}
|
||||
{%- for port_idx in range(14,17) %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4 + 2)) %}{%- endif %}
|
||||
{%- endfor %}
|
||||
{%- for port_idx in range(22,31) %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4 + 2)) %}{%- endif %}
|
||||
{%- endfor %}
|
||||
{%- for port_idx in range(10,13) %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
|
||||
{%- endfor %}
|
||||
{%- for port_idx in range(18,21) %}
|
||||
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
|
||||
{%- endfor %}
|
||||
{%- endmacro %}
|
||||
|
||||
{%- macro generate_buffer_pool_and_profiles() %}
|
||||
"BUFFER_POOL": {
|
||||
"ingress_lossless_pool": {
|
||||
"size": "10875072",
|
||||
"type": "ingress",
|
||||
"mode": "dynamic",
|
||||
"xoff": "4194112"
|
||||
},
|
||||
"egress_lossy_pool": {
|
||||
"size": "9243812",
|
||||
"type": "egress",
|
||||
"mode": "dynamic"
|
||||
},
|
||||
"egress_lossless_pool": {
|
||||
"size": "15982720",
|
||||
"type": "egress",
|
||||
"mode": "static"
|
||||
}
|
||||
},
|
||||
"BUFFER_PROFILE": {
|
||||
"ingress_lossy_profile": {
|
||||
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
|
||||
"size":"0",
|
||||
"dynamic_th":"3"
|
||||
},
|
||||
"egress_lossless_profile": {
|
||||
"pool":"[BUFFER_POOL|egress_lossless_pool]",
|
||||
"size":"1518",
|
||||
"static_th":"3995680"
|
||||
},
|
||||
"egress_lossy_profile": {
|
||||
"pool":"[BUFFER_POOL|egress_lossy_pool]",
|
||||
"size":"1518",
|
||||
"dynamic_th":"3"
|
||||
}
|
||||
},
|
||||
{%- endmacro %}
|
||||
@ -0,0 +1,17 @@
|
||||
# PG lossless profiles.
|
||||
# speed cable size xon xoff threshold xon_offset
|
||||
10000 5m 1248 2288 35776 -3 2288
|
||||
25000 5m 1248 2288 53248 -3 2288
|
||||
40000 5m 1248 2288 66560 -3 2288
|
||||
50000 5m 1248 2288 90272 -3 2288
|
||||
100000 5m 1248 2288 165568 -3 2288
|
||||
10000 40m 1248 2288 37024 -3 2288
|
||||
25000 40m 1248 2288 53248 -3 2288
|
||||
40000 40m 1248 2288 71552 -3 2288
|
||||
50000 40m 1248 2288 96096 -3 2288
|
||||
100000 40m 1248 2288 177632 -3 2288
|
||||
10000 300m 1248 2288 46176 -3 2288
|
||||
25000 300m 1248 2288 79040 -3 2288
|
||||
40000 300m 1248 2288 108160 -3 2288
|
||||
50000 300m 1248 2288 141856 -3 2288
|
||||
100000 300m 1248 2288 268736 -3 2288
|
||||
@ -0,0 +1,57 @@
|
||||
# name lanes alias speed index
|
||||
Ethernet0 65,66 etp1a 50000 1
|
||||
Ethernet2 67,68 etp1b 50000 1
|
||||
Ethernet4 69,70 etp2a 50000 2
|
||||
Ethernet6 71,72 etp2b 50000 2
|
||||
Ethernet8 73,74 etp3a 50000 3
|
||||
Ethernet10 75,76 etp3b 50000 3
|
||||
Ethernet12 77,78 etp4a 50000 4
|
||||
Ethernet14 79,80 etp4b 50000 4
|
||||
Ethernet16 33,34 etp5a 50000 5
|
||||
Ethernet18 35,36 etp5b 50000 5
|
||||
Ethernet20 37,38 etp6a 50000 6
|
||||
Ethernet22 39,40 etp6b 50000 6
|
||||
Ethernet24 41,42 etp7a 50000 7
|
||||
Ethernet26 43,44 etp7b 50000 7
|
||||
Ethernet28 45,46 etp8a 50000 8
|
||||
Ethernet30 47,48 etp8b 50000 8
|
||||
Ethernet32 49,50 etp9a 50000 9
|
||||
Ethernet34 51,52 etp9b 50000 9
|
||||
Ethernet36 53,54 etp10a 50000 10
|
||||
Ethernet38 55,56 etp10b 50000 10
|
||||
Ethernet40 57,58,59,60 etp11 100000 11
|
||||
Ethernet44 61,62,63,64 etp12 100000 12
|
||||
Ethernet48 81,82,83,84 etp13 100000 13
|
||||
Ethernet52 85,86,87,88 etp14 100000 14
|
||||
Ethernet56 89,90 etp15a 50000 15
|
||||
Ethernet58 91,92 etp15b 50000 15
|
||||
Ethernet60 93,94 etp16a 50000 16
|
||||
Ethernet62 95,96 etp16b 50000 16
|
||||
Ethernet64 97,98 etp17a 50000 17
|
||||
Ethernet66 99,100 etp17b 50000 17
|
||||
Ethernet68 101,102 etp18a 50000 18
|
||||
Ethernet70 103,104 etp18b 50000 18
|
||||
Ethernet72 105,106,107,108 etp19 100000 19
|
||||
Ethernet76 109,110,111,112 etp20 100000 20
|
||||
Ethernet80 1,2,3,4 etp21 100000 21
|
||||
Ethernet84 5,6,7,8 etp22 100000 22
|
||||
Ethernet88 9,10 etp23a 50000 23
|
||||
Ethernet90 11,12 etp23b 50000 23
|
||||
Ethernet92 13,14 etp24a 50000 24
|
||||
Ethernet94 15,16 etp24b 50000 24
|
||||
Ethernet96 17,18 etp25a 50000 25
|
||||
Ethernet98 19,20 etp25b 50000 25
|
||||
Ethernet100 21,22 etp26a 50000 26
|
||||
Ethernet102 23,24 etp26b 50000 26
|
||||
Ethernet104 25,26 etp27a 50000 27
|
||||
Ethernet106 27,28 etp27b 50000 27
|
||||
Ethernet108 29,30 etp28a 50000 28
|
||||
Ethernet110 31,32 etp28b 50000 28
|
||||
Ethernet112 113,114 etp29a 50000 29
|
||||
Ethernet114 115,116 etp29b 50000 29
|
||||
Ethernet116 117,118 etp30a 50000 30
|
||||
Ethernet118 119,120 etp30b 50000 30
|
||||
Ethernet120 121,122 etp31a 50000 31
|
||||
Ethernet122 123,124 etp31b 50000 31
|
||||
Ethernet124 125,126 etp32a 50000 32
|
||||
Ethernet126 127,128 etp32b 50000 32
|
||||
@ -0,0 +1 @@
|
||||
{%- include 'qos_config.j2' %}
|
||||
@ -0,0 +1 @@
|
||||
SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-seastone-dx010-48x50G+8x100G.config.bcm
|
||||
@ -0,0 +1,648 @@
|
||||
os=unix
|
||||
l2xmsg_mode=1
|
||||
parity_enable=0
|
||||
rate_ext_mdio_divisor=0x80
|
||||
phy_ext_rom_boot=0
|
||||
fpem_mem_entries=32768
|
||||
l2xmsg_mode=1
|
||||
oversubscribe_mode=1
|
||||
pbmp_xport_xe=0xcccc44cc33113333044cccccc66666622
|
||||
|
||||
|
||||
dport_map_enable=1
|
||||
dport_map_port_68=1
|
||||
dport_map_port_69=2
|
||||
|
||||
dport_map_port_72=5
|
||||
dport_map_port_73=6
|
||||
|
||||
dport_map_port_76=9
|
||||
dport_map_port_77=10
|
||||
|
||||
dport_map_port_80=13
|
||||
dport_map_port_81=14
|
||||
|
||||
dport_map_port_34=17
|
||||
dport_map_port_35=18
|
||||
|
||||
dport_map_port_38=21
|
||||
dport_map_port_39=22
|
||||
|
||||
dport_map_port_42=25
|
||||
dport_map_port_43=26
|
||||
|
||||
dport_map_port_46=29
|
||||
dport_map_port_47=30
|
||||
|
||||
dport_map_port_50=33
|
||||
dport_map_port_51=34
|
||||
|
||||
dport_map_port_54=37
|
||||
dport_map_port_55=38
|
||||
|
||||
dport_map_port_58=41
|
||||
|
||||
dport_map_port_62=45
|
||||
|
||||
dport_map_port_84=49
|
||||
|
||||
dport_map_port_88=53
|
||||
|
||||
dport_map_port_92=57
|
||||
dport_map_port_93=58
|
||||
|
||||
dport_map_port_96=61
|
||||
dport_map_port_97=62
|
||||
|
||||
dport_map_port_102=65
|
||||
dport_map_port_103=66
|
||||
|
||||
dport_map_port_106=69
|
||||
dport_map_port_107=70
|
||||
|
||||
dport_map_port_110=73
|
||||
|
||||
dport_map_port_114=77
|
||||
|
||||
dport_map_port_1=81
|
||||
|
||||
dport_map_port_5=85
|
||||
|
||||
dport_map_port_9=89
|
||||
dport_map_port_10=90
|
||||
|
||||
dport_map_port_13=93
|
||||
dport_map_port_14=94
|
||||
|
||||
dport_map_port_17=97
|
||||
dport_map_port_18=98
|
||||
|
||||
dport_map_port_21=101
|
||||
dport_map_port_22=102
|
||||
|
||||
dport_map_port_25=105
|
||||
dport_map_port_26=106
|
||||
|
||||
dport_map_port_29=109
|
||||
dport_map_port_30=110
|
||||
|
||||
dport_map_port_118=113
|
||||
dport_map_port_119=114
|
||||
|
||||
dport_map_port_122=117
|
||||
dport_map_port_123=118
|
||||
|
||||
dport_map_port_126=121
|
||||
dport_map_port_127=122
|
||||
|
||||
dport_map_port_130=125
|
||||
dport_map_port_131=126
|
||||
|
||||
|
||||
# port mapping
|
||||
portmap_68=65:50:2
|
||||
portmap_69=67:50:2
|
||||
|
||||
portmap_72=69:50:2
|
||||
portmap_73=71:50:2
|
||||
|
||||
portmap_76=73:50:2
|
||||
portmap_77=75:50:2
|
||||
|
||||
portmap_80=77:50:2
|
||||
portmap_81=79:50:2
|
||||
|
||||
portmap_34=33:50:2
|
||||
portmap_35=35:50:2
|
||||
|
||||
portmap_38=37:50:2
|
||||
portmap_39=39:50:2
|
||||
|
||||
portmap_42=41:50:2
|
||||
portmap_43=43:50:2
|
||||
|
||||
portmap_46=45:50:2
|
||||
portmap_47=47:50:2
|
||||
|
||||
portmap_50=49:50:2
|
||||
portmap_51=51:50:2
|
||||
|
||||
portmap_54=53:50:2
|
||||
portmap_55=55:50:2
|
||||
|
||||
portmap_58=57:100:4
|
||||
|
||||
portmap_62=61:100:4
|
||||
|
||||
portmap_84=81:100:4
|
||||
|
||||
portmap_88=85:100:4
|
||||
|
||||
portmap_92=89:50:2
|
||||
portmap_93=91:50:2
|
||||
|
||||
portmap_96=93:50:2
|
||||
portmap_97=95:50:2
|
||||
|
||||
portmap_102=97:50:2
|
||||
portmap_103=99:50:2
|
||||
|
||||
portmap_106=101:50:2
|
||||
portmap_107=103:50:2
|
||||
|
||||
portmap_110=105:100:4
|
||||
|
||||
portmap_114=109:100:4
|
||||
|
||||
portmap_1=1:100:4
|
||||
|
||||
portmap_5=5:100:4
|
||||
|
||||
portmap_9=9:50:2
|
||||
portmap_10=11:50:2
|
||||
|
||||
portmap_13=13:50:2
|
||||
portmap_14=15:50:2
|
||||
|
||||
portmap_17=17:50:2
|
||||
portmap_18=19:50:2
|
||||
|
||||
portmap_21=21:50:2
|
||||
portmap_22=23:50:2
|
||||
|
||||
portmap_25=25:50:2
|
||||
portmap_26=27:50:2
|
||||
|
||||
portmap_29=29:50:2
|
||||
portmap_30=31:50:2
|
||||
|
||||
portmap_118=113:50:2
|
||||
portmap_119=115:50:2
|
||||
|
||||
portmap_122=117:50:2
|
||||
portmap_123=119:50:2
|
||||
|
||||
portmap_126=121:50:2
|
||||
portmap_127=123:50:2
|
||||
|
||||
portmap_130=125:50:2
|
||||
portmap_131=127:50:2
|
||||
|
||||
|
||||
#WC16
|
||||
xgxs_tx_lane_map_68=0x1023
|
||||
xgxs_rx_lane_map_68=0x0132
|
||||
xgxs_tx_lane_map_69=0x1023
|
||||
xgxs_rx_lane_map_69=0x0132
|
||||
|
||||
|
||||
#WC17
|
||||
xgxs_tx_lane_map_72=0x1023
|
||||
xgxs_rx_lane_map_72=0x1032
|
||||
xgxs_tx_lane_map_73=0x1023
|
||||
xgxs_rx_lane_map_73=0x1032
|
||||
|
||||
#WC18
|
||||
xgxs_tx_lane_map_76=0x2310
|
||||
xgxs_rx_lane_map_76=0x3210
|
||||
xgxs_tx_lane_map_77=0x2310
|
||||
xgxs_rx_lane_map_77=0x3210
|
||||
|
||||
#WC19
|
||||
xgxs_tx_lane_map_80=0x1302
|
||||
xgxs_rx_lane_map_80=0x0231
|
||||
xgxs_tx_lane_map_81=0x1302
|
||||
xgxs_rx_lane_map_81=0x0231
|
||||
#WC8
|
||||
xgxs_tx_lane_map_34=0x1203
|
||||
xgxs_rx_lane_map_34=0x3120
|
||||
xgxs_tx_lane_map_35=0x1203
|
||||
xgxs_rx_lane_map_35=0x3120
|
||||
|
||||
#WC9
|
||||
xgxs_tx_lane_map_38=0x0123
|
||||
xgxs_rx_lane_map_38=0x3201
|
||||
xgxs_tx_lane_map_39=0x0123
|
||||
xgxs_rx_lane_map_39=0x3201
|
||||
|
||||
#WC10
|
||||
xgxs_tx_lane_map_42=0x0132
|
||||
xgxs_rx_lane_map_42=0x0123
|
||||
xgxs_tx_lane_map_43=0x0132
|
||||
xgxs_rx_lane_map_43=0x0123
|
||||
|
||||
#WC11
|
||||
xgxs_tx_lane_map_46=0x2301
|
||||
xgxs_rx_lane_map_46=0x2031
|
||||
xgxs_tx_lane_map_47=0x2301
|
||||
xgxs_rx_lane_map_47=0x2031
|
||||
|
||||
#WC12
|
||||
xgxs_tx_lane_map_50=0x1032
|
||||
xgxs_rx_lane_map_50=0x3120
|
||||
xgxs_tx_lane_map_51=0x1032
|
||||
xgxs_rx_lane_map_51=0x3120
|
||||
|
||||
|
||||
#WC13
|
||||
xgxs_tx_lane_map_54=0x1032
|
||||
xgxs_rx_lane_map_54=0x0132
|
||||
xgxs_tx_lane_map_55=0x1032
|
||||
xgxs_rx_lane_map_55=0x0132
|
||||
|
||||
#WC14
|
||||
xgxs_tx_lane_map_58=0x1032
|
||||
xgxs_rx_lane_map_58=0x3120
|
||||
|
||||
#WC15
|
||||
xgxs_tx_lane_map_62=0x2031
|
||||
xgxs_rx_lane_map_62=0x0132
|
||||
|
||||
#WC20
|
||||
xgxs_tx_lane_map_84=0x3120
|
||||
xgxs_rx_lane_map_84=0x1032
|
||||
|
||||
#WC21
|
||||
xgxs_tx_lane_map_88=0x2310
|
||||
xgxs_rx_lane_map_88=0x0123
|
||||
|
||||
#WC22
|
||||
xgxs_tx_lane_map_92=0x2310
|
||||
xgxs_rx_lane_map_92=0x1302
|
||||
xgxs_tx_lane_map_93=0x2310
|
||||
xgxs_rx_lane_map_93=0x1302
|
||||
|
||||
#WC23
|
||||
xgxs_tx_lane_map_96=0x1302
|
||||
xgxs_rx_lane_map_96=0x1023
|
||||
xgxs_tx_lane_map_97=0x1302
|
||||
xgxs_rx_lane_map_97=0x1023
|
||||
|
||||
#WC24
|
||||
xgxs_tx_lane_map_102=0x2310
|
||||
xgxs_rx_lane_map_102=0x1032
|
||||
xgxs_tx_lane_map_103=0x2310
|
||||
xgxs_rx_lane_map_103=0x1032
|
||||
|
||||
#WC25
|
||||
xgxs_tx_lane_map_106=0x2310
|
||||
xgxs_rx_lane_map_106=0x1023
|
||||
xgxs_tx_lane_map_107=0x2310
|
||||
xgxs_rx_lane_map_107=0x1023
|
||||
|
||||
#WC26
|
||||
xgxs_tx_lane_map_110=0x2310
|
||||
xgxs_rx_lane_map_110=0x1302
|
||||
|
||||
#WC27
|
||||
xgxs_tx_lane_map_114=0x1302
|
||||
xgxs_rx_lane_map_114=0x1032
|
||||
|
||||
#WC0
|
||||
xgxs_tx_lane_map_1=0x0123
|
||||
xgxs_rx_lane_map_1=0x0213
|
||||
|
||||
#WC1
|
||||
xgxs_tx_lane_map_5=0x2310
|
||||
xgxs_rx_lane_map_5=0x3201
|
||||
|
||||
#WC2
|
||||
xgxs_tx_lane_map_9=0x1023
|
||||
xgxs_rx_lane_map_9=0x0213
|
||||
xgxs_tx_lane_map_10=0x1023
|
||||
xgxs_rx_lane_map_10=0x0213
|
||||
|
||||
#WC3
|
||||
xgxs_tx_lane_map_13=0x1302
|
||||
xgxs_rx_lane_map_13=0x3201
|
||||
xgxs_tx_lane_map_14=0x1302
|
||||
xgxs_rx_lane_map_14=0x3201
|
||||
|
||||
#WC4
|
||||
xgxs_tx_lane_map_17=0x0132
|
||||
xgxs_rx_lane_map_17=0x0123
|
||||
xgxs_tx_lane_map_18=0x0132
|
||||
xgxs_rx_lane_map_18=0x0123
|
||||
|
||||
#WC5
|
||||
xgxs_tx_lane_map_21=0x1032
|
||||
xgxs_rx_lane_map_21=0x0213
|
||||
xgxs_tx_lane_map_22=0x1032
|
||||
xgxs_rx_lane_map_22=0x0213
|
||||
|
||||
#WC6
|
||||
xgxs_tx_lane_map_25=0x1023
|
||||
xgxs_rx_lane_map_25=0x3120
|
||||
xgxs_tx_lane_map_26=0x1023
|
||||
xgxs_rx_lane_map_26=0x3120
|
||||
|
||||
#WC7
|
||||
xgxs_tx_lane_map_29=0x2031
|
||||
xgxs_rx_lane_map_29=0x3201
|
||||
xgxs_tx_lane_map_30=0x2031
|
||||
xgxs_rx_lane_map_30=0x3201
|
||||
|
||||
#WC28
|
||||
xgxs_tx_lane_map_118=0x0231
|
||||
xgxs_rx_lane_map_118=0x2031
|
||||
xgxs_tx_lane_map_119=0x0231
|
||||
xgxs_rx_lane_map_119=0x2031
|
||||
|
||||
#WC29
|
||||
xgxs_tx_lane_map_122=0x3201
|
||||
xgxs_rx_lane_map_122=0x2301
|
||||
xgxs_tx_lane_map_123=0x3201
|
||||
xgxs_rx_lane_map_123=0x2301
|
||||
|
||||
#WC30
|
||||
xgxs_tx_lane_map_126=0x0213
|
||||
xgxs_rx_lane_map_126=0x0213
|
||||
xgxs_tx_lane_map_127=0x0213
|
||||
xgxs_rx_lane_map_127=0x0213
|
||||
|
||||
#WC31
|
||||
xgxs_tx_lane_map_130=0x2031
|
||||
xgxs_rx_lane_map_130=0x1032
|
||||
xgxs_tx_lane_map_131=0x2031
|
||||
xgxs_rx_lane_map_131=0x1032
|
||||
|
||||
#PN
|
||||
|
||||
#WC16
|
||||
phy_xaui_tx_polarity_flip_68=0x0000
|
||||
phy_xaui_rx_polarity_flip_68=0x0000
|
||||
phy_xaui_tx_polarity_flip_69=0x0000
|
||||
phy_xaui_rx_polarity_flip_69=0x0000
|
||||
|
||||
#WC17
|
||||
phy_xaui_tx_polarity_flip_72=0x0003
|
||||
phy_xaui_rx_polarity_flip_72=0x0000
|
||||
phy_xaui_tx_polarity_flip_73=0x0002
|
||||
phy_xaui_rx_polarity_flip_73=0x0001
|
||||
|
||||
|
||||
|
||||
#WC18
|
||||
phy_xaui_tx_polarity_flip_76=0x0003
|
||||
phy_xaui_rx_polarity_flip_76=0x0000
|
||||
phy_xaui_tx_polarity_flip_77=0x0003
|
||||
phy_xaui_rx_polarity_flip_77=0x0000
|
||||
|
||||
|
||||
#WC19
|
||||
phy_xaui_tx_polarity_flip_80=0x0003
|
||||
phy_xaui_rx_polarity_flip_80=0x0003
|
||||
phy_xaui_tx_polarity_flip_81=0x0003
|
||||
phy_xaui_rx_polarity_flip_81=0x0003
|
||||
|
||||
|
||||
#WC8
|
||||
phy_xaui_tx_polarity_flip_34=0x0003
|
||||
phy_xaui_rx_polarity_flip_34=0x0000
|
||||
phy_xaui_tx_polarity_flip_35=0x0001
|
||||
phy_xaui_rx_polarity_flip_35=0x0000
|
||||
|
||||
|
||||
#WC9
|
||||
phy_xaui_tx_polarity_flip_38=0x0001
|
||||
phy_xaui_rx_polarity_flip_38=0x0000
|
||||
phy_xaui_tx_polarity_flip_39=0x0000
|
||||
phy_xaui_rx_polarity_flip_39=0x0000
|
||||
|
||||
|
||||
#WC10
|
||||
phy_xaui_tx_polarity_flip_42=0x0003
|
||||
phy_xaui_rx_polarity_flip_42=0x0000
|
||||
phy_xaui_tx_polarity_flip_43=0x0002
|
||||
phy_xaui_rx_polarity_flip_43=0x0000
|
||||
|
||||
|
||||
#WC11
|
||||
phy_xaui_tx_polarity_flip_46=0x0000
|
||||
phy_xaui_rx_polarity_flip_46=0x0000
|
||||
phy_xaui_tx_polarity_flip_47=0x0000
|
||||
phy_xaui_rx_polarity_flip_47=0x0000
|
||||
|
||||
|
||||
#WC12
|
||||
phy_xaui_tx_polarity_flip_50=0x0000
|
||||
phy_xaui_rx_polarity_flip_50=0x0000
|
||||
phy_xaui_tx_polarity_flip_51=0x0001
|
||||
phy_xaui_rx_polarity_flip_51=0x0000
|
||||
|
||||
#WC13
|
||||
phy_xaui_tx_polarity_flip_54=0x0000
|
||||
phy_xaui_rx_polarity_flip_54=0x0000
|
||||
phy_xaui_tx_polarity_flip_55=0x0001
|
||||
phy_xaui_rx_polarity_flip_55=0x0000
|
||||
|
||||
#WC14
|
||||
phy_xaui_tx_polarity_flip_58=0x0000
|
||||
phy_xaui_rx_polarity_flip_58=0x0000
|
||||
|
||||
#WC15
|
||||
phy_xaui_tx_polarity_flip_62=0x0005
|
||||
phy_xaui_rx_polarity_flip_62=0x000F
|
||||
|
||||
#WC20
|
||||
phy_xaui_tx_polarity_flip_84=0x000E
|
||||
phy_xaui_rx_polarity_flip_84=0x0007
|
||||
|
||||
#WC21
|
||||
phy_xaui_tx_polarity_flip_88=0x000B
|
||||
phy_xaui_rx_polarity_flip_88=0x000B
|
||||
|
||||
#WC22
|
||||
phy_xaui_tx_polarity_flip_92=0x0003
|
||||
phy_xaui_rx_polarity_flip_92=0x0001
|
||||
phy_xaui_tx_polarity_flip_93=0x0003
|
||||
phy_xaui_rx_polarity_flip_93=0x0000
|
||||
|
||||
|
||||
#WC23
|
||||
phy_xaui_tx_polarity_flip_96=0x0002
|
||||
phy_xaui_rx_polarity_flip_96=0x0000
|
||||
phy_xaui_tx_polarity_flip_97=0x0002
|
||||
phy_xaui_rx_polarity_flip_97=0x0000
|
||||
|
||||
#WC24
|
||||
phy_xaui_tx_polarity_flip_102=0x0000
|
||||
phy_xaui_rx_polarity_flip_102=0x0003
|
||||
phy_xaui_tx_polarity_flip_103=0x0000
|
||||
phy_xaui_rx_polarity_flip_103=0x0003
|
||||
|
||||
|
||||
#WC25
|
||||
phy_xaui_tx_polarity_flip_106=0x0003
|
||||
phy_xaui_rx_polarity_flip_106=0x0000
|
||||
phy_xaui_tx_polarity_flip_107=0x0003
|
||||
phy_xaui_rx_polarity_flip_107=0x0000
|
||||
|
||||
#WC26
|
||||
phy_xaui_tx_polarity_flip_110=0x000F
|
||||
phy_xaui_rx_polarity_flip_110=0x000F
|
||||
|
||||
#WC27
|
||||
phy_xaui_tx_polarity_flip_114=0x000F
|
||||
phy_xaui_rx_polarity_flip_114=0x000E
|
||||
|
||||
#WC0
|
||||
phy_xaui_tx_polarity_flip_1=0x000C
|
||||
phy_xaui_rx_polarity_flip_1=0x000F
|
||||
|
||||
#WC1
|
||||
phy_xaui_tx_polarity_flip_5=0x000E
|
||||
phy_xaui_rx_polarity_flip_5=0x0000
|
||||
|
||||
#WC2
|
||||
phy_xaui_tx_polarity_flip_9=0x0000
|
||||
phy_xaui_rx_polarity_flip_9=0x0001
|
||||
phy_xaui_tx_polarity_flip_10=0x0001
|
||||
phy_xaui_rx_polarity_flip_10=0x0000
|
||||
|
||||
|
||||
#WC3
|
||||
phy_xaui_tx_polarity_flip_13=0x0003
|
||||
phy_xaui_rx_polarity_flip_13=0x0000
|
||||
phy_xaui_tx_polarity_flip_14=0x0003
|
||||
phy_xaui_rx_polarity_flip_14=0x0000
|
||||
|
||||
#WC4
|
||||
phy_xaui_tx_polarity_flip_17=0x0002
|
||||
phy_xaui_rx_polarity_flip_17=0x0000
|
||||
phy_xaui_tx_polarity_flip_18=0x0003
|
||||
phy_xaui_rx_polarity_flip_18=0x0000
|
||||
|
||||
|
||||
#WC5
|
||||
phy_xaui_tx_polarity_flip_21=0x0000
|
||||
phy_xaui_rx_polarity_flip_21=0x0000
|
||||
phy_xaui_tx_polarity_flip_22=0x0000
|
||||
phy_xaui_rx_polarity_flip_22=0x0000
|
||||
|
||||
|
||||
#WC6
|
||||
phy_xaui_tx_polarity_flip_25=0x0000
|
||||
phy_xaui_rx_polarity_flip_25=0x0002
|
||||
phy_xaui_tx_polarity_flip_26=0x0001
|
||||
phy_xaui_rx_polarity_flip_26=0x0002
|
||||
|
||||
|
||||
#WC7
|
||||
phy_xaui_tx_polarity_flip_29=0x0000
|
||||
phy_xaui_rx_polarity_flip_29=0x0000
|
||||
phy_xaui_tx_polarity_flip_30=0x0001
|
||||
phy_xaui_rx_polarity_flip_30=0x0000
|
||||
|
||||
|
||||
#WC28
|
||||
phy_xaui_tx_polarity_flip_118=0x0003
|
||||
phy_xaui_rx_polarity_flip_118=0x0003
|
||||
phy_xaui_tx_polarity_flip_119=0x0003
|
||||
phy_xaui_rx_polarity_flip_119=0x0003
|
||||
|
||||
|
||||
#WC29
|
||||
phy_xaui_tx_polarity_flip_122=0x0002
|
||||
phy_xaui_rx_polarity_flip_122=0x0000
|
||||
phy_xaui_tx_polarity_flip_123=0x0000
|
||||
phy_xaui_rx_polarity_flip_123=0x0000
|
||||
|
||||
|
||||
#WC30
|
||||
phy_xaui_tx_polarity_flip_126=0x0003
|
||||
phy_xaui_rx_polarity_flip_126=0x0000
|
||||
phy_xaui_tx_polarity_flip_127=0x0003
|
||||
phy_xaui_rx_polarity_flip_127=0x0000
|
||||
|
||||
|
||||
#WC31
|
||||
phy_xaui_tx_polarity_flip_130=0x0002
|
||||
phy_xaui_rx_polarity_flip_130=0x0000
|
||||
phy_xaui_tx_polarity_flip_131=0x0001
|
||||
phy_xaui_rx_polarity_flip_131=0x0000
|
||||
|
||||
#xe
|
||||
serdes_driver_current=0x0a
|
||||
serdes_preemphasis=0x1a5402
|
||||
|
||||
#ce0
|
||||
serdes_driver_current_lane0_58=0x0a
|
||||
serdes_driver_current_lane1_58=0x09
|
||||
serdes_driver_current_lane2_58=0x09
|
||||
serdes_driver_current_lane3_58=0x0a
|
||||
serdes_preemphasis_lane0_58=0x254902
|
||||
serdes_preemphasis_lane1_58=0x244a02
|
||||
serdes_preemphasis_lane2_58=0x244a02
|
||||
serdes_preemphasis_lane3_58=0x254902
|
||||
|
||||
#ce1
|
||||
serdes_driver_current_lane0_62=0x09
|
||||
serdes_driver_current_lane1_62=0x0a
|
||||
serdes_driver_current_lane2_62=0x09
|
||||
serdes_driver_current_lane3_62=0x09
|
||||
serdes_preemphasis_lane0_62=0x244a02
|
||||
serdes_preemphasis_lane1_62=0x254902
|
||||
serdes_preemphasis_lane2_62=0x244a02
|
||||
serdes_preemphasis_lane3_62=0x244a02
|
||||
|
||||
#ce2
|
||||
serdes_driver_current_lane0_84=0x09
|
||||
serdes_driver_current_lane1_84=0x09
|
||||
serdes_driver_current_lane2_84=0x09
|
||||
serdes_driver_current_lane3_84=0x09
|
||||
serdes_preemphasis_lane0_84=0x204e02
|
||||
serdes_preemphasis_lane1_84=0x204e02
|
||||
serdes_preemphasis_lane2_84=0x204e02
|
||||
serdes_preemphasis_lane3_84=0x204e02
|
||||
|
||||
#ce3
|
||||
serdes_driver_current_lane0_88=0x09
|
||||
serdes_driver_current_lane1_88=0x08
|
||||
serdes_driver_current_lane2_88=0x08
|
||||
serdes_driver_current_lane3_88=0x09
|
||||
serdes_preemphasis_lane0_88=0x204e02
|
||||
serdes_preemphasis_lane1_88=0x1d5102
|
||||
serdes_preemphasis_lane2_88=0x1d5102
|
||||
serdes_preemphasis_lane3_88=0x204e02
|
||||
|
||||
#ce4
|
||||
serdes_driver_current_lane0_110=0x09
|
||||
serdes_driver_current_lane1_110=0x08
|
||||
serdes_driver_current_lane2_110=0x08
|
||||
serdes_driver_current_lane3_110=0x09
|
||||
serdes_preemphasis_lane0_110=0x204e02
|
||||
serdes_preemphasis_lane1_110=0x1d5102
|
||||
serdes_preemphasis_lane2_110=0x1d5102
|
||||
serdes_preemphasis_lane3_110=0x204e02
|
||||
|
||||
#ce5
|
||||
serdes_driver_current_lane0_114=0x09
|
||||
serdes_driver_current_lane1_114=0x08
|
||||
serdes_driver_current_lane2_114=0x09
|
||||
serdes_driver_current_lane3_114=0x09
|
||||
serdes_preemphasis_lane0_114=0x204e02
|
||||
serdes_preemphasis_lane1_114=0x1d5102
|
||||
serdes_preemphasis_lane2_114=0x224c02
|
||||
serdes_preemphasis_lane3_114=0x224c02
|
||||
|
||||
#ce6
|
||||
serdes_driver_current_lane0_1=0x09
|
||||
serdes_driver_current_lane1_1=0x0a
|
||||
serdes_driver_current_lane2_1=0x09
|
||||
serdes_driver_current_lane3_1=0x0a
|
||||
serdes_preemphasis_lane0_1=0x244a02
|
||||
serdes_preemphasis_lane1_1=0x254902
|
||||
serdes_preemphasis_lane2_1=0x244a02
|
||||
serdes_preemphasis_lane3_1=0x254902
|
||||
|
||||
#ce7
|
||||
serdes_driver_current_lane0_5=0x09
|
||||
serdes_driver_current_lane1_5=0x09
|
||||
serdes_driver_current_lane2_5=0x09
|
||||
serdes_driver_current_lane3_5=0x0a
|
||||
serdes_preemphasis_lane0_5=0x244a02
|
||||
serdes_preemphasis_lane1_5=0x244a02
|
||||
serdes_preemphasis_lane2_5=0x244a02
|
||||
serdes_preemphasis_lane3_5=0x254902
|
||||
|
||||
Loading…
Reference in New Issue
Block a user