Add support as4630-54pe device and sdk cfg (#2928)
* Add to support as4630-54pe platform * Add as4630 monitor psu/fan status * Add support as4630-54pe device and sdk cfg
This commit is contained in:
jostar-yang
lguohan
parent
62ef8593e7
commit
b44eef9822
@ -0,0 +1,486 @@
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stable_size=71303168
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#polarity/lanemap is using TH2 style.
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core_clock_frequency=893
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dpp_clock_ratio=2:3
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ptp_ts_pll_fref=50000000
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ptp_bs_fref_0=50000000
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ptp_bs_fref_1=50000000
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#oversubscribe_mode=1
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pbmp_xport_xe=0x1FFFFFFE000000000000
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parity_enable=0
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mem_cache_enable=1
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l2_mem_entries=32768
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#l3_mem_entries=49152
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#fpem_mem_entries=16384
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l2xmsg_mode=1
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port_flex_enable=1
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#3x PM4x10Q (3 * 16 = 48 physical ports)
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#Doesn't support oversubscribe in Q mode
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#MCQ0
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port_gmii_mode_1=1 #Q mode
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#PHY4 U56 xx1, MDC/MDIO2, PHYADDR:0x00-0x07, 0x08
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port_phy_addr_1=0x40
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port_phy_addr_2=0x41
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port_phy_addr_3=0x42
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port_phy_addr_4=0x43
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port_phy_addr_5=0x44
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port_phy_addr_6=0x45
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port_phy_addr_7=0x46
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port_phy_addr_8=0x47
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phy_port_primary_and_offset_1=0x0100
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phy_port_primary_and_offset_2=0x0101
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phy_port_primary_and_offset_3=0x0102
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phy_port_primary_and_offset_4=0x0103
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phy_port_primary_and_offset_5=0x0104
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phy_port_primary_and_offset_6=0x0105
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phy_port_primary_and_offset_7=0x0106
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phy_port_primary_and_offset_8=0x0107
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dport_map_port_1=26
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dport_map_port_2=25
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dport_map_port_3=28
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dport_map_port_4=27
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dport_map_port_5=30
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dport_map_port_6=29
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dport_map_port_7=32
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dport_map_port_8=31
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portmap_1=1:1
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portmap_2=2:1
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portmap_3=3:1
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portmap_4=4:1
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portmap_5=5:1
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portmap_6=6:1
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portmap_7=7:1
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portmap_8=8:1
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phy_chain_rx_lane_map_physical{1.0}=0x3210
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phy_chain_rx_lane_map_physical{2.0}=0x3210
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phy_chain_rx_lane_map_physical{3.0}=0x3210
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phy_chain_rx_lane_map_physical{4.0}=0x3210
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phy_chain_rx_lane_map_physical{5.0}=0x3210
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phy_chain_rx_lane_map_physical{6.0}=0x3210
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phy_chain_rx_lane_map_physical{7.0}=0x3210
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phy_chain_rx_lane_map_physical{8.0}=0x3210
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phy_chain_tx_lane_map_physical{1.0}=0x3210
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phy_chain_tx_lane_map_physical{2.0}=0x3210
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phy_chain_tx_lane_map_physical{3.0}=0x3210
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phy_chain_tx_lane_map_physical{4.0}=0x3210
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phy_chain_tx_lane_map_physical{5.0}=0x3210
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phy_chain_tx_lane_map_physical{6.0}=0x3210
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phy_chain_tx_lane_map_physical{7.0}=0x3210
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phy_chain_tx_lane_map_physical{8.0}=0x3210
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phy_chain_rx_polarity_flip_physical{1.0}=0x0
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phy_chain_rx_polarity_flip_physical{2.0}=0x0
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phy_chain_rx_polarity_flip_physical{3.0}=0x0
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phy_chain_rx_polarity_flip_physical{4.0}=0x0
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phy_chain_rx_polarity_flip_physical{5.0}=0x0
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phy_chain_rx_polarity_flip_physical{6.0}=0x0
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phy_chain_rx_polarity_flip_physical{7.0}=0x0
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phy_chain_rx_polarity_flip_physical{8.0}=0x0
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phy_chain_tx_polarity_flip_physical{1.0}=0x0
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phy_chain_tx_polarity_flip_physical{2.0}=0x0
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phy_chain_tx_polarity_flip_physical{3.0}=0x0
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phy_chain_tx_polarity_flip_physical{4.0}=0x0
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phy_chain_tx_polarity_flip_physical{5.0}=0x0
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phy_chain_tx_polarity_flip_physical{6.0}=0x0
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phy_chain_tx_polarity_flip_physical{7.0}=0x0
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phy_chain_tx_polarity_flip_physical{8.0}=0x0
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#PHY5 U57 x1x, MDC/MDIO2, PHYADDR:0x09-0x10, 0x11
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port_phy_addr_9=0x49
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port_phy_addr_10=0x4A
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port_phy_addr_11=0x4B
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port_phy_addr_12=0x4C
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port_phy_addr_13=0x4D
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port_phy_addr_14=0x4E
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port_phy_addr_15=0x4F
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port_phy_addr_16=0x50
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phy_port_primary_and_offset_9=0x0900
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phy_port_primary_and_offset_10=0x0901
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phy_port_primary_and_offset_11=0x0902
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phy_port_primary_and_offset_12=0x0903
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phy_port_primary_and_offset_13=0x0904
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phy_port_primary_and_offset_14=0x0905
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phy_port_primary_and_offset_15=0x0906
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phy_port_primary_and_offset_16=0x0907
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dport_map_port_9=34
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dport_map_port_10=33
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dport_map_port_11=36
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dport_map_port_12=35
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dport_map_port_13=38
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dport_map_port_14=37
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dport_map_port_15=40
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dport_map_port_16=39
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portmap_9=9:1
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portmap_10=10:1
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portmap_11=11:1
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portmap_12=12:1
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portmap_13=13:1
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portmap_14=14:1
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portmap_15=15:1
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portmap_16=16:1
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phy_chain_rx_lane_map_physical{9.0}=0x3210
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phy_chain_rx_lane_map_physical{10.0}=0x3210
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phy_chain_rx_lane_map_physical{11.0}=0x3210
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phy_chain_rx_lane_map_physical{12.0}=0x3210
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phy_chain_rx_lane_map_physical{13.0}=0x3210
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phy_chain_rx_lane_map_physical{14.0}=0x3210
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phy_chain_rx_lane_map_physical{15.0}=0x3210
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phy_chain_rx_lane_map_physical{16.0}=0x3210
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phy_chain_tx_lane_map_physical{9.0}=0x3210
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phy_chain_tx_lane_map_physical{10.0}=0x3210
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phy_chain_tx_lane_map_physical{11.0}=0x3210
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phy_chain_tx_lane_map_physical{12.0}=0x3210
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phy_chain_tx_lane_map_physical{13.0}=0x3210
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phy_chain_tx_lane_map_physical{14.0}=0x3210
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phy_chain_tx_lane_map_physical{15.0}=0x3210
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phy_chain_tx_lane_map_physical{16.0}=0x3210
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phy_chain_rx_polarity_flip_physical{9.0}=0x0
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phy_chain_rx_polarity_flip_physical{10.0}=0x0
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phy_chain_rx_polarity_flip_physical{11.0}=0x0
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phy_chain_rx_polarity_flip_physical{12.0}=0x0
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phy_chain_rx_polarity_flip_physical{13.0}=0x0
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phy_chain_rx_polarity_flip_physical{14.0}=0x0
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phy_chain_rx_polarity_flip_physical{15.0}=0x0
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phy_chain_rx_polarity_flip_physical{16.0}=0x0
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phy_chain_tx_polarity_flip_physical{9.0}=0x0
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phy_chain_tx_polarity_flip_physical{10.0}=0x0
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phy_chain_tx_polarity_flip_physical{11.0}=0x0
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phy_chain_tx_polarity_flip_physical{12.0}=0x0
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phy_chain_tx_polarity_flip_physical{13.0}=0x0
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phy_chain_tx_polarity_flip_physical{14.0}=0x0
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phy_chain_tx_polarity_flip_physical{15.0}=0x0
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phy_chain_tx_polarity_flip_physical{16.0}=0x0
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#MCQ1
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port_gmii_mode_17=1 #Q mode
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#PHY6 U58 11x, MDC/MDIO2, PHYADDR:0x12-0x19, 0x1A
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port_phy_addr_17=0x52
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port_phy_addr_18=0x53
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port_phy_addr_19=0x54
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port_phy_addr_20=0x55
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port_phy_addr_21=0x56
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port_phy_addr_22=0x57
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port_phy_addr_23=0x58
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port_phy_addr_24=0x59
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phy_port_primary_and_offset_17=0x1100
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phy_port_primary_and_offset_18=0x1101
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phy_port_primary_and_offset_19=0x1102
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phy_port_primary_and_offset_20=0x1103
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phy_port_primary_and_offset_21=0x1104
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phy_port_primary_and_offset_22=0x1105
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phy_port_primary_and_offset_23=0x1106
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phy_port_primary_and_offset_24=0x1107
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dport_map_port_17=42
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dport_map_port_18=41
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dport_map_port_19=44
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dport_map_port_20=43
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dport_map_port_21=46
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dport_map_port_22=45
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dport_map_port_23=48
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dport_map_port_24=47
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portmap_17=17:1
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portmap_18=18:1
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portmap_19=19:1
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portmap_20=20:1
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portmap_21=21:1
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portmap_22=22:1
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portmap_23=23:1
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portmap_24=24:1
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phy_chain_rx_lane_map_physical{17.0}=0x3210
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phy_chain_rx_lane_map_physical{18.0}=0x3210
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phy_chain_rx_lane_map_physical{19.0}=0x3210
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phy_chain_rx_lane_map_physical{20.0}=0x3210
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phy_chain_rx_lane_map_physical{21.0}=0x3210
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phy_chain_rx_lane_map_physical{22.0}=0x3210
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phy_chain_rx_lane_map_physical{23.0}=0x3210
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phy_chain_rx_lane_map_physical{24.0}=0x3210
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phy_chain_tx_lane_map_physical{17.0}=0x3210
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phy_chain_tx_lane_map_physical{18.0}=0x3210
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phy_chain_tx_lane_map_physical{19.0}=0x3210
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phy_chain_tx_lane_map_physical{20.0}=0x3210
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phy_chain_tx_lane_map_physical{21.0}=0x3210
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phy_chain_tx_lane_map_physical{22.0}=0x3210
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phy_chain_tx_lane_map_physical{23.0}=0x3210
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phy_chain_tx_lane_map_physical{24.0}=0x3210
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phy_chain_rx_polarity_flip_physical{17.0}=0x0
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phy_chain_rx_polarity_flip_physical{18.0}=0x0
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phy_chain_rx_polarity_flip_physical{19.0}=0x0
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phy_chain_rx_polarity_flip_physical{20.0}=0x0
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phy_chain_rx_polarity_flip_physical{21.0}=0x0
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phy_chain_rx_polarity_flip_physical{22.0}=0x0
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phy_chain_rx_polarity_flip_physical{23.0}=0x0
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phy_chain_rx_polarity_flip_physical{24.0}=0x0
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phy_chain_tx_polarity_flip_physical{17.0}=0x0
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phy_chain_tx_polarity_flip_physical{18.0}=0x0
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phy_chain_tx_polarity_flip_physical{19.0}=0x0
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phy_chain_tx_polarity_flip_physical{20.0}=0x0
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phy_chain_tx_polarity_flip_physical{21.0}=0x0
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phy_chain_tx_polarity_flip_physical{22.0}=0x0
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phy_chain_tx_polarity_flip_physical{23.0}=0x0
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phy_chain_tx_polarity_flip_physical{24.0}=0x0
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#PHY1 U53 xx1, MDC/MDIO0, PHYADDR:0x00-0x07, 0x08
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port_phy_addr_25=0x00
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port_phy_addr_26=0x01
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port_phy_addr_27=0x02
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port_phy_addr_28=0x03
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port_phy_addr_29=0x04
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port_phy_addr_30=0x05
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port_phy_addr_31=0x06
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port_phy_addr_32=0x07
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phy_port_primary_and_offset_25=0x1900
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phy_port_primary_and_offset_26=0x1901
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phy_port_primary_and_offset_27=0x1902
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phy_port_primary_and_offset_28=0x1903
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phy_port_primary_and_offset_29=0x1904
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phy_port_primary_and_offset_30=0x1905
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phy_port_primary_and_offset_31=0x1906
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phy_port_primary_and_offset_32=0x1907
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dport_map_port_25=2
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dport_map_port_26=1
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dport_map_port_27=4
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dport_map_port_28=3
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dport_map_port_29=6
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dport_map_port_30=5
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dport_map_port_31=8
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dport_map_port_32=7
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portmap_25=25:1
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portmap_26=26:1
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portmap_27=27:1
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portmap_28=28:1
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portmap_29=29:1
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portmap_30=30:1
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portmap_31=31:1
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portmap_32=32:1
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phy_chain_rx_lane_map_physical{25.0}=0x3210
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phy_chain_rx_lane_map_physical{26.0}=0x3210
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phy_chain_rx_lane_map_physical{27.0}=0x3210
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phy_chain_rx_lane_map_physical{28.0}=0x3210
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phy_chain_rx_lane_map_physical{29.0}=0x3210
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phy_chain_rx_lane_map_physical{30.0}=0x3210
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phy_chain_rx_lane_map_physical{31.0}=0x3210
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phy_chain_rx_lane_map_physical{32.0}=0x3210
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phy_chain_tx_lane_map_physical{25.0}=0x3210
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phy_chain_tx_lane_map_physical{26.0}=0x3210
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phy_chain_tx_lane_map_physical{27.0}=0x3210
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phy_chain_tx_lane_map_physical{28.0}=0x3210
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phy_chain_tx_lane_map_physical{29.0}=0x3210
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phy_chain_tx_lane_map_physical{30.0}=0x3210
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phy_chain_tx_lane_map_physical{31.0}=0x3210
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phy_chain_tx_lane_map_physical{32.0}=0x3210
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phy_chain_rx_polarity_flip_physical{25.0}=0x0
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phy_chain_rx_polarity_flip_physical{26.0}=0x0
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phy_chain_rx_polarity_flip_physical{27.0}=0x0
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phy_chain_rx_polarity_flip_physical{28.0}=0x0
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phy_chain_rx_polarity_flip_physical{29.0}=0x0
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phy_chain_rx_polarity_flip_physical{30.0}=0x0
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phy_chain_rx_polarity_flip_physical{31.0}=0x0
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phy_chain_rx_polarity_flip_physical{32.0}=0x0
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phy_chain_tx_polarity_flip_physical{25.0}=0x0
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phy_chain_tx_polarity_flip_physical{26.0}=0x0
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phy_chain_tx_polarity_flip_physical{27.0}=0x0
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phy_chain_tx_polarity_flip_physical{28.0}=0x0
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phy_chain_tx_polarity_flip_physical{29.0}=0x0
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phy_chain_tx_polarity_flip_physical{30.0}=0x0
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phy_chain_tx_polarity_flip_physical{31.0}=0x0
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phy_chain_tx_polarity_flip_physical{32.0}=0x0
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#MCQ2
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port_gmii_mode_33=1 #Q mode
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#PHY2 U54 x1x, MDC/MDIO0, PHYADDR:0x09-0x10, 0x11
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port_phy_addr_33=0x0D
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port_phy_addr_34=0x0E
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port_phy_addr_35=0x0F
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port_phy_addr_36=0x10
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port_phy_addr_37=0x09
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port_phy_addr_38=0x0A
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port_phy_addr_39=0x0B
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port_phy_addr_40=0x0C
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phy_port_primary_and_offset_33=0x2504
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phy_port_primary_and_offset_34=0x2505
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phy_port_primary_and_offset_35=0x2506
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phy_port_primary_and_offset_36=0x2507
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phy_port_primary_and_offset_37=0x2500
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phy_port_primary_and_offset_38=0x2501
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phy_port_primary_and_offset_39=0x2502
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phy_port_primary_and_offset_40=0x2503
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dport_map_port_33=14
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dport_map_port_34=13
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dport_map_port_35=16
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dport_map_port_36=15
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dport_map_port_37=10
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dport_map_port_38=9
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dport_map_port_39=12
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dport_map_port_40=11
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portmap_33=33:1
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portmap_34=34:1
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portmap_35=35:1
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portmap_36=36:1
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portmap_37=37:1
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portmap_38=38:1
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portmap_39=39:1
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portmap_40=40:1
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phy_chain_rx_lane_map_physical{33.0}=0x3210
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phy_chain_rx_lane_map_physical{34.0}=0x3210
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phy_chain_rx_lane_map_physical{35.0}=0x3210
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phy_chain_rx_lane_map_physical{36.0}=0x3210
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phy_chain_rx_lane_map_physical{37.0}=0x3210
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phy_chain_rx_lane_map_physical{38.0}=0x3210
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phy_chain_rx_lane_map_physical{39.0}=0x3210
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phy_chain_rx_lane_map_physical{40.0}=0x3210
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phy_chain_tx_lane_map_physical{33.0}=0x3210
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phy_chain_tx_lane_map_physical{34.0}=0x3210
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phy_chain_tx_lane_map_physical{35.0}=0x3210
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phy_chain_tx_lane_map_physical{36.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{37.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{38.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{39.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{40.0}=0x3210
|
||||
phy_chain_rx_polarity_flip_physical{33.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{34.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{35.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{36.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{37.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{38.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{39.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{40.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{33.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{34.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{35.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{36.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{37.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{38.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{39.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{40.0}=0x1
|
||||
|
||||
#PHY3 U55 11x, MDC/MDIO0, PHYADDR:0x12-0x19, 0x1A
|
||||
port_phy_addr_41=0x16
|
||||
port_phy_addr_42=0x17
|
||||
port_phy_addr_43=0x18
|
||||
port_phy_addr_44=0x19
|
||||
port_phy_addr_45=0x12
|
||||
port_phy_addr_46=0x13
|
||||
port_phy_addr_47=0x14
|
||||
port_phy_addr_48=0x15
|
||||
phy_port_primary_and_offset_41=0x2D00
|
||||
phy_port_primary_and_offset_42=0x2D01
|
||||
phy_port_primary_and_offset_43=0x2D02
|
||||
phy_port_primary_and_offset_44=0x2D03
|
||||
phy_port_primary_and_offset_45=0x2D04
|
||||
phy_port_primary_and_offset_46=0x2D05
|
||||
phy_port_primary_and_offset_47=0x2D06
|
||||
phy_port_primary_and_offset_48=0x2D07
|
||||
dport_map_port_41=22
|
||||
dport_map_port_42=21
|
||||
dport_map_port_43=24
|
||||
dport_map_port_44=23
|
||||
dport_map_port_45=18
|
||||
dport_map_port_46=17
|
||||
dport_map_port_47=20
|
||||
dport_map_port_48=19
|
||||
portmap_41=41:1
|
||||
portmap_42=42:1
|
||||
portmap_43=43:1
|
||||
portmap_44=44:1
|
||||
portmap_45=45:1
|
||||
portmap_46=46:1
|
||||
portmap_47=47:1
|
||||
portmap_48=48:1
|
||||
phy_chain_rx_lane_map_physical{41.0}=0x3210
|
||||
phy_chain_rx_lane_map_physical{42.0}=0x3210
|
||||
phy_chain_rx_lane_map_physical{43.0}=0x3210
|
||||
phy_chain_rx_lane_map_physical{44.0}=0x3210
|
||||
phy_chain_rx_lane_map_physical{45.0}=0x3210
|
||||
phy_chain_rx_lane_map_physical{46.0}=0x3210
|
||||
phy_chain_rx_lane_map_physical{47.0}=0x3210
|
||||
phy_chain_rx_lane_map_physical{48.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{41.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{42.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{43.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{44.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{45.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{46.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{47.0}=0x3210
|
||||
phy_chain_tx_lane_map_physical{48.0}=0x3210
|
||||
phy_chain_rx_polarity_flip_physical{41.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{42.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{43.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{44.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{45.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{46.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{47.0}=0x1
|
||||
phy_chain_rx_polarity_flip_physical{48.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{41.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{42.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{43.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{44.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{45.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{46.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{47.0}=0x1
|
||||
phy_chain_tx_polarity_flip_physical{48.0}=0x1
|
||||
|
||||
#3x PM4x25 (3 * 4 = 12 physical ports)
|
||||
#FC0
|
||||
dport_map_port_49=51
|
||||
dport_map_port_50=50
|
||||
dport_map_port_51=49
|
||||
dport_map_port_52=52
|
||||
portmap_49=65:25
|
||||
portmap_50=66:25
|
||||
portmap_51=67:25
|
||||
portmap_52=68:25
|
||||
#FC1
|
||||
dport_map_port_53=57
|
||||
dport_map_port_54=58
|
||||
dport_map_port_55=59
|
||||
dport_map_port_56=60
|
||||
portmap_53=69:100:4
|
||||
#portmap_55=71:50
|
||||
#portmap_54=70:25
|
||||
#portmap_55=71:25
|
||||
#portmap_56=72:25
|
||||
#FC2
|
||||
dport_map_port_57=53
|
||||
dport_map_port_58=54
|
||||
dport_map_port_59=55
|
||||
dport_map_port_60=56
|
||||
portmap_57=73:100:4
|
||||
#portmap_59=75:50
|
||||
#portmap_58=74:25
|
||||
#portmap_59=75:25
|
||||
#portmap_60=76:25
|
||||
|
||||
#4x PM4x10 (4 * 4 = 16 physical ports)
|
||||
#MC0 No connection
|
||||
#MC1 No connection
|
||||
#MC2 No connection
|
||||
#MC3 No connection
|
||||
#portmap_=49:10
|
||||
#portmap_=50:10
|
||||
#portmap_=51:10
|
||||
#portmap_=52:10
|
||||
|
||||
#portmap_=53:10
|
||||
#portmap_=54:10
|
||||
#portmap_=55:10
|
||||
#portmap_=56:10
|
||||
|
||||
#portmap_=57:10
|
||||
#portmap_=58:10
|
||||
#portmap_=59:10
|
||||
#portmap_=60:10
|
||||
|
||||
#portmap_=61:10
|
||||
#portmap_=62:10
|
||||
#portmap_=63:10
|
||||
#portmap_=64:10
|
||||
@ -0,0 +1,55 @@
|
||||
# name lanes alias index
|
||||
Ethernet0 26 thousandE1 0
|
||||
Ethernet1 25 thousandE2 1
|
||||
Ethernet2 28 thousandE3 2
|
||||
Ethernet3 27 thousandE4 3
|
||||
Ethernet4 30 thousandE5 4
|
||||
Ethernet5 29 thousandE6 5
|
||||
Ethernet6 32 thousandE7 6
|
||||
Ethernet7 31 thousandE8 7
|
||||
Ethernet8 38 thousandE9 8
|
||||
Ethernet9 37 thousandE10 9
|
||||
Ethernet10 40 thousandE11 10
|
||||
Ethernet11 39 thousandE12 11
|
||||
Ethernet12 34 thousandE13 12
|
||||
Ethernet13 33 thousandE14 13
|
||||
Ethernet14 36 thousandE15 14
|
||||
Ethernet15 35 thousandE16 15
|
||||
Ethernet16 46 thousandE17 16
|
||||
Ethernet17 45 thousandE18 17
|
||||
Ethernet18 48 thousandE19 18
|
||||
Ethernet19 47 thousandE20 19
|
||||
Ethernet20 42 thousandE21 20
|
||||
Ethernet21 41 thousandE22 21
|
||||
Ethernet22 44 thousandE23 22
|
||||
Ethernet23 43 thousandE24 23
|
||||
Ethernet24 2 thousandE25 24
|
||||
Ethernet25 1 thousandE26 25
|
||||
Ethernet26 4 thousandE27 26
|
||||
Ethernet27 3 thousandE28 27
|
||||
Ethernet28 6 thousandE29 28
|
||||
Ethernet29 5 thousandE30 29
|
||||
Ethernet30 8 thousandE31 30
|
||||
Ethernet31 7 thousandE32 31
|
||||
Ethernet32 10 thousandE33 32
|
||||
Ethernet33 9 thousandE34 33
|
||||
Ethernet34 12 thousandE35 34
|
||||
Ethernet35 11 thousandE36 35
|
||||
Ethernet36 14 thousandE37 36
|
||||
Ethernet37 13 thousandE38 37
|
||||
Ethernet38 16 thousandE39 38
|
||||
Ethernet39 15 thousandE40 39
|
||||
Ethernet40 18 thousandE41 40
|
||||
Ethernet41 17 thousandE42 41
|
||||
Ethernet42 20 thousandE43 42
|
||||
Ethernet43 19 thousandE44 43
|
||||
Ethernet44 22 thousandE45 44
|
||||
Ethernet45 21 thousandE46 45
|
||||
Ethernet46 24 thousandE47 46
|
||||
Ethernet47 23 thousandE48 47
|
||||
Ethernet48 67 twentyfiveGigE49 48
|
||||
Ethernet49 66 twentyfiveGigE50 49
|
||||
Ethernet50 65 twentyfiveGigE51 50
|
||||
Ethernet51 68 twentyfiveGigE52 51
|
||||
Ethernet52 73,74,75,76 hundredGigE53 52
|
||||
Ethernet56 69,70,71,72 hundredGigE54 56
|
||||
@ -0,0 +1 @@
|
||||
SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/hx5-as4630-48x1G+4x25G+2x100G.bcm
|
||||
1
device/accton/x86_64-accton_as4630_54pe-r0/default_sku
Executable file
1
device/accton/x86_64-accton_as4630_54pe-r0/default_sku
Executable file
@ -0,0 +1 @@
|
||||
Accton-AS4630-54PE t1
|
||||
3
device/accton/x86_64-accton_as4630_54pe-r0/installer.conf
Executable file
3
device/accton/x86_64-accton_as4630_54pe-r0/installer.conf
Executable file
@ -0,0 +1,3 @@
|
||||
CONSOLE_PORT=0x3f8
|
||||
CONSOLE_DEV=0
|
||||
CONSOLE_SPEED=115200
|
||||
2
device/accton/x86_64-accton_as4630_54pe-r0/led_proc_init.soc
Executable file
2
device/accton/x86_64-accton_as4630_54pe-r0/led_proc_init.soc
Executable file
@ -0,0 +1,2 @@
|
||||
led start
|
||||
led auto on
|
||||
21
device/accton/x86_64-accton_as4630_54pe-r0/plugins/eeprom.py
Executable file
21
device/accton/x86_64-accton_as4630_54pe-r0/plugins/eeprom.py
Executable file
@ -0,0 +1,21 @@
|
||||
#!/usr/bin/env python
|
||||
|
||||
try:
|
||||
import exceptions
|
||||
import binascii
|
||||
import time
|
||||
import optparse
|
||||
import warnings
|
||||
import os
|
||||
import sys
|
||||
from sonic_eeprom import eeprom_base
|
||||
from sonic_eeprom import eeprom_tlvinfo
|
||||
import subprocess
|
||||
except ImportError, e:
|
||||
raise ImportError (str(e) + "- required module not found")
|
||||
|
||||
class board(eeprom_tlvinfo.TlvInfoDecoder):
|
||||
_TLV_INFO_MAX_LEN = 256
|
||||
def __init__(self, name, path, cpld_root, ro):
|
||||
self.eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
|
||||
super(board, self).__init__(self.eeprom_path, 0, '', True)
|
||||
61
device/accton/x86_64-accton_as4630_54pe-r0/plugins/psuutil.py
Executable file
61
device/accton/x86_64-accton_as4630_54pe-r0/plugins/psuutil.py
Executable file
@ -0,0 +1,61 @@
|
||||
#!/usr/bin/env python
|
||||
|
||||
#############################################################################
|
||||
# Accton
|
||||
#
|
||||
# Module contains an implementation of SONiC PSU Base API and
|
||||
# provides the PSUs status which are available in the platform
|
||||
#
|
||||
#############################################################################
|
||||
|
||||
import os.path
|
||||
|
||||
try:
|
||||
from sonic_psu.psu_base import PsuBase
|
||||
except ImportError as e:
|
||||
raise ImportError (str(e) + "- required module not found")
|
||||
|
||||
class PsuUtil(PsuBase):
|
||||
"""Platform-specific PSUutil class"""
|
||||
|
||||
def __init__(self):
|
||||
PsuBase.__init__(self)
|
||||
|
||||
self.psu_path = "/sys/bus/i2c/devices/"
|
||||
self.psu_presence = "/psu_present"
|
||||
self.psu_oper_status = "/psu_power_good"
|
||||
self.psu_mapping = {
|
||||
1: "10-0050",
|
||||
2: "11-0051",
|
||||
}
|
||||
|
||||
def get_num_psus(self):
|
||||
return len(self.psu_mapping)
|
||||
|
||||
def get_psu_status(self, index):
|
||||
if index is None:
|
||||
return False
|
||||
|
||||
status = 0
|
||||
node = self.psu_path + self.psu_mapping[index]+self.psu_oper_status
|
||||
try:
|
||||
with open(node, 'r') as power_status:
|
||||
status = int(power_status.read())
|
||||
except IOError:
|
||||
return False
|
||||
|
||||
return status == 1
|
||||
|
||||
def get_psu_presence(self, index):
|
||||
if index is None:
|
||||
return False
|
||||
|
||||
status = 0
|
||||
node = self.psu_path + self.psu_mapping[index] + self.psu_presence
|
||||
try:
|
||||
with open(node, 'r') as presence_status:
|
||||
status = int(presence_status.read())
|
||||
except IOError:
|
||||
return False
|
||||
|
||||
return status == 1
|
||||
103
device/accton/x86_64-accton_as4630_54pe-r0/plugins/sfputil.py
Executable file
103
device/accton/x86_64-accton_as4630_54pe-r0/plugins/sfputil.py
Executable file
@ -0,0 +1,103 @@
|
||||
# sfputil.py
|
||||
#
|
||||
# Platform-specific SFP transceiver interface for SONiC
|
||||
#
|
||||
|
||||
try:
|
||||
import time
|
||||
from sonic_sfp.sfputilbase import SfpUtilBase
|
||||
except ImportError as e:
|
||||
raise ImportError("%s - required module not found" % str(e))
|
||||
|
||||
|
||||
class SfpUtil(SfpUtilBase):
|
||||
"""Platform-specific SfpUtil class"""
|
||||
|
||||
|
||||
PORT_START = 48
|
||||
PORT_END = 53
|
||||
PORTS_IN_BLOCK = 54
|
||||
|
||||
BASE_OOM_PATH = "/sys/bus/i2c/devices/{0}-0050/"
|
||||
BASE_CPLD_PATH = "/sys/bus/i2c/devices/3-0060/"
|
||||
|
||||
_port_to_is_present = {}
|
||||
_port_to_lp_mode = {}
|
||||
|
||||
_port_to_eeprom_mapping = {}
|
||||
_port_to_i2c_mapping = {
|
||||
48: [18],
|
||||
49: [19],
|
||||
50: [20],
|
||||
51: [21],
|
||||
52: [22],
|
||||
53: [23],
|
||||
}
|
||||
|
||||
@property
|
||||
def port_start(self):
|
||||
return self.PORT_START
|
||||
|
||||
@property
|
||||
def port_end(self):
|
||||
return self.PORT_END
|
||||
|
||||
@property
|
||||
def qsfp_ports(self):
|
||||
return range(self.PORT_START, self.PORTS_IN_BLOCK + 1)
|
||||
|
||||
@property
|
||||
def port_to_eeprom_mapping(self):
|
||||
return self._port_to_eeprom_mapping
|
||||
|
||||
def __init__(self):
|
||||
eeprom_path = self.BASE_OOM_PATH + "eeprom"
|
||||
|
||||
for x in range(0, self.port_end+1):
|
||||
if x < 48:
|
||||
self.port_to_eeprom_mapping[x] = eeprom_path.format(0)
|
||||
else:
|
||||
self.port_to_eeprom_mapping[x] = eeprom_path.format(
|
||||
self._port_to_i2c_mapping[x][0])
|
||||
|
||||
SfpUtilBase.__init__(self)
|
||||
|
||||
def get_presence(self, port_num):
|
||||
# Check for invalid port_num
|
||||
if port_num < self.port_start or port_num > self.port_end:
|
||||
return False
|
||||
|
||||
present_path = self.BASE_CPLD_PATH + "module_present_" + str(port_num+1)
|
||||
self.__port_to_is_present = present_path
|
||||
|
||||
try:
|
||||
val_file = open(self.__port_to_is_present)
|
||||
except IOError as e:
|
||||
print "Error: unable to open file: %s" % str(e)
|
||||
return False
|
||||
|
||||
content = val_file.readline().rstrip()
|
||||
val_file.close()
|
||||
|
||||
# content is a string, either "0" or "1"
|
||||
if content == "1":
|
||||
return True
|
||||
|
||||
return False
|
||||
|
||||
def get_low_power_mode(self, port_num):
|
||||
raise NotImplementedError
|
||||
|
||||
def set_low_power_mode(self, port_num, lpmode):
|
||||
raise NotImplementedError
|
||||
|
||||
def reset(self, port_num):
|
||||
raise NotImplementedError
|
||||
|
||||
def get_transceiver_change_event(self):
|
||||
"""
|
||||
TODO: This function need to be implemented
|
||||
when decide to support monitoring SFP(Xcvrd)
|
||||
on this platform.
|
||||
"""
|
||||
raise NotImplementedError
|
||||
Loading…
Reference in New Issue
Block a user