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[device/accton] Platform2.0 API Implementation for accton as7116-54x (#3622)

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Implement Component platform2.0 API for accton as7116-54x platform
This commit is contained in:
simonJi2018 2019-11-09 13:49:46 +08:00 committed by lguohan
parent 96fffd883d
commit b2e15f2318
37 changed files with 2711 additions and 866 deletions
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0
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/buffers.json.j2 → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/buffers.json.j2
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device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/buffers_defaults_t0.j2 → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/buffers_defaults_t0.j2
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device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/buffers_defaults_t1.j2 → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/buffers_defaults_t1.j2
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device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/led.bin Normal file
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device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/nephos_dac.dsh Normal file
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init start stage unit=0 low-level
init set port-map unit=0 port=0 eth-macro=2 lane=0 max-speed=25g active=true
init set port-map unit=0 port=1 eth-macro=2 lane=1 max-speed=25g active=true
init set port-map unit=0 port=2 eth-macro=2 lane=2 max-speed=25g active=true
init set port-map unit=0 port=3 eth-macro=2 lane=3 max-speed=25g active=true
init set port-map unit=0 port=4 eth-macro=3 lane=0 max-speed=25g active=true
init set port-map unit=0 port=5 eth-macro=3 lane=1 max-speed=25g active=true
init set port-map unit=0 port=6 eth-macro=3 lane=2 max-speed=25g active=true
init set port-map unit=0 port=7 eth-macro=3 lane=3 max-speed=25g active=true
init set port-map unit=0 port=8 eth-macro=4 lane=0 max-speed=25g active=true
init set port-map unit=0 port=9 eth-macro=4 lane=1 max-speed=25g active=true
init set port-map unit=0 port=10 eth-macro=4 lane=2 max-speed=25g active=true
init set port-map unit=0 port=11 eth-macro=4 lane=3 max-speed=25g active=true
init set port-map unit=0 port=12 eth-macro=5 lane=0 max-speed=25g active=true
init set port-map unit=0 port=13 eth-macro=5 lane=1 max-speed=25g active=true
init set port-map unit=0 port=14 eth-macro=5 lane=2 max-speed=25g active=true
init set port-map unit=0 port=15 eth-macro=5 lane=3 max-speed=25g active=true
init set port-map unit=0 port=16 eth-macro=8 lane=0 max-speed=25g active=true
init set port-map unit=0 port=17 eth-macro=8 lane=1 max-speed=25g active=true
init set port-map unit=0 port=18 eth-macro=8 lane=2 max-speed=25g active=true
init set port-map unit=0 port=19 eth-macro=8 lane=3 max-speed=25g active=true
init set port-map unit=0 port=20 eth-macro=10 lane=0 max-speed=25g active=true
init set port-map unit=0 port=21 eth-macro=10 lane=1 max-speed=25g active=true
init set port-map unit=0 port=22 eth-macro=10 lane=2 max-speed=25g active=true
init set port-map unit=0 port=23 eth-macro=10 lane=3 max-speed=25g active=true
init set port-map unit=0 port=24 eth-macro=12 lane=0 max-speed=25g active=true
init set port-map unit=0 port=25 eth-macro=12 lane=1 max-speed=25g active=true
init set port-map unit=0 port=26 eth-macro=12 lane=2 max-speed=25g active=true
init set port-map unit=0 port=27 eth-macro=12 lane=3 max-speed=25g active=true
init set port-map unit=0 port=28 eth-macro=14 lane=0 max-speed=25g active=true
init set port-map unit=0 port=29 eth-macro=14 lane=1 max-speed=25g active=true
init set port-map unit=0 port=30 eth-macro=14 lane=2 max-speed=25g active=true
init set port-map unit=0 port=31 eth-macro=14 lane=3 max-speed=25g active=true
init set port-map unit=0 port=32 eth-macro=16 lane=0 max-speed=25g active=true
init set port-map unit=0 port=33 eth-macro=16 lane=1 max-speed=25g active=true
init set port-map unit=0 port=34 eth-macro=16 lane=2 max-speed=25g active=true
init set port-map unit=0 port=35 eth-macro=16 lane=3 max-speed=25g active=true
init set port-map unit=0 port=36 eth-macro=17 lane=0 max-speed=25g active=true
init set port-map unit=0 port=37 eth-macro=17 lane=1 max-speed=25g active=true
init set port-map unit=0 port=38 eth-macro=17 lane=2 max-speed=25g active=true
init set port-map unit=0 port=39 eth-macro=17 lane=3 max-speed=25g active=true
init set port-map unit=0 port=40 eth-macro=18 lane=0 max-speed=25g active=true
init set port-map unit=0 port=41 eth-macro=18 lane=1 max-speed=25g active=true
init set port-map unit=0 port=42 eth-macro=18 lane=2 max-speed=25g active=true
init set port-map unit=0 port=43 eth-macro=18 lane=3 max-speed=25g active=true
init set port-map unit=0 port=44 eth-macro=19 lane=0 max-speed=25g active=true
init set port-map unit=0 port=45 eth-macro=19 lane=1 max-speed=25g active=true
init set port-map unit=0 port=46 eth-macro=19 lane=2 max-speed=25g active=true
init set port-map unit=0 port=47 eth-macro=19 lane=3 max-speed=25g active=true
init set port-map unit=0 port=48 eth-macro=21 lane=0 max-speed=100g active=true
init set port-map unit=0 port=49 eth-macro=20 lane=0 max-speed=100g active=true
init set port-map unit=0 port=50 eth-macro=26 lane=0 max-speed=100g active=true
init set port-map unit=0 port=51 eth-macro=27 lane=0 max-speed=100g active=true
init set port-map unit=0 port=52 eth-macro=28 lane=0 max-speed=100g active=true
init set port-map unit=0 port=53 eth-macro=29 lane=0 max-speed=100g active=true
init set port-map unit=0 port=129 eth-macro=0 lane=1 max-speed=10g active=true guarantee=true cpi=true
init set port-map unit=0 port=130 eth-macro=0 lane=0 max-speed=10g active=true guarantee=true cpi=true init-done=true
init start stage unit=0 task-rsrc
init start stage unit=0 module
init start stage unit=0 task
phy set lane-swap unit=0 portlist=0 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=1 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=2 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=3 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=4 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=5 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=6 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=7 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=8 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=9 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=10 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=11 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=12 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=13 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=14 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=15 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=16 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=17 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=18 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=19 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=20 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=21 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=22 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=23 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=24 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=25 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=26 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=27 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=28 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=29 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=30 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=31 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=32 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=33 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=34 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=35 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=36 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=37 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=38 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=39 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=40 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=41 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=42 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=43 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=44 lane-cnt=1 property=tx data=0x0
phy set lane-swap unit=0 portlist=45 lane-cnt=1 property=tx data=0x1
phy set lane-swap unit=0 portlist=46 lane-cnt=1 property=tx data=0x2
phy set lane-swap unit=0 portlist=47 lane-cnt=1 property=tx data=0x3
phy set lane-swap unit=0 portlist=48 lane-cnt=4 property=tx data=0x1.3.0.2
phy set lane-swap unit=0 portlist=49 lane-cnt=4 property=tx data=0x0.3.1.2
phy set lane-swap unit=0 portlist=50 lane-cnt=4 property=tx data=0x1.3.0.2
phy set lane-swap unit=0 portlist=51 lane-cnt=4 property=tx data=0x2.0.3.1
phy set lane-swap unit=0 portlist=52 lane-cnt=4 property=tx data=0x3.2.1.0
phy set lane-swap unit=0 portlist=53 lane-cnt=4 property=tx data=0x3.2.1.0
phy set lane-swap unit=0 portlist=0 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=1 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=2 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=3 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=4 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=5 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=6 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=7 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=8 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=9 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=10 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=11 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=12 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=13 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=14 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=15 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=16 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=17 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=18 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=19 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=20 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=21 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=22 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=23 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=24 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=25 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=26 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=27 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=28 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=29 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=30 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=31 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=32 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=33 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=34 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=35 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=36 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=37 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=38 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=39 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=40 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=41 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=42 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=43 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=44 lane-cnt=1 property=rx data=0x1
phy set lane-swap unit=0 portlist=45 lane-cnt=1 property=rx data=0x2
phy set lane-swap unit=0 portlist=46 lane-cnt=1 property=rx data=0x3
phy set lane-swap unit=0 portlist=47 lane-cnt=1 property=rx data=0x0
phy set lane-swap unit=0 portlist=48 lane-cnt=4 property=rx data=0x2.1.0.3
phy set lane-swap unit=0 portlist=49 lane-cnt=4 property=rx data=0x0.1.3.2
phy set lane-swap unit=0 portlist=50 lane-cnt=4 property=rx data=0x3.1.0.2
phy set lane-swap unit=0 portlist=51 lane-cnt=4 property=rx data=0x1.3.0.2
phy set lane-swap unit=0 portlist=52 lane-cnt=4 property=rx data=0x3.2.1.0
phy set lane-swap unit=0 portlist=53 lane-cnt=4 property=rx data=0x3.2.1.0
phy set polarity-rev unit=0 portlist=0 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=1 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=2 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=3 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=4 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=5 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=6 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=7 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=8 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=9 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=10 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=11 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=12 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=13 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=14 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=15 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=16 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=17 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=18 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=19 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=20 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=21 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=22 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=23 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=24 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=25 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=26 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=27 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=28 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=29 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=30 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=31 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=32 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=33 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=34 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=35 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=36 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=37 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=38 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=39 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=40 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=41 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=42 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=43 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=44 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=45 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=46 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=47 lane-cnt=1 property=tx data=0x0
phy set polarity-rev unit=0 portlist=48 lane-cnt=4 property=tx data=0x0.0.0.1
phy set polarity-rev unit=0 portlist=49 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev unit=0 portlist=50 lane-cnt=4 property=tx data=0x1.1.0.0
phy set polarity-rev unit=0 portlist=51 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev unit=0 portlist=52 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev unit=0 portlist=53 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev unit=0 portlist=0 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=1 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=2 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=3 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=4 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=5 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=6 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=7 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=8 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=9 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=10 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=11 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=12 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=13 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=14 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=15 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=16 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=17 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=18 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=19 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=20 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=21 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=22 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=23 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=24 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=25 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=26 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=27 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=28 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=29 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=30 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=31 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=32 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=33 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=34 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=35 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=36 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=37 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=38 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=39 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=40 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=41 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=42 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=43 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=44 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=45 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=46 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=47 lane-cnt=1 property=rx data=0x0
phy set polarity-rev unit=0 portlist=48 lane-cnt=4 property=rx data=0x0.1.0.1
phy set polarity-rev unit=0 portlist=49 lane-cnt=4 property=rx data=0x1.0.1.0
phy set polarity-rev unit=0 portlist=50 lane-cnt=4 property=rx data=0x0.0.1.0
phy set polarity-rev unit=0 portlist=51 lane-cnt=4 property=rx data=0x0.0.0.1
phy set polarity-rev unit=0 portlist=52 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev unit=0 portlist=53 lane-cnt=4 property=rx data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=0 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=0 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=0 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=0 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=4 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=4 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=4 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=4 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=8 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=8 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=8 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=8 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=12 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=12 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=12 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=12 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=16 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=16 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=16 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=16 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=20 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=20 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=20 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=20 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=24 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=24 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=24 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=24 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=28 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=28 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=28 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=28 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=32 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=32 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=32 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=32 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=36 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=36 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=36 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=36 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=40 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=40 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=40 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=40 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=44 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=44 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=44 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=44 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=48 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=48 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=48 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=48 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=49 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=49 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=49 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=49 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=50 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=50 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=50 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=50 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=51 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=51 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=51 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=51 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=52 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=52 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=52 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=52 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis unit=0 portlist=53 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis unit=0 portlist=53 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis unit=0 portlist=53 lane-cnt=4 property=c0 data=0x1e.1e.1e.1e
phy set pre-emphasis unit=0 portlist=53 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set mdio portlist=0 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=1 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=2 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=3 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=4 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=5 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=6 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=7 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=8 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=9 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=10 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=11 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=12 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=13 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=14 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=15 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=16 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=17 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=18 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=19 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=20 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=21 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=22 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=23 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=24 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=25 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=26 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=27 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=28 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=29 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=30 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=31 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=32 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=33 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=34 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=35 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=36 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=37 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=38 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=39 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=40 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=41 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=42 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=43 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=44 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=45 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=46 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=47 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=48 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=49 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=50 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=51 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=52 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=53 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=129 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=130 devad=0x1E addr=0x2 data=0x0000
port set property unit=0 portlist=0-47 speed=25g
port set property unit=0 portlist=48-53 speed=100g
port set property unit=0 portlist=129-130 speed=10g
port set property unit=0 portlist=0-47 medium-type=cr
port set property unit=0 portlist=48-53 medium-type=cr4
port set property unit=0 portlist=129-130 medium-type=kr
port set adver unit=0 portlist=129-130 speed-10g-kr
port set property unit=0 portlist=129-130 an=enable
port set property unit=0 portlist=129-130 admin=enable
port set property unit=0 portlist=0-53 admin=disable

187
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/nephos_opt.dsh → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/nephos_opt.dsh
View File

@ -1,63 +1,63 @@
init start stage low-level
init set port-map port=0 eth-macro=2 lane=0 max-speed=25g active=true
init set port-map port=1 eth-macro=2 lane=1 max-speed=25g active=true
init set port-map port=2 eth-macro=2 lane=2 max-speed=25g active=true
init set port-map port=3 eth-macro=2 lane=3 max-speed=25g active=true
init set port-map port=4 eth-macro=3 lane=0 max-speed=25g active=true
init set port-map port=5 eth-macro=3 lane=1 max-speed=25g active=true
init set port-map port=6 eth-macro=3 lane=2 max-speed=25g active=true
init set port-map port=7 eth-macro=3 lane=3 max-speed=25g active=true
init set port-map port=8 eth-macro=4 lane=0 max-speed=25g active=true
init set port-map port=9 eth-macro=4 lane=1 max-speed=25g active=true
init set port-map port=10 eth-macro=4 lane=2 max-speed=25g active=true
init set port-map port=11 eth-macro=4 lane=3 max-speed=25g active=true
init set port-map port=12 eth-macro=5 lane=0 max-speed=25g active=true
init set port-map port=13 eth-macro=5 lane=1 max-speed=25g active=true
init set port-map port=14 eth-macro=5 lane=2 max-speed=25g active=true
init set port-map port=15 eth-macro=5 lane=3 max-speed=25g active=true
init set port-map port=16 eth-macro=8 lane=0 max-speed=25g active=true
init set port-map port=17 eth-macro=8 lane=1 max-speed=25g active=true
init set port-map port=18 eth-macro=8 lane=2 max-speed=25g active=true
init set port-map port=19 eth-macro=8 lane=3 max-speed=25g active=true
init set port-map port=20 eth-macro=10 lane=0 max-speed=25g active=true
init set port-map port=21 eth-macro=10 lane=1 max-speed=25g active=true
init set port-map port=22 eth-macro=10 lane=2 max-speed=25g active=true
init set port-map port=23 eth-macro=10 lane=3 max-speed=25g active=true
init set port-map port=24 eth-macro=12 lane=0 max-speed=25g active=true
init set port-map port=25 eth-macro=12 lane=1 max-speed=25g active=true
init set port-map port=26 eth-macro=12 lane=2 max-speed=25g active=true
init set port-map port=27 eth-macro=12 lane=3 max-speed=25g active=true
init set port-map port=28 eth-macro=14 lane=0 max-speed=25g active=true
init set port-map port=29 eth-macro=14 lane=1 max-speed=25g active=true
init set port-map port=30 eth-macro=14 lane=2 max-speed=25g active=true
init set port-map port=31 eth-macro=14 lane=3 max-speed=25g active=true
init set port-map port=32 eth-macro=16 lane=0 max-speed=25g active=true
init set port-map port=33 eth-macro=16 lane=1 max-speed=25g active=true
init set port-map port=34 eth-macro=16 lane=2 max-speed=25g active=true
init set port-map port=35 eth-macro=16 lane=3 max-speed=25g active=true
init set port-map port=36 eth-macro=17 lane=0 max-speed=25g active=true
init set port-map port=37 eth-macro=17 lane=1 max-speed=25g active=true
init set port-map port=38 eth-macro=17 lane=2 max-speed=25g active=true
init set port-map port=39 eth-macro=17 lane=3 max-speed=25g active=true
init set port-map port=40 eth-macro=18 lane=0 max-speed=25g active=true
init set port-map port=41 eth-macro=18 lane=1 max-speed=25g active=true
init set port-map port=42 eth-macro=18 lane=2 max-speed=25g active=true
init set port-map port=43 eth-macro=18 lane=3 max-speed=25g active=true
init set port-map port=44 eth-macro=19 lane=0 max-speed=25g active=true
init set port-map port=45 eth-macro=19 lane=1 max-speed=25g active=true
init set port-map port=46 eth-macro=19 lane=2 max-speed=25g active=true
init set port-map port=47 eth-macro=19 lane=3 max-speed=25g active=true
init set port-map port=48 eth-macro=20 lane=0 max-speed=100g active=true
init set port-map port=49 eth-macro=21 lane=0 max-speed=100g active=true
init set port-map port=50 eth-macro=26 lane=0 max-speed=100g active=true
init set port-map port=51 eth-macro=27 lane=0 max-speed=100g active=true
init set port-map port=52 eth-macro=28 lane=0 max-speed=100g active=true
init set port-map port=53 eth-macro=29 lane=0 max-speed=100g active=true
init set port-map port=129 eth-macro=0 lane=1 max-speed=10g active=true guarantee=true cpi=true
init set port-map port=130 eth-macro=0 lane=0 max-speed=10g active=true guarantee=true cpi=true init-done=true
init start stage task-rsrc
init start stage module
init start stage task
init start stage unit=0 low-level
init set port-map unit=0 port=0 eth-macro=2 lane=0 max-speed=25g active=true
init set port-map unit=0 port=1 eth-macro=2 lane=1 max-speed=25g active=true
init set port-map unit=0 port=2 eth-macro=2 lane=2 max-speed=25g active=true
init set port-map unit=0 port=3 eth-macro=2 lane=3 max-speed=25g active=true
init set port-map unit=0 port=4 eth-macro=3 lane=0 max-speed=25g active=true
init set port-map unit=0 port=5 eth-macro=3 lane=1 max-speed=25g active=true
init set port-map unit=0 port=6 eth-macro=3 lane=2 max-speed=25g active=true
init set port-map unit=0 port=7 eth-macro=3 lane=3 max-speed=25g active=true
init set port-map unit=0 port=8 eth-macro=4 lane=0 max-speed=25g active=true
init set port-map unit=0 port=9 eth-macro=4 lane=1 max-speed=25g active=true
init set port-map unit=0 port=10 eth-macro=4 lane=2 max-speed=25g active=true
init set port-map unit=0 port=11 eth-macro=4 lane=3 max-speed=25g active=true
init set port-map unit=0 port=12 eth-macro=5 lane=0 max-speed=25g active=true
init set port-map unit=0 port=13 eth-macro=5 lane=1 max-speed=25g active=true
init set port-map unit=0 port=14 eth-macro=5 lane=2 max-speed=25g active=true
init set port-map unit=0 port=15 eth-macro=5 lane=3 max-speed=25g active=true
init set port-map unit=0 port=16 eth-macro=8 lane=0 max-speed=25g active=true
init set port-map unit=0 port=17 eth-macro=8 lane=1 max-speed=25g active=true
init set port-map unit=0 port=18 eth-macro=8 lane=2 max-speed=25g active=true
init set port-map unit=0 port=19 eth-macro=8 lane=3 max-speed=25g active=true
init set port-map unit=0 port=20 eth-macro=10 lane=0 max-speed=25g active=true
init set port-map unit=0 port=21 eth-macro=10 lane=1 max-speed=25g active=true
init set port-map unit=0 port=22 eth-macro=10 lane=2 max-speed=25g active=true
init set port-map unit=0 port=23 eth-macro=10 lane=3 max-speed=25g active=true
init set port-map unit=0 port=24 eth-macro=12 lane=0 max-speed=25g active=true
init set port-map unit=0 port=25 eth-macro=12 lane=1 max-speed=25g active=true
init set port-map unit=0 port=26 eth-macro=12 lane=2 max-speed=25g active=true
init set port-map unit=0 port=27 eth-macro=12 lane=3 max-speed=25g active=true
init set port-map unit=0 port=28 eth-macro=14 lane=0 max-speed=25g active=true
init set port-map unit=0 port=29 eth-macro=14 lane=1 max-speed=25g active=true
init set port-map unit=0 port=30 eth-macro=14 lane=2 max-speed=25g active=true
init set port-map unit=0 port=31 eth-macro=14 lane=3 max-speed=25g active=true
init set port-map unit=0 port=32 eth-macro=16 lane=0 max-speed=25g active=true
init set port-map unit=0 port=33 eth-macro=16 lane=1 max-speed=25g active=true
init set port-map unit=0 port=34 eth-macro=16 lane=2 max-speed=25g active=true
init set port-map unit=0 port=35 eth-macro=16 lane=3 max-speed=25g active=true
init set port-map unit=0 port=36 eth-macro=17 lane=0 max-speed=25g active=true
init set port-map unit=0 port=37 eth-macro=17 lane=1 max-speed=25g active=true
init set port-map unit=0 port=38 eth-macro=17 lane=2 max-speed=25g active=true
init set port-map unit=0 port=39 eth-macro=17 lane=3 max-speed=25g active=true
init set port-map unit=0 port=40 eth-macro=18 lane=0 max-speed=25g active=true
init set port-map unit=0 port=41 eth-macro=18 lane=1 max-speed=25g active=true
init set port-map unit=0 port=42 eth-macro=18 lane=2 max-speed=25g active=true
init set port-map unit=0 port=43 eth-macro=18 lane=3 max-speed=25g active=true
init set port-map unit=0 port=44 eth-macro=19 lane=0 max-speed=25g active=true
init set port-map unit=0 port=45 eth-macro=19 lane=1 max-speed=25g active=true
init set port-map unit=0 port=46 eth-macro=19 lane=2 max-speed=25g active=true
init set port-map unit=0 port=47 eth-macro=19 lane=3 max-speed=25g active=true
init set port-map unit=0 port=48 eth-macro=21 lane=0 max-speed=100g active=true
init set port-map unit=0 port=49 eth-macro=20 lane=0 max-speed=100g active=true
init set port-map unit=0 port=50 eth-macro=26 lane=0 max-speed=100g active=true
init set port-map unit=0 port=51 eth-macro=27 lane=0 max-speed=100g active=true
init set port-map unit=0 port=52 eth-macro=28 lane=0 max-speed=100g active=true
init set port-map unit=0 port=53 eth-macro=29 lane=0 max-speed=100g active=true
init set port-map unit=0 port=129 eth-macro=0 lane=1 max-speed=10g active=true guarantee=true cpi=true
init set port-map unit=0 port=130 eth-macro=0 lane=0 max-speed=10g active=true guarantee=true cpi=true init-done=true
init start stage unit=0 task-rsrc
init start stage unit=0 module
init start stage unit=0 task
phy set lane-swap portlist=0 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=1 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=2 lane-cnt=1 property=tx data=0x2
@ -106,7 +106,12 @@ phy set lane-swap portlist=44 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=45 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=46 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=47 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=48-53 lane-cnt=4 property=tx data=0x03.02.01.00
phy set lane-swap portlist=48 lane-cnt=4 property=tx data=0x1.3.0.2
phy set lane-swap portlist=49 lane-cnt=4 property=tx data=0x0.3.1.2
phy set lane-swap portlist=50 lane-cnt=4 property=tx data=0x1.3.0.2
phy set lane-swap portlist=51 lane-cnt=4 property=tx data=0x2.0.3.1
phy set lane-swap portlist=52 lane-cnt=4 property=tx data=0x3.2.1.0
phy set lane-swap portlist=53 lane-cnt=4 property=tx data=0x3.2.1.0
phy set lane-swap portlist=0 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=1 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=2 lane-cnt=1 property=rx data=0x2
@ -155,7 +160,12 @@ phy set lane-swap portlist=44 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=45 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=46 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=47 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=48-53 lane-cnt=4 property=rx data=0x03.02.01.00
phy set lane-swap portlist=48 lane-cnt=4 property=rx data=0x2.1.0.3
phy set lane-swap portlist=49 lane-cnt=4 property=rx data=0x0.1.3.2
phy set lane-swap portlist=50 lane-cnt=4 property=rx data=0x3.1.0.2
phy set lane-swap portlist=51 lane-cnt=4 property=rx data=0x1.3.0.2
phy set lane-swap portlist=52 lane-cnt=4 property=rx data=0x3.2.1.0
phy set lane-swap portlist=53 lane-cnt=4 property=rx data=0x3.2.1.0
phy set polarity-rev portlist=0 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=1 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=2 lane-cnt=1 property=tx data=0x0
@ -204,9 +214,9 @@ phy set polarity-rev portlist=44 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=45 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=46 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=47 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=48 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=48 lane-cnt=4 property=tx data=0x0.0.0.1
phy set polarity-rev portlist=49 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=50 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=50 lane-cnt=4 property=tx data=0x1.1.0.0
phy set polarity-rev portlist=51 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=52 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=53 lane-cnt=4 property=tx data=0x0.0.0.0
@ -258,83 +268,83 @@ phy set polarity-rev portlist=44 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=45 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=46 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=47 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=48 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=49 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=50 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=51 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=48 lane-cnt=4 property=rx data=0x0.1.0.1
phy set polarity-rev portlist=49 lane-cnt=4 property=rx data=0x1.0.1.0
phy set polarity-rev portlist=50 lane-cnt=4 property=rx data=0x0.0.1.0
phy set polarity-rev portlist=51 lane-cnt=4 property=rx data=0x0.0.0.1
phy set polarity-rev portlist=52 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=53 lane-cnt=4 property=rx data=0x0.0.0.0
phy set pre-emphasis portlist=0 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=0 lane-cnt=4 property=cn1 data=0x1.1.1.1
phy set pre-emphasis portlist=0 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
phy set pre-emphasis portlist=0 lane-cnt=4 property=c0 data=0x1a.1a.1a.1a
phy set pre-emphasis portlist=0 lane-cnt=4 property=c1 data=0x7.7.7.7
phy set pre-emphasis portlist=4 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=4 lane-cnt=4 property=cn1 data=0x1.1.1.1
phy set pre-emphasis portlist=4 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
phy set pre-emphasis portlist=4 lane-cnt=4 property=c0 data=0x1a.1a.1a.1a
phy set pre-emphasis portlist=4 lane-cnt=4 property=c1 data=0x7.7.7.7
phy set pre-emphasis portlist=8 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=8 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=8 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=8 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=8 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=12 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=12 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=12 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
phy set pre-emphasis portlist=12 lane-cnt=4 property=c0 data=0x1b.1b.1b.1b
phy set pre-emphasis portlist=12 lane-cnt=4 property=c1 data=0x7.7.7.7
phy set pre-emphasis portlist=16 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=16 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=16 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=16 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=16 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=20 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=20 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=20 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=20 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=20 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=24 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=24 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=24 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=24 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=24 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=28 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=28 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=28 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=28 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=28 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=32 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=32 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=32 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=32 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=32 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=36 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=36 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=36 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=36 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=36 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=40 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=40 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=40 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=40 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=40 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=44 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=44 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=44 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
phy set pre-emphasis portlist=44 lane-cnt=4 property=c0 data=0x1c.1c.1c.1c
phy set pre-emphasis portlist=44 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=48 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=48 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=48 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
phy set pre-emphasis portlist=48 lane-cnt=4 property=c0 data=0x1b.1b.1b.1b
phy set pre-emphasis portlist=48 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=49 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=49 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=49 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
phy set pre-emphasis portlist=49 lane-cnt=4 property=c0 data=0x1b.1b.1b.1b
phy set pre-emphasis portlist=49 lane-cnt=4 property=c1 data=0x6.6.6.6
phy set pre-emphasis portlist=50 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=50 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=50 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
phy set pre-emphasis portlist=50 lane-cnt=4 property=c0 data=0x1b.1b.1b.1b
phy set pre-emphasis portlist=50 lane-cnt=4 property=c1 data=0x7.7.7.7
phy set pre-emphasis portlist=51 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=51 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=51 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
phy set pre-emphasis portlist=51 lane-cnt=4 property=c0 data=0x1b.1b.1b.1b
phy set pre-emphasis portlist=51 lane-cnt=4 property=c1 data=0x7.7.7.7
phy set pre-emphasis portlist=52 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=52 lane-cnt=4 property=cn1 data=0x0.0.0.0
phy set pre-emphasis portlist=52 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
phy set pre-emphasis portlist=52 lane-cnt=4 property=c0 data=0x1a.1a.1a.1a
phy set pre-emphasis portlist=52 lane-cnt=4 property=c1 data=0x8.8.8.8
phy set pre-emphasis portlist=53 lane-cnt=4 property=c2 data=0x2.2.2.2
phy set pre-emphasis portlist=53 lane-cnt=4 property=cn1 data=0x1.1.1.1
phy set pre-emphasis portlist=53 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
phy set pre-emphasis portlist=53 lane-cnt=4 property=c0 data=0x1a.1a.1a.1a
phy set pre-emphasis portlist=53 lane-cnt=4 property=c1 data=0x7.7.7.7
phy set mdio portlist=0 devad=0x1E addr=0x2 data=0x8000
phy set mdio portlist=1 devad=0x1E addr=0x2 data=0x8000
@ -400,5 +410,6 @@ port set property portlist=48-53 medium-type=sr4
port set property portlist=129-130 medium-type=kr
port set adver portlist=129-130 speed-10g-kr
port set property portlist=129-130 an=enable
port set property portlist=129-130 admin=enable
port set property portlist=0-53 admin=disable
port set property unit=0 portlist=129-130 admin=enable
port set property unit=0 portlist=0-53 admin=disable

0
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/pg_profile_lookup.ini → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/pg_profile_lookup.ini
View File

0
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/port_config.ini → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/port_config.ini
View File

1
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/port_config.nps → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/port_config.nps
View File

@ -412,3 +412,4 @@ port set adver portlist=129-130 speed-10g-kr
port set property portlist=129-130 an=enable
port set property unit=0 portlist=129-130 admin=enable
port set property unit=0 portlist=0-53 admin=disable

0
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/proc_init.nps → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/proc_init.nps
View File

0
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/qos.json.j2 → device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/qos.json.j2
View File

2
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X-R0/sai.profile Normal file
View File

@ -0,0 +1,2 @@
SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/proc_init.nps
SAI_DSH_CONFIG_FILE=/usr/share/sonic/hwsku/port_config.nps

404
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/nephos_dac.dsh
View File

@ -1,404 +0,0 @@
init start stage low-level
init set port-map port=0 eth-macro=2 lane=0 max-speed=25g active=true
init set port-map port=1 eth-macro=2 lane=1 max-speed=25g active=true
init set port-map port=2 eth-macro=2 lane=2 max-speed=25g active=true
init set port-map port=3 eth-macro=2 lane=3 max-speed=25g active=true
init set port-map port=4 eth-macro=3 lane=0 max-speed=25g active=true
init set port-map port=5 eth-macro=3 lane=1 max-speed=25g active=true
init set port-map port=6 eth-macro=3 lane=2 max-speed=25g active=true
init set port-map port=7 eth-macro=3 lane=3 max-speed=25g active=true
init set port-map port=8 eth-macro=4 lane=0 max-speed=25g active=true
init set port-map port=9 eth-macro=4 lane=1 max-speed=25g active=true
init set port-map port=10 eth-macro=4 lane=2 max-speed=25g active=true
init set port-map port=11 eth-macro=4 lane=3 max-speed=25g active=true
init set port-map port=12 eth-macro=5 lane=0 max-speed=25g active=true
init set port-map port=13 eth-macro=5 lane=1 max-speed=25g active=true
init set port-map port=14 eth-macro=5 lane=2 max-speed=25g active=true
init set port-map port=15 eth-macro=5 lane=3 max-speed=25g active=true
init set port-map port=16 eth-macro=8 lane=0 max-speed=25g active=true
init set port-map port=17 eth-macro=8 lane=1 max-speed=25g active=true
init set port-map port=18 eth-macro=8 lane=2 max-speed=25g active=true
init set port-map port=19 eth-macro=8 lane=3 max-speed=25g active=true
init set port-map port=20 eth-macro=10 lane=0 max-speed=25g active=true
init set port-map port=21 eth-macro=10 lane=1 max-speed=25g active=true
init set port-map port=22 eth-macro=10 lane=2 max-speed=25g active=true
init set port-map port=23 eth-macro=10 lane=3 max-speed=25g active=true
init set port-map port=24 eth-macro=12 lane=0 max-speed=25g active=true
init set port-map port=25 eth-macro=12 lane=1 max-speed=25g active=true
init set port-map port=26 eth-macro=12 lane=2 max-speed=25g active=true
init set port-map port=27 eth-macro=12 lane=3 max-speed=25g active=true
init set port-map port=28 eth-macro=14 lane=0 max-speed=25g active=true
init set port-map port=29 eth-macro=14 lane=1 max-speed=25g active=true
init set port-map port=30 eth-macro=14 lane=2 max-speed=25g active=true
init set port-map port=31 eth-macro=14 lane=3 max-speed=25g active=true
init set port-map port=32 eth-macro=16 lane=0 max-speed=25g active=true
init set port-map port=33 eth-macro=16 lane=1 max-speed=25g active=true
init set port-map port=34 eth-macro=16 lane=2 max-speed=25g active=true
init set port-map port=35 eth-macro=16 lane=3 max-speed=25g active=true
init set port-map port=36 eth-macro=17 lane=0 max-speed=25g active=true
init set port-map port=37 eth-macro=17 lane=1 max-speed=25g active=true
init set port-map port=38 eth-macro=17 lane=2 max-speed=25g active=true
init set port-map port=39 eth-macro=17 lane=3 max-speed=25g active=true
init set port-map port=40 eth-macro=18 lane=0 max-speed=25g active=true
init set port-map port=41 eth-macro=18 lane=1 max-speed=25g active=true
init set port-map port=42 eth-macro=18 lane=2 max-speed=25g active=true
init set port-map port=43 eth-macro=18 lane=3 max-speed=25g active=true
init set port-map port=44 eth-macro=19 lane=0 max-speed=25g active=true
init set port-map port=45 eth-macro=19 lane=1 max-speed=25g active=true
init set port-map port=46 eth-macro=19 lane=2 max-speed=25g active=true
init set port-map port=47 eth-macro=19 lane=3 max-speed=25g active=true
init set port-map port=48 eth-macro=20 lane=0 max-speed=100g active=true
init set port-map port=49 eth-macro=21 lane=0 max-speed=100g active=true
init set port-map port=50 eth-macro=26 lane=0 max-speed=100g active=true
init set port-map port=51 eth-macro=27 lane=0 max-speed=100g active=true
init set port-map port=52 eth-macro=28 lane=0 max-speed=100g active=true
init set port-map port=53 eth-macro=29 lane=0 max-speed=100g active=true
init set port-map port=129 eth-macro=0 lane=1 max-speed=10g active=true guarantee=true cpi=true
init set port-map port=130 eth-macro=0 lane=0 max-speed=10g active=true guarantee=true cpi=true init-done=true
init start stage task-rsrc
init start stage module
init start stage task
phy set lane-swap portlist=0 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=1 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=2 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=3 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=4 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=5 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=6 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=7 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=8 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=9 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=10 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=11 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=12 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=13 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=14 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=15 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=16 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=17 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=18 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=19 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=20 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=21 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=22 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=23 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=24 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=25 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=26 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=27 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=28 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=29 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=30 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=31 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=32 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=33 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=34 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=35 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=36 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=37 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=38 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=39 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=40 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=41 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=42 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=43 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=44 lane-cnt=1 property=tx data=0x0
phy set lane-swap portlist=45 lane-cnt=1 property=tx data=0x1
phy set lane-swap portlist=46 lane-cnt=1 property=tx data=0x2
phy set lane-swap portlist=47 lane-cnt=1 property=tx data=0x3
phy set lane-swap portlist=48-53 lane-cnt=4 property=tx data=0x03.02.01.00
phy set lane-swap portlist=0 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=1 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=2 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=3 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=4 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=5 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=6 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=7 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=8 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=9 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=10 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=11 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=12 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=13 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=14 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=15 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=16 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=17 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=18 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=19 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=20 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=21 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=22 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=23 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=24 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=25 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=26 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=27 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=28 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=29 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=30 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=31 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=32 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=33 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=34 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=35 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=36 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=37 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=38 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=39 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=40 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=41 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=42 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=43 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=44 lane-cnt=1 property=rx data=0x1
phy set lane-swap portlist=45 lane-cnt=1 property=rx data=0x2
phy set lane-swap portlist=46 lane-cnt=1 property=rx data=0x3
phy set lane-swap portlist=47 lane-cnt=1 property=rx data=0x0
phy set lane-swap portlist=48-53 lane-cnt=4 property=rx data=0x03.02.01.00
phy set polarity-rev portlist=0 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=1 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=2 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=3 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=4 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=5 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=6 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=7 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=8 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=9 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=10 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=11 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=12 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=13 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=14 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=15 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=16 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=17 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=18 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=19 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=20 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=21 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=22 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=23 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=24 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=25 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=26 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=27 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=28 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=29 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=30 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=31 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=32 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=33 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=34 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=35 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=36 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=37 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=38 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=39 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=40 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=41 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=42 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=43 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=44 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=45 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=46 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=47 lane-cnt=1 property=tx data=0x0
phy set polarity-rev portlist=48 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=49 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=50 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=51 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=52 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=53 lane-cnt=4 property=tx data=0x0.0.0.0
phy set polarity-rev portlist=0 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=1 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=2 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=3 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=4 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=5 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=6 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=7 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=8 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=9 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=10 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=11 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=12 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=13 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=14 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=15 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=16 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=17 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=18 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=19 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=20 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=21 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=22 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=23 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=24 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=25 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=26 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=27 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=28 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=29 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=30 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=31 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=32 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=33 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=34 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=35 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=36 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=37 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=38 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=39 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=40 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=41 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=42 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=43 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=44 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=45 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=46 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=47 lane-cnt=1 property=rx data=0x0
phy set polarity-rev portlist=48 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=49 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=50 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=51 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=52 lane-cnt=4 property=rx data=0x0.0.0.0
phy set polarity-rev portlist=53 lane-cnt=4 property=rx data=0x0.0.0.0
phy set pre-emphasis portlist=0 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=0 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=0 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=0 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=4 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=4 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=4 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=4 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=8 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=8 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=8 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=8 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=12 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=12 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=12 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=12 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=16 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=16 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=16 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=16 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=20 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=20 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=20 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=20 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=24 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=24 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=24 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=24 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=28 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=28 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=28 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=28 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=32 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=32 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=32 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=32 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=36 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=36 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=36 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=36 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=40 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=40 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=40 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=40 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=44 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=44 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=44 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=44 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=48 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=48 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=48 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=48 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=49 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=49 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=49 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=49 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=50 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=50 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=50 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=50 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=51 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=51 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=51 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=51 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=52 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=52 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=52 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=52 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set pre-emphasis portlist=53 lane-cnt=4 property=c2 data=0x0.0.0.0
phy set pre-emphasis portlist=53 lane-cnt=4 property=cn1 data=0x4.4.4.4
phy set pre-emphasis portlist=53 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
phy set pre-emphasis portlist=53 lane-cnt=4 property=c1 data=0x2.2.2.2
phy set mdio portlist=0 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=1 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=2 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=3 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=4 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=5 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=6 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=7 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=8 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=9 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=10 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=11 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=12 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=13 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=14 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=15 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=16 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=17 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=18 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=19 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=20 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=21 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=22 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=23 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=24 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=25 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=26 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=27 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=28 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=29 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=30 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=31 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=32 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=33 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=34 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=35 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=36 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=37 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=38 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=39 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=40 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=41 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=42 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=43 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=44 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=45 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=46 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=47 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=48 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=49 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=50 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=51 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=52 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=53 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=129 devad=0x1E addr=0x2 data=0x0000
phy set mdio portlist=130 devad=0x1E addr=0x2 data=0x0000
port set property portlist=0-47 speed=25g
port set property portlist=48-53 speed=100g
port set property portlist=129-130 speed=10g
port set property portlist=0-47 medium-type=cr
port set property portlist=48-53 medium-type=cr4
port set property portlist=129-130 medium-type=kr
port set adver portlist=129-130 speed-10g-kr
port set property portlist=129-130 an=enable
port set property portlist=129-130 admin=enable
port set property portlist=0-53 admin=disable

2
device/accton/x86_64-accton_as7116_54x-r0/Accton-AS7116-54X/sai.profile
View File

@ -1,2 +0,0 @@
SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/proc_init.nps
SAI_DSH_CONFIG_FILE=/usr/share/sonic/hwsku/port_config.nps

2
device/accton/x86_64-accton_as7116_54x-r0/default_sku
View File

@ -1 +1 @@
Accton-AS7116-54X t1
Accton-AS7116-54X-R0 t1

1
device/accton/x86_64-accton_as7116_54x-r0/plugins/sfputil.py
View File

@ -169,3 +169,4 @@ class SfpUtil(SfpUtilBase):
time.sleep(2)
return True, ret_present

2
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/__init__.py Normal file
View File

@ -0,0 +1,2 @@
__all__ = ["platform", "chassis"]
from sonic_platform import *

174
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/chassis.py Normal file
View File

@ -0,0 +1,174 @@
#!/usr/bin/env python
#############################################################################
#
# Module contains an implementation of SONiC Platform Base API and
# provides the Chassis information which are available in the platform
#
#############################################################################
try:
import sys
import re
import os
import subprocess
import json
import syslog
from sonic_platform_base.chassis_base import ChassisBase
from sonic_daemon_base.daemon_base import Logger
from sonic_platform.fan import Fan
from sonic_platform.psu import Psu
from sonic_platform.component import Component
from sonic_platform.thermal import Thermal
from sonic_platform.sfp import Sfp
from sonic_platform.eeprom import Tlv
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
NUM_FAN_TRAY = 5
NUM_FAN = 2
NUM_PSU = 2
NUM_THERMAL = 4
NUM_SFP = 54
SFP_PORT_START = 0
QSFP_PORT_START = 48
SFP_PORT_END = 47
QSFP_PORT_END=53
HOST_REBOOT_CAUSE_PATH = "/host/reboot-cause/"
PMON_REBOOT_CAUSE_PATH = "/usr/share/sonic/platform/api_files/reboot-cause/"
REBOOT_CAUSE_FILE = "reboot-cause.txt"
PREV_REBOOT_CAUSE_FILE = "previous-reboot-cause.txt"
COMPONENT_NAME_LIST = ["BIOS"]
HOST_CHK_CMD = "docker > /dev/null 2>&1"
class Chassis(ChassisBase):
"""Platform-specific Chassis class"""
def __init__(self):
super(Chassis, self).__init__()
for fantray_index in range(0, NUM_FAN_TRAY):
for fan_index in range(0, NUM_FAN):
fan = Fan(fantray_index, fan_index)
self._fan_list.append(fan)
for index in range(0, NUM_PSU):
psu = Psu(index)
self._psu_list.append(psu)
for index in range(0, NUM_THERMAL):
thermal = Thermal(index)
self._thermal_list.append(thermal)
self.PORT_START = SFP_PORT_START
self.QSFP_PORT_START = QSFP_PORT_START
self.PORT_END = QSFP_PORT_END
for index in range(0, NUM_SFP):
if index in range(self.QSFP_PORT_START, self.QSPORT_END + 1):
sfp_module = Sfp(index, 'QSFP')
else:
sfp_module = Sfp(index, 'SFP')
self._sfp_list.append(sfp_module)
self._component_name_list = COMPONENT_NAME_LIST
self._watchdog = Watchdog()
self._eeprom = Tlv()
logger.log_info("Chassis loaded successfully")
def __is_host(self):
return os.system(HOST_CHK_CMD) == 0
def __read_txt_file(self, file_path):
try:
with open(file_path, 'r') as fd:
data = fd.read()
return data.strip()
except IOError:
pass
return None
def get_base_mac(self):
"""
Retrieves the base MAC address for the chassis
Returns:
A string containing the MAC address in the format
'XX:XX:XX:XX:XX:XX'
"""
return self._eeprom.get_mac()
def get_serial_number(self):
"""
Retrieves the hardware serial number for the chassis
Returns:
A string containing the hardware serial number for this chassis.
"""
return self._eeprom.get_serial()
def get_system_eeprom_info(self):
"""
Retrieves the full content of system EEPROM information for the chassis
Returns:
A dictionary where keys are the type code defined in
OCP ONIE TlvInfo EEPROM format and values are their corresponding
values.
"""
return self._eeprom.get_eeprom()
def get_firmware_version(self, component_name):
"""
Retrieves platform-specific hardware/firmware versions for chassis
componenets such as BIOS, CPLD, FPGA, etc.
Args:
type: A string, component name
Returns:
A string containing platform-specific component versions
"""
self.component = Component(component_name)
if component_name not in self._component_name_list:
return None
return self.component.get_firmware_version()
def install_component_firmware(self, component_name, image_path):
"""
Install firmware to module
Args:
type: A string, component name.
image_path: A string, path to firmware image.
Returns:
A boolean, True if install successfully, False if not
"""
self.component = Component(component_name)
if component_name not in self._component_name_list:
return False
return self.component.upgrade_firmware(image_path)
def get_reboot_cause(self):
"""
Retrieves the cause of the previous reboot
Returns:
A tuple (string, string) where the first element is a string
containing the cause of the previous reboot. This string must be
one of the predefined strings in this class. If the first string
is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used
to pass a description of the reboot cause.
"""
description = 'None'
reboot_cause = self.REBOOT_CAUSE_HARDWARE_OTHER
reboot_cause_path = (HOST_REBOOT_CAUSE_PATH + REBOOT_CAUSE_FILE) if self.__is_host(
) else PMON_REBOOT_CAUSE_PATH + REBOOT_CAUSE_FILE
prev_reboot_cause_path = (HOST_REBOOT_CAUSE_PATH + PREV_REBOOT_CAUSE_FILE) if self.__is_host(
) else PMON_REBOOT_CAUSE_PATH + PREV_REBOOT_CAUSE_FILE
sw_reboot_cause = self.__read_txt_file(
reboot_cause_path) or "Unknown"
prev_sw_reboot_cause = self.__read_txt_file(
prev_reboot_cause_path) or "Unknown"
if sw_reboot_cause != "Unknown":
reboot_cause = self.REBOOT_CAUSE_NON_HARDWARE
description = sw_reboot_cause
else:
reboot_cause = self.REBOOT_CAUSE_HARDWARE_OTHER
description = 'Unknown reason'
return (reboot_cause, description)

83
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/component.py Normal file
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@ -0,0 +1,83 @@
#!/usr/bin/env python
#############################################################################
# Component contains an implementation of SONiC Platform Base API and
# provides the components firmware management function
#############################################################################
import json
import os.path
import shutil
import shlex
import subprocess
try:
from sonic_platform_base.device_base import DeviceBase
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
BIOS_VERSION_PATH = "/sys/class/dmi/id/bios_version"
class Component(DeviceBase):
"""Platform-specific Component class"""
DEVICE_TYPE = "component"
def __init__(self, component_name):
DeviceBase.__init__(self)
self.name = component_name.upper()
def __run_command(self, command):
# Run bash command and print output to stdout
try:
process = subprocess.Popen(
shlex.split(command), stdout=subprocess.PIPE)
while True:
output = process.stdout.readline()
if output == '' and process.poll() is not None:
break
rc = process.poll()
if rc != 0:
return False
except:
return False
return True
def __get_bios_version(self):
# Retrieves the BIOS firmware version
try:
with open(BIOS_VERSION_PATH, 'r') as fd:
bios_version = fd.read()
return bios_version.strip()
except Exception as e:
return None
def get_firmware_version(self):
"""
Retrieves the firmware version of module
Returns:
string: The firmware versions of the module
"""
fw_version = None
if self.name == "BIOS":
fw_version = self.__get_bios_version()
return fw_version
def upgrade_firmware(self, image_path):
"""
Install firmware to module
Args:
image_path: A string, path to firmware image
Returns:
A boolean, True if install successfully, False if not
"""
if not os.path.isfile(image_path):
return False
if self.name == "BIOS":
print("Not supported")
return False
return self.__run_command(install_command)

112
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/eeprom.py Normal file
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@ -0,0 +1,112 @@
#!/usr/bin/env python
#############################################################################
# Platform and model specific eeprom subclass, inherits from the base class,
# and provides the followings:
# - the eeprom format definition
# - specific encoder/decoder if there is special need
#############################################################################
try:
import glob
import os
import sys
import imp
import re
from array import array
from cStringIO import StringIO
from sonic_platform_base.sonic_eeprom import eeprom_dts
from sonic_platform_base.sonic_eeprom import eeprom_tlvinfo
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
CACHE_ROOT = '/var/cache/sonic/decode-syseeprom'
CACHE_FILE = 'syseeprom_cache'
class Tlv(eeprom_tlvinfo.TlvInfoDecoder):
EEPROM_DECODE_HEADLINES = 6
def __init__(self):
self._eeprom_path = "/sys/bus/i2c/devices/0-0056/eeprom"
super(Tlv, self).__init__(self._eeprom_path, 0, '', True)
self._eeprom = self._load_eeprom()
def __parse_output(self, decode_output):
decode_output.replace('\0', '')
lines = decode_output.split('\n')
lines = lines[self.EEPROM_DECODE_HEADLINES:]
_eeprom_info_dict = dict()
for line in lines:
try:
match = re.search(
'(0x[0-9a-fA-F]{2})([\s]+[\S]+[\s]+)([\S]+)', line)
if match is not None:
idx = match.group(1)
value = match.group(3).rstrip('\0')
_eeprom_info_dict[idx] = value
except:
pass
return _eeprom_info_dict
def _load_eeprom(self):
original_stdout = sys.stdout
sys.stdout = StringIO()
err = self.read_eeprom_db()
if err:
# Failed to read EEPROM information from database. Read from cache file
pass
else:
decode_output = sys.stdout.getvalue()
sys.stdout = original_stdout
return self.__parse_output(decode_output)
status = self.check_status()
if status < 'ok':
return False
if not os.path.exists(CACHE_ROOT):
try:
os.makedirs(CACHE_ROOT)
except:
pass
#
# only the eeprom classes that inherit from eeprom_base
# support caching. Others will work normally
#
try:
self.set_cache_name(os.path.join(CACHE_ROOT, CACHE_FILE))
except:
pass
e = self.read_eeprom()
if e is None:
return 0
try:
self.update_cache(e)
except:
pass
self.decode_eeprom(e)
decode_output = sys.stdout.getvalue()
sys.stdout = original_stdout
(is_valid, valid_crc) = self.is_checksum_valid(e)
if not is_valid:
return False
return self.__parse_output(decode_output)
def get_eeprom(self):
return self._eeprom
def get_serial(self):
return self._eeprom.get('0x23', "Undefined.")
def get_mac(self):
return self._eeprom.get('0x24', "Undefined.")

165
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/fan.py Normal file
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@ -0,0 +1,165 @@
#!/usr/bin/env python
#############################################################################
#
# Module contains an implementation of SONiC Platform Base API and
# provides the fan status which are available in the platform
#
#############################################################################
import json
import math
import os.path
try:
from sonic_platform_base.fan_base import FanBase
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
FAN_PATH = "/sys/bus/i2c/devices/1-0063/"
FANTRAY_NAME_LIST = ["FANTRAY-1", "FANTRAY-2",
"FANTRAY-3", "FANTRAY-4", "FANTRAY-5"]
FAN_NAME_LIST = ["front", "rear"]
class Fan(FanBase):
"""Platform-specific Fan class"""
def __init__(self, fan_tray_index, fan_index=0):
self.fan_index = fan_index
self.fan_tray_index = fan_tray_index
self.fan_presence = "fan{}_present"
self.fan_direction = "fan{}_direction"
self.fan_fault = "fan{}_{}_fault"
self.fan_speed_rpm = "fan{}_{}_speed_rpm"
FanBase.__init__(self)
def __read_txt_file(self, file_path):
try:
with open(file_path, 'r') as fd:
data = fd.read()
return data.strip()
except IOError:
pass
return ""
def __write_txt_file(self, file_path, value):
try:
with open(file_path, 'w') as fd:
fd.write(str(value))
except:
return False
return True
def __search_file_by_name(self, directory, file_name):
for dirpath, dirnames, files in os.walk(directory):
for name in files:
file_path = os.path.join(dirpath, name)
if name in file_name:
return file_path
return None
def get_direction(self):
"""
Retrieves the direction of fan
Returns:
A string, either FAN_DIRECTION_INTAKE or FAN_DIRECTION_EXHAUST
depending on fan direction
"""
direction = self.FAN_DIRECTION_EXHAUST
fan_direction_file = (FAN_PATH +
self.fan_direction.format(self.fan_tray_index+1))
raw = self.__read_txt_file(fan_direction_file).strip('\r\n')
direction = self.FAN_DIRECTION_INTAKE if str(
raw).upper() == "1" else self.FAN_DIRECTION_EXHAUST
return direction
def get_speed(self):
"""
Retrieves the speed of fan as a percentage of full speed
Returns:
An integer, the percentage of full fan speed, in the range 0 (off)
to 12000 (full speed)
"""
speed = 0
if self.get_presence():
fan_speed_file = (FAN_PATH +
self.fan_speed_rpm.format(self.fan_tray_index+1,FAN_NAME_LIST[self.fan_index]))
speed = self.__read_txt_file(fan_speed_file).strip('\r\n')
return int(speed)
def get_target_speed(self):
"""
Retrieves the target (expected) speed of the fan
Returns:
An integer, the percentage of full fan speed, in the range 0 (off)
to 100 (full speed)
"""
target = 0
if self.get_presence():
fan_speed_file=(FAN_PATH +
self.fan_speed_rpm.format(self.fan_tray_index+1, FAN_NAME_LIST[self.fan_index]))
target=self.__read_txt_file(fan_speed_file).strip('\r\n')
return target
def get_speed_tolerance(self):
"""
Retrieves the speed tolerance of the fan
Returns:
An integer, the percentage of variance from target speed which is
considered tolerable
"""
return 10
def set_speed(self, speed):
"""
Sets the fan speed
Args:
speed: An integer, the percentage of full fan speed to set fan to,
in the range 0 (off) to 100 (full speed)
Returns:
A boolean, True if speed is set successfully, False if not
Note:
Depends on pwm or target mode is selected:
1) pwm = speed_pc * 255 <-- Currently use this mode.
2) target_pwm = speed_pc * 100 / 255
2.1) set pwm{}_enable to 3
"""
return False
def set_status_led(self, color):
"""
Sets the state of the fan module status LED
Args:
color: A string representing the color with which to set the
fan module status LED
Returns:
bool: True if status LED state is set successfully, False if not
"""
return False
def get_name(self):
"""
Retrieves the name of the device
Returns:
string: The name of the device
"""
fan_name = FAN_NAME_LIST[self.fan_tray_index]
return fan_name
def get_presence(self):
"""
Retrieves the presence of the PSU
Returns:
bool: True if PSU is present, False if not
"""
fan_direction_file = (FAN_PATH +
self.fan_presence.format(self.fan_tray_index+1))
present_str = self.__read_txt_file(fan_direction_file) or '1'
return int(present_str) == 0

20
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/platform.py Normal file
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@ -0,0 +1,20 @@
#!/usr/bin/env python
#############################################################################
# Module contains an implementation of SONiC Platform Base API and
# provides the platform information
#
#############################################################################
try:
from sonic_platform_base.platform_base import PlatformBase
from sonic_platform.chassis import Chassis
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
class Platform(PlatformBase):
"""Platform-specific Platform class"""
def __init__(self):
PlatformBase.__init__(self)
self._chassis = Chassis()

102
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/psu.py Normal file
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@ -0,0 +1,102 @@
#!/usr/bin/env python
#############################################################################
# psuutil.py
# Platform-specific PSU status interface for SONiC
#############################################################################
import os.path
import sonic_platform
try:
from sonic_platform_base.psu_base import PsuBase
from sonic_platform.fan import Fan
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
FAN_MAX_RPM = 9600
PSU_NAME_LIST = ["PSU-0", "PSU-1"]
class Psu(PsuBase):
"""Platform-specific Psu class"""
SYSFS_PSU_DIR = ["/sys/bus/i2c/devices/10-0050",
"/sys/bus/i2c/devices/11-0053"]
def __init__(self):
self.index = psu_index
PsuBase.__init__(self)
def get_fan(self):
"""
Retrieves object representing the fan module contained in this PSU
Returns:
An object dervied from FanBase representing the fan module
contained in this PSU
"""
# Hardware not supported
return False
def get_powergood_status(self):
"""
Retrieves the powergood status of PSU
Returns:
A boolean, True if PSU has stablized its output voltages and passed all
its internal self-tests, False if not.
"""
return self.get_status()
def set_status_led(self, color):
"""
Sets the state of the PSU status LED
Args:
color: A string representing the color with which to set the PSU status LED
Note: Only support green and off
Returns:
bool: True if status LED state is set successfully, False if not
"""
# Hardware not supported
return False
def get_name(self):
"""
Retrieves the name of the device
Returns:
string: The name of the device
"""
return PSU_NAME_LIST[self.index]
def get_presence(self):
"""
Retrieves the presence of the PSU
Returns:
bool: True if PSU is present, False if not
"""
attr_file ='psu_present'
attr_path = self.SYSFS_PSU_DIR[self.index-1] +'/' + attr_file
status = 0
try:
with open(attr_path, 'r') as psu_prs:
status = int(psu_prs.read())
except IOError:
return False
return status == 1
def get_status(self):
"""
Retrieves the operational status of the device
Returns:
A boolean value, True if device is operating properly, False if not
"""
attr_file = 'psu_power_good'
attr_path = self.SYSFS_PSU_DIR[self.index-1] +'/' + attr_file
status = 0
try:
with open(attr_path, 'r') as power_status:
status = int(power_status.read())
except IOError:
return False
return status == 1

1133
device/accton/x86_64-accton_as7116_54x-r0/sonic_platform/sfp.py Normal file
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0
platform/nephos/sonic-platform-modules-accton/as7116-54x/classes/__init__.py
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0
platform/nephos/sonic-platform-modules-accton/as7116-54x/classes/fanutil.py
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0
platform/nephos/sonic-platform-modules-accton/as7116-54x/classes/thermalutil.py
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1
platform/nephos/sonic-platform-modules-accton/as7116-54x/service/as7116-platform-init.service
View File

@ -1,6 +1,7 @@
[Unit]
Description=Accton AS7116-54X Platform initialization service
Before=pmon.service
After=sysinit.target
DefaultDependencies=no
[Service]

41
platform/nephos/sonic-platform-modules-accton/as7116-54x/service/platform_api/platform_api_mgnt.sh Executable file
View File

@ -0,0 +1,41 @@
#!/bin/bash
PREV_REBOOT_CAUSE="/host/reboot-cause/"
DEVICE="/usr/share/sonic/device"
PLATFORM=$(/usr/local/bin/sonic-cfggen -H -v DEVICE_METADATA.localhost.platform)
FILES=$DEVICE/$PLATFORM/api_files
install() {
# Install sonic-platform package
if [ -e $DEVICE/$PLATFORM/sonic_platform-1.0-py2-none-any.whl ]; then
pip install $DEVICE/$PLATFORM/sonic_platform-1.0-py2-none-any.whl
fi
}
init() {
# mount needed files for sonic-platform package
mkdir -p $FILES
mkdir -p $FILES/reboot-cause
mount -B $PREV_REBOOT_CAUSE $FILES/reboot-cause
}
deinit() {
# deinit sonic-platform package
umount -f $PREV_REBOOT_CAUSE $FILES/reboot-cause >/dev/null 2>/dev/null
}
uninstall() {
# Uninstall sonic-platform package
pip uninstall -y sonic-platform >/dev/null 2>/dev/null
}
case "$1" in
install | uninstall | init | deinit)
$1
;;
*)
echo "Usage: $0 {install|uninstall|init|deinit}"
exit 1
;;
esac

43
platform/nephos/sonic-platform-modules-accton/as7116-54x/setup.py
View File

@ -1,15 +1,34 @@
#!/usr/bin/env python
import os
import sys
from setuptools import setup
os.listdir
DEVICE_NAME = 'accton'
HW_SKU = 'x86_64-accton_as7116_54x-r0'
setup(
name='as7116-54x',
version='1.0.0',
description='Module to initialize Accton AS7116-54X platforms',
packages=['as7116-54x'],
package_dir={'as7116-54x': 'as7116-54x/classes'},
)
name='sonic-platform',
version='1.0',
description='SONiC platform API implementation on Accton Platforms',
license='Apache 2.0',
author='SONiC Team',
author_email='linuxnetdev@microsoft.com',
url='https://github.com/Azure/sonic-buildimage',
maintainer='Simon Ji',
maintainer_email='Simon.Ji@mediatek.com',
packages=[
'sonic_platform',
],
package_dir={
'sonic_platform': '../../../device/{}/{}/sonic_platform'.format(DEVICE_NAME, HW_SKU)},
classifiers=[
'Development Status :: 3 - Alpha',
'Environment :: Plugins',
'Intended Audience :: Developers',
'Intended Audience :: Information Technology',
'Intended Audience :: System Administrators',
'License :: OSI Approved :: Apache Software License',
'Natural Language :: English',
'Operating System :: POSIX :: Linux',
'Programming Language :: Python :: 2.7',
'Topic :: Utilities',
],
keywords='sonic SONiC platform PLATFORM',
)

7
platform/nephos/sonic-platform-modules-accton/as7116-54x/utils/accton_as7116_util.py
View File

@ -315,6 +315,13 @@ def do_install():
return status
else:
print PROJECT_NAME.upper()+" devices detected...."
status, output = log_os_system(
"/bin/sh /usr/local/bin/platform_api_mgnt.sh init", 1)
if status:
print output
if FORCE == 0:
return status
return
def do_uninstall():

76
platform/nephos/sonic-platform-modules-accton/debian/rules
View File

@ -1,19 +1,8 @@
#!/usr/bin/make -f
# -*- makefile -*-
# Sample debian/rules that uses debhelper.
# This file was originally written by Joey Hess and Craig Small.
# As a special exception, when this file is copied by dh-make into a
# dh-make output file, you may use that output file without restriction.
# This special exception was added by Craig Small in version 0.37 of dh-make.
include /usr/share/dpkg/pkg-info.mk
# Uncomment this to turn on verbose mode.
#export DH_VERBOSE=1
export INSTALL_MOD_DIR:=extra
PYTHON ?= python2
PYTHON ?= python2.7
PACKAGE_PRE_NAME := sonic-platform-accton
KVERSION ?= $(shell uname -r)
@ -27,60 +16,25 @@ CLASSES_DIR := classes
CONF_DIR := conf
%:
dh $@ --with systemd,python2,python3 --buildsystem=pybuild
dh $@
clean:
dh_testdir
dh_testroot
dh_clean
build:
#make modules -C $(KERNEL_SRC)/build M=$(MODULE_SRC)
override_dh_auto_build:
(for mod in $(MODULE_DIRS); do \
make modules -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules; \
$(PYTHON) $${mod}/setup.py build; \
$(PYTHON) $${mod}/setup.py bdist_wheel -d $(MOD_SRC_DIR)/$${mod}/modules; \
done)
binary: binary-arch binary-indep
# Nothing to do
binary-arch:
# Nothing to do
#install: build
#dh_testdir
#dh_testroot
#dh_clean -k
#dh_installdirs
binary-indep:
dh_testdir
dh_installdirs
# Custom package commands
override_dh_auto_install:
(for mod in $(MODULE_DIRS); do \
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod} /$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod} /usr/local/bin; \
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod} /lib/systemd/system; \
cp $(MOD_SRC_DIR)/$${mod}/$(MODULE_DIR)/*.ko debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \
cp $(MOD_SRC_DIR)/$${mod}/$(UTILS_DIR)/* debian/$(PACKAGE_PRE_NAME)-$${mod}/usr/local/bin/; \
cp $(MOD_SRC_DIR)/$${mod}/$(SERVICE_DIR)/*.service debian/$(PACKAGE_PRE_NAME)-$${mod}/lib/systemd/system/; \
$(PYTHON) $${mod}/setup.py install --root=$(MOD_SRC_DIR)/debian/$(PACKAGE_PRE_NAME)-$${mod} --install-layout=deb; \
cp $(MOD_SRC_DIR)/$${mod}/$(MODULE_DIR)/*.ko \
debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \
done)
override_dh_usrlocal:
override_dh_clean:
dh_clean
(for mod in $(MODULE_DIRS); do \
make -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules clean; \
done)
# Resuming debhelper scripts
dh_testroot
dh_install
dh_installchangelogs
dh_installdocs
dh_systemd_enable
dh_installinit
dh_systemd_start
dh_link
dh_fixperms
dh_compress
dh_strip
dh_installdeb
dh_gencontrol
dh_md5sums
dh_builddeb
.PHONY: build binary binary-arch binary-indep clean

4
platform/nephos/sonic-platform-modules-accton/debian/sonic-platform-accton-as7116-54x.install Normal file
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as7116-54x/utils/* usr/local/bin
as7116-54x/service/*.service lib/systemd/system
as7116-54x/modules/sonic_platform-1.0-py2-none-any.whl usr/share/sonic/device/x86_64-accton_as7116_54x-r0
as7116-54x/service/platform_api/platform_api_mgnt.sh usr/local/bin

5
platform/nephos/sonic-platform-modules-accton/debian/sonic-platform-accton-as7116-54x.postinst Normal file
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depmod -a
systemctl enable as7116-platform-init.service
systemctl start as7116-platform-init.service
/usr/local/bin/platform_api_mgnt.sh install