matthew/sonic-buildimage
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Merge remote-tracking branch 'github/master' into 201904

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This commit is contained in:
Shu0T1an ChenG 2019-05-29 15:55:28 -07:00
commit 9c6b0dccea
196 changed files with 18252 additions and 998 deletions
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16
.gitignore vendored
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@ -9,6 +9,12 @@ target/
*.deb
*.changes
*.buildinfo
*.tar
*.xz
*.gz
*-dbg
*dbg.j2
*.img
# Subdirectories in src
src/bash/*
@ -43,6 +49,8 @@ src/libnl3/*
!src/libnl3/Makefile
src/libteam/*
!src/libteam/Makefile
src/libyang/*
!src/libyang/Makefile
src/lldpd/*
!src/lldpd/Makefile
!src/lldpd/patch/
@ -59,6 +67,8 @@ src/radvd/*
!src/radvd/patch/
src/redis/*
!src/redis/Makefile
src/smartmontools/*
!src/smartmontools/Makefile
src/snmpd/*
!src/snmpd/Makefile
src/sonic-device-data/src/device/
@ -66,6 +76,8 @@ src/sonic-device-data/src/debian/
src/supervisor/*
!src/supervisor/Makefile
!src/supervisor/patch/
src/swig/*
!src/swig/Makefile
src/telemetry/debian/*
!src/telemetry/debian/changelog
!src/telemetry/debian/compat
@ -109,3 +121,7 @@ src/sonic-config-engine/sonic_config_engine.egg-info
src/sonic-daemon-base/**/*.pyc
src/sonic-daemon-base/build
src/sonic-daemon-base/sonic_daemon_base.egg-info
# Misc. files
files/initramfs-tools/arista-convertfs
files/initramfs-tools/union-mount

1
.gitmodules vendored
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@ -47,6 +47,7 @@
[submodule "src/sonic-frr/frr"]
path = src/sonic-frr/frr
url = https://github.com/Azure/sonic-frr.git
branch = frr/7.0
[submodule "platform/p4/p4-hlir/p4-hlir-v1.1"]
path = platform/p4/p4-hlir/p4-hlir-v1.1
url = https://github.com/p4lang/p4-hlir.git

16
Makefile
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@ -1,20 +1,20 @@
# SONiC make file
NOSTRETCH ?= 0
NOJESSIE ?= 0
%::
@echo "+++ --- Making $@ --- +++"
ifeq ($(NOSTRETCH), 0)
BLDENV=stretch EXTRA_STRETCH_TARGETS=$(notdir $@) make -f Makefile.work stretch
ifeq ($(NOJESSIE), 0)
EXTRA_JESSIE_TARGETS=$(notdir $@) make -f Makefile.work jessie
endif
make -f Makefile.work $@
BLDENV=stretch make -f Makefile.work $@
stretch:
jessie:
@echo "+++ Making $@ +++"
ifeq ($(NOSTRETCH), 0)
BLDENV=stretch make -f Makefile.work stretch
ifeq ($(NOJESSIE), 0)
make -f Makefile.work jessie
endif
clean reset init configure showtag sonic-slave-build sonic-slave-bash :
@echo "+++ Making $@ +++"
make -f Makefile.work $@
BLDENV=stretch make -f Makefile.work $@

9
Makefile.work
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@ -20,11 +20,10 @@
# * Please note that with current Stretch build structure,
# * user of KEEP_SLAVE_ON feature will have to be conscious
# * about which docker to stay inside after build is done.
# * - If user desires to stay inside Stretch docker, please issue
# * make KEEP_SLAVE_ON=yes stretch
# * - If user desires to stay inside Jessie docker, please issue
# * (a successful "make stretch" may be needed before the following command)
# * make NOSTRETCH=1 KEEP_SLAVE_ON=yes <any jessie target>
# * make KEEP_SLAVE_ON=yes jessie
# * - If user desires to stay inside Stretch docker, please issue
# * make NOJESSIE=1 KEEP_SLAVE_ON=yes <any target>
# * SOURCE_FOLDER: host path to be mount as /var/$(USER)/src, only effective when KEEP_SLAVE_ON=yes
# * SONIC_BUILD_JOBS: Specifying number of concurrent build job(s) to run
# * VS_PREPARE_MEM: Prepare memory in VS build (drop cache and compact).
@ -123,7 +122,7 @@ SONIC_BUILD_INSTRUCTION := make \
HTTP_PROXY=$(http_proxy) \
HTTPS_PROXY=$(https_proxy) \
SONIC_ENABLE_SYSTEM_TELEMETRY=$(ENABLE_SYSTEM_TELEMETRY) \
EXTRA_STRETCH_TARGETS=$(EXTRA_STRETCH_TARGETS) \
EXTRA_JESSIE_TARGETS=$(EXTRA_JESSIE_TARGETS) \
$(SONIC_OVERRIDE_BUILD_VARS)
.PHONY: sonic-slave-build sonic-slave-bash init reset

3
README.md
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@ -71,9 +71,6 @@ To build SONiC installer image and docker images, run the following commands:
# Execute make configure once to configure ASIC
make configure PLATFORM=[ASIC_VENDOR]
# Build Debian Stretch required targets (Manual execution optional; will also be executed as part of the build)
BLDENV=stretch make stretch
# Build SONiC image
make all

10
build_debian.sh
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@ -160,7 +160,7 @@ sudo chmod +x $FILESYSTEM_ROOT/etc/initramfs-tools/hooks/union-fsck
pushd $FILESYSTEM_ROOT/usr/share/initramfs-tools/scripts/init-bottom && sudo patch -p1 < $OLDPWD/files/initramfs-tools/udev.patch; popd
## Install latest intel ixgbe driver
sudo cp target/files/stretch/ixgbe.ko $FILESYSTEM_ROOT/lib/modules/${LINUX_KERNEL_VERSION}-amd64/kernel/drivers/net/ethernet/intel/ixgbe/ixgbe.ko
sudo cp $files_path/ixgbe.ko $FILESYSTEM_ROOT/lib/modules/${LINUX_KERNEL_VERSION}-amd64/kernel/drivers/net/ethernet/intel/ixgbe/ixgbe.ko
## Install docker
echo '[INFO] Install docker'
@ -230,6 +230,7 @@ sudo LANG=C DEBIAN_FRONTEND=noninteractive chroot $FILESYSTEM_ROOT apt-get -y in
usbutils \
pciutils \
iptables-persistent \
ebtables \
logrotate \
curl \
kexec-tools \
@ -247,6 +248,7 @@ sudo LANG=C DEBIAN_FRONTEND=noninteractive chroot $FILESYSTEM_ROOT apt-get -y in
tcptraceroute \
mtr-tiny \
locales \
flashrom \
cgroup-tools
#Adds a locale to a debian system in non-interactive mode
@ -305,7 +307,7 @@ check filesystem root-overlay with path /
check filesystem var-log with path /var/log
if space usage > 90% for 5 times within 10 cycles then alert
check system $HOST
if memory usage > 90% for 5 times within 10 cycles then alert
if memory usage > 50% for 5 times within 10 cycles then alert
if cpu usage (user) > 90% for 5 times within 10 cycles then alert
if cpu usage (system) > 90% for 5 times within 10 cycles then alert
EOF
@ -411,6 +413,10 @@ if [ "${enable_organization_extensions}" = "y" ]; then
fi
fi
## Setup ebtable rules (rule file is in binary format)
sudo sed -i 's/EBTABLES_LOAD_ON_START="no"/EBTABLES_LOAD_ON_START="yes"/g' ${FILESYSTEM_ROOT}/etc/default/ebtables
sudo cp files/image_config/ebtables/ebtables.filter ${FILESYSTEM_ROOT}/etc
## Remove gcc and python dev pkgs
sudo LANG=C DEBIAN_FRONTEND=noninteractive chroot $FILESYSTEM_ROOT apt-get -y remove gcc libpython2.7-dev

486
device/accton/x86_64-accton_as4630_54pe-r0/Accton-AS4630-54PE/hx5-as4630-48x1G+4x25G+2x100G.bcm Executable file
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@ -0,0 +1,486 @@
stable_size=71303168
#polarity/lanemap is using TH2 style.
core_clock_frequency=893
dpp_clock_ratio=2:3
ptp_ts_pll_fref=50000000
ptp_bs_fref_0=50000000
ptp_bs_fref_1=50000000
#oversubscribe_mode=1
pbmp_xport_xe=0x1FFFFFFE000000000000
parity_enable=0
mem_cache_enable=1
l2_mem_entries=32768
#l3_mem_entries=49152
#fpem_mem_entries=16384
l2xmsg_mode=1
port_flex_enable=1
#3x PM4x10Q (3 * 16 = 48 physical ports)
#Doesn't support oversubscribe in Q mode
#MCQ0
port_gmii_mode_1=1 #Q mode
#PHY4 U56 xx1, MDC/MDIO2, PHYADDR:0x00-0x07, 0x08
port_phy_addr_1=0x40
port_phy_addr_2=0x41
port_phy_addr_3=0x42
port_phy_addr_4=0x43
port_phy_addr_5=0x44
port_phy_addr_6=0x45
port_phy_addr_7=0x46
port_phy_addr_8=0x47
phy_port_primary_and_offset_1=0x0100
phy_port_primary_and_offset_2=0x0101
phy_port_primary_and_offset_3=0x0102
phy_port_primary_and_offset_4=0x0103
phy_port_primary_and_offset_5=0x0104
phy_port_primary_and_offset_6=0x0105
phy_port_primary_and_offset_7=0x0106
phy_port_primary_and_offset_8=0x0107
dport_map_port_1=26
dport_map_port_2=25
dport_map_port_3=28
dport_map_port_4=27
dport_map_port_5=30
dport_map_port_6=29
dport_map_port_7=32
dport_map_port_8=31
portmap_1=1:1
portmap_2=2:1
portmap_3=3:1
portmap_4=4:1
portmap_5=5:1
portmap_6=6:1
portmap_7=7:1
portmap_8=8:1
phy_chain_rx_lane_map_physical{1.0}=0x3210
phy_chain_rx_lane_map_physical{2.0}=0x3210
phy_chain_rx_lane_map_physical{3.0}=0x3210
phy_chain_rx_lane_map_physical{4.0}=0x3210
phy_chain_rx_lane_map_physical{5.0}=0x3210
phy_chain_rx_lane_map_physical{6.0}=0x3210
phy_chain_rx_lane_map_physical{7.0}=0x3210
phy_chain_rx_lane_map_physical{8.0}=0x3210
phy_chain_tx_lane_map_physical{1.0}=0x3210
phy_chain_tx_lane_map_physical{2.0}=0x3210
phy_chain_tx_lane_map_physical{3.0}=0x3210
phy_chain_tx_lane_map_physical{4.0}=0x3210
phy_chain_tx_lane_map_physical{5.0}=0x3210
phy_chain_tx_lane_map_physical{6.0}=0x3210
phy_chain_tx_lane_map_physical{7.0}=0x3210
phy_chain_tx_lane_map_physical{8.0}=0x3210
phy_chain_rx_polarity_flip_physical{1.0}=0x0
phy_chain_rx_polarity_flip_physical{2.0}=0x0
phy_chain_rx_polarity_flip_physical{3.0}=0x0
phy_chain_rx_polarity_flip_physical{4.0}=0x0
phy_chain_rx_polarity_flip_physical{5.0}=0x0
phy_chain_rx_polarity_flip_physical{6.0}=0x0
phy_chain_rx_polarity_flip_physical{7.0}=0x0
phy_chain_rx_polarity_flip_physical{8.0}=0x0
phy_chain_tx_polarity_flip_physical{1.0}=0x0
phy_chain_tx_polarity_flip_physical{2.0}=0x0
phy_chain_tx_polarity_flip_physical{3.0}=0x0
phy_chain_tx_polarity_flip_physical{4.0}=0x0
phy_chain_tx_polarity_flip_physical{5.0}=0x0
phy_chain_tx_polarity_flip_physical{6.0}=0x0
phy_chain_tx_polarity_flip_physical{7.0}=0x0
phy_chain_tx_polarity_flip_physical{8.0}=0x0
#PHY5 U57 x1x, MDC/MDIO2, PHYADDR:0x09-0x10, 0x11
port_phy_addr_9=0x49
port_phy_addr_10=0x4A
port_phy_addr_11=0x4B
port_phy_addr_12=0x4C
port_phy_addr_13=0x4D
port_phy_addr_14=0x4E
port_phy_addr_15=0x4F
port_phy_addr_16=0x50
phy_port_primary_and_offset_9=0x0900
phy_port_primary_and_offset_10=0x0901
phy_port_primary_and_offset_11=0x0902
phy_port_primary_and_offset_12=0x0903
phy_port_primary_and_offset_13=0x0904
phy_port_primary_and_offset_14=0x0905
phy_port_primary_and_offset_15=0x0906
phy_port_primary_and_offset_16=0x0907
dport_map_port_9=34
dport_map_port_10=33
dport_map_port_11=36
dport_map_port_12=35
dport_map_port_13=38
dport_map_port_14=37
dport_map_port_15=40
dport_map_port_16=39
portmap_9=9:1
portmap_10=10:1
portmap_11=11:1
portmap_12=12:1
portmap_13=13:1
portmap_14=14:1
portmap_15=15:1
portmap_16=16:1
phy_chain_rx_lane_map_physical{9.0}=0x3210
phy_chain_rx_lane_map_physical{10.0}=0x3210
phy_chain_rx_lane_map_physical{11.0}=0x3210
phy_chain_rx_lane_map_physical{12.0}=0x3210
phy_chain_rx_lane_map_physical{13.0}=0x3210
phy_chain_rx_lane_map_physical{14.0}=0x3210
phy_chain_rx_lane_map_physical{15.0}=0x3210
phy_chain_rx_lane_map_physical{16.0}=0x3210
phy_chain_tx_lane_map_physical{9.0}=0x3210
phy_chain_tx_lane_map_physical{10.0}=0x3210
phy_chain_tx_lane_map_physical{11.0}=0x3210
phy_chain_tx_lane_map_physical{12.0}=0x3210
phy_chain_tx_lane_map_physical{13.0}=0x3210
phy_chain_tx_lane_map_physical{14.0}=0x3210
phy_chain_tx_lane_map_physical{15.0}=0x3210
phy_chain_tx_lane_map_physical{16.0}=0x3210
phy_chain_rx_polarity_flip_physical{9.0}=0x0
phy_chain_rx_polarity_flip_physical{10.0}=0x0
phy_chain_rx_polarity_flip_physical{11.0}=0x0
phy_chain_rx_polarity_flip_physical{12.0}=0x0
phy_chain_rx_polarity_flip_physical{13.0}=0x0
phy_chain_rx_polarity_flip_physical{14.0}=0x0
phy_chain_rx_polarity_flip_physical{15.0}=0x0
phy_chain_rx_polarity_flip_physical{16.0}=0x0
phy_chain_tx_polarity_flip_physical{9.0}=0x0
phy_chain_tx_polarity_flip_physical{10.0}=0x0
phy_chain_tx_polarity_flip_physical{11.0}=0x0
phy_chain_tx_polarity_flip_physical{12.0}=0x0
phy_chain_tx_polarity_flip_physical{13.0}=0x0
phy_chain_tx_polarity_flip_physical{14.0}=0x0
phy_chain_tx_polarity_flip_physical{15.0}=0x0
phy_chain_tx_polarity_flip_physical{16.0}=0x0
#MCQ1
port_gmii_mode_17=1 #Q mode
#PHY6 U58 11x, MDC/MDIO2, PHYADDR:0x12-0x19, 0x1A
port_phy_addr_17=0x52
port_phy_addr_18=0x53
port_phy_addr_19=0x54
port_phy_addr_20=0x55
port_phy_addr_21=0x56
port_phy_addr_22=0x57
port_phy_addr_23=0x58
port_phy_addr_24=0x59
phy_port_primary_and_offset_17=0x1100
phy_port_primary_and_offset_18=0x1101
phy_port_primary_and_offset_19=0x1102
phy_port_primary_and_offset_20=0x1103
phy_port_primary_and_offset_21=0x1104
phy_port_primary_and_offset_22=0x1105
phy_port_primary_and_offset_23=0x1106
phy_port_primary_and_offset_24=0x1107
dport_map_port_17=42
dport_map_port_18=41
dport_map_port_19=44
dport_map_port_20=43
dport_map_port_21=46
dport_map_port_22=45
dport_map_port_23=48
dport_map_port_24=47
portmap_17=17:1
portmap_18=18:1
portmap_19=19:1
portmap_20=20:1
portmap_21=21:1
portmap_22=22:1
portmap_23=23:1
portmap_24=24:1
phy_chain_rx_lane_map_physical{17.0}=0x3210
phy_chain_rx_lane_map_physical{18.0}=0x3210
phy_chain_rx_lane_map_physical{19.0}=0x3210
phy_chain_rx_lane_map_physical{20.0}=0x3210
phy_chain_rx_lane_map_physical{21.0}=0x3210
phy_chain_rx_lane_map_physical{22.0}=0x3210
phy_chain_rx_lane_map_physical{23.0}=0x3210
phy_chain_rx_lane_map_physical{24.0}=0x3210
phy_chain_tx_lane_map_physical{17.0}=0x3210
phy_chain_tx_lane_map_physical{18.0}=0x3210
phy_chain_tx_lane_map_physical{19.0}=0x3210
phy_chain_tx_lane_map_physical{20.0}=0x3210
phy_chain_tx_lane_map_physical{21.0}=0x3210
phy_chain_tx_lane_map_physical{22.0}=0x3210
phy_chain_tx_lane_map_physical{23.0}=0x3210
phy_chain_tx_lane_map_physical{24.0}=0x3210
phy_chain_rx_polarity_flip_physical{17.0}=0x0
phy_chain_rx_polarity_flip_physical{18.0}=0x0
phy_chain_rx_polarity_flip_physical{19.0}=0x0
phy_chain_rx_polarity_flip_physical{20.0}=0x0
phy_chain_rx_polarity_flip_physical{21.0}=0x0
phy_chain_rx_polarity_flip_physical{22.0}=0x0
phy_chain_rx_polarity_flip_physical{23.0}=0x0
phy_chain_rx_polarity_flip_physical{24.0}=0x0
phy_chain_tx_polarity_flip_physical{17.0}=0x0
phy_chain_tx_polarity_flip_physical{18.0}=0x0
phy_chain_tx_polarity_flip_physical{19.0}=0x0
phy_chain_tx_polarity_flip_physical{20.0}=0x0
phy_chain_tx_polarity_flip_physical{21.0}=0x0
phy_chain_tx_polarity_flip_physical{22.0}=0x0
phy_chain_tx_polarity_flip_physical{23.0}=0x0
phy_chain_tx_polarity_flip_physical{24.0}=0x0
#PHY1 U53 xx1, MDC/MDIO0, PHYADDR:0x00-0x07, 0x08
port_phy_addr_25=0x00
port_phy_addr_26=0x01
port_phy_addr_27=0x02
port_phy_addr_28=0x03
port_phy_addr_29=0x04
port_phy_addr_30=0x05
port_phy_addr_31=0x06
port_phy_addr_32=0x07
phy_port_primary_and_offset_25=0x1900
phy_port_primary_and_offset_26=0x1901
phy_port_primary_and_offset_27=0x1902
phy_port_primary_and_offset_28=0x1903
phy_port_primary_and_offset_29=0x1904
phy_port_primary_and_offset_30=0x1905
phy_port_primary_and_offset_31=0x1906
phy_port_primary_and_offset_32=0x1907
dport_map_port_25=2
dport_map_port_26=1
dport_map_port_27=4
dport_map_port_28=3
dport_map_port_29=6
dport_map_port_30=5
dport_map_port_31=8
dport_map_port_32=7
portmap_25=25:1
portmap_26=26:1
portmap_27=27:1
portmap_28=28:1
portmap_29=29:1
portmap_30=30:1
portmap_31=31:1
portmap_32=32:1
phy_chain_rx_lane_map_physical{25.0}=0x3210
phy_chain_rx_lane_map_physical{26.0}=0x3210
phy_chain_rx_lane_map_physical{27.0}=0x3210
phy_chain_rx_lane_map_physical{28.0}=0x3210
phy_chain_rx_lane_map_physical{29.0}=0x3210
phy_chain_rx_lane_map_physical{30.0}=0x3210
phy_chain_rx_lane_map_physical{31.0}=0x3210
phy_chain_rx_lane_map_physical{32.0}=0x3210
phy_chain_tx_lane_map_physical{25.0}=0x3210
phy_chain_tx_lane_map_physical{26.0}=0x3210
phy_chain_tx_lane_map_physical{27.0}=0x3210
phy_chain_tx_lane_map_physical{28.0}=0x3210
phy_chain_tx_lane_map_physical{29.0}=0x3210
phy_chain_tx_lane_map_physical{30.0}=0x3210
phy_chain_tx_lane_map_physical{31.0}=0x3210
phy_chain_tx_lane_map_physical{32.0}=0x3210
phy_chain_rx_polarity_flip_physical{25.0}=0x0
phy_chain_rx_polarity_flip_physical{26.0}=0x0
phy_chain_rx_polarity_flip_physical{27.0}=0x0
phy_chain_rx_polarity_flip_physical{28.0}=0x0
phy_chain_rx_polarity_flip_physical{29.0}=0x0
phy_chain_rx_polarity_flip_physical{30.0}=0x0
phy_chain_rx_polarity_flip_physical{31.0}=0x0
phy_chain_rx_polarity_flip_physical{32.0}=0x0
phy_chain_tx_polarity_flip_physical{25.0}=0x0
phy_chain_tx_polarity_flip_physical{26.0}=0x0
phy_chain_tx_polarity_flip_physical{27.0}=0x0
phy_chain_tx_polarity_flip_physical{28.0}=0x0
phy_chain_tx_polarity_flip_physical{29.0}=0x0
phy_chain_tx_polarity_flip_physical{30.0}=0x0
phy_chain_tx_polarity_flip_physical{31.0}=0x0
phy_chain_tx_polarity_flip_physical{32.0}=0x0
#MCQ2
port_gmii_mode_33=1 #Q mode
#PHY2 U54 x1x, MDC/MDIO0, PHYADDR:0x09-0x10, 0x11
port_phy_addr_33=0x0D
port_phy_addr_34=0x0E
port_phy_addr_35=0x0F
port_phy_addr_36=0x10
port_phy_addr_37=0x09
port_phy_addr_38=0x0A
port_phy_addr_39=0x0B
port_phy_addr_40=0x0C
phy_port_primary_and_offset_33=0x2504
phy_port_primary_and_offset_34=0x2505
phy_port_primary_and_offset_35=0x2506
phy_port_primary_and_offset_36=0x2507
phy_port_primary_and_offset_37=0x2500
phy_port_primary_and_offset_38=0x2501
phy_port_primary_and_offset_39=0x2502
phy_port_primary_and_offset_40=0x2503
dport_map_port_33=14
dport_map_port_34=13
dport_map_port_35=16
dport_map_port_36=15
dport_map_port_37=10
dport_map_port_38=9
dport_map_port_39=12
dport_map_port_40=11
portmap_33=33:1
portmap_34=34:1
portmap_35=35:1
portmap_36=36:1
portmap_37=37:1
portmap_38=38:1
portmap_39=39:1
portmap_40=40:1
phy_chain_rx_lane_map_physical{33.0}=0x3210
phy_chain_rx_lane_map_physical{34.0}=0x3210
phy_chain_rx_lane_map_physical{35.0}=0x3210
phy_chain_rx_lane_map_physical{36.0}=0x3210
phy_chain_rx_lane_map_physical{37.0}=0x3210
phy_chain_rx_lane_map_physical{38.0}=0x3210
phy_chain_rx_lane_map_physical{39.0}=0x3210
phy_chain_rx_lane_map_physical{40.0}=0x3210
phy_chain_tx_lane_map_physical{33.0}=0x3210
phy_chain_tx_lane_map_physical{34.0}=0x3210
phy_chain_tx_lane_map_physical{35.0}=0x3210
phy_chain_tx_lane_map_physical{36.0}=0x3210
phy_chain_tx_lane_map_physical{37.0}=0x3210
phy_chain_tx_lane_map_physical{38.0}=0x3210
phy_chain_tx_lane_map_physical{39.0}=0x3210
phy_chain_tx_lane_map_physical{40.0}=0x3210
phy_chain_rx_polarity_flip_physical{33.0}=0x1
phy_chain_rx_polarity_flip_physical{34.0}=0x1
phy_chain_rx_polarity_flip_physical{35.0}=0x1
phy_chain_rx_polarity_flip_physical{36.0}=0x1
phy_chain_rx_polarity_flip_physical{37.0}=0x1
phy_chain_rx_polarity_flip_physical{38.0}=0x1
phy_chain_rx_polarity_flip_physical{39.0}=0x1
phy_chain_rx_polarity_flip_physical{40.0}=0x1
phy_chain_tx_polarity_flip_physical{33.0}=0x1
phy_chain_tx_polarity_flip_physical{34.0}=0x1
phy_chain_tx_polarity_flip_physical{35.0}=0x1
phy_chain_tx_polarity_flip_physical{36.0}=0x1
phy_chain_tx_polarity_flip_physical{37.0}=0x1
phy_chain_tx_polarity_flip_physical{38.0}=0x1
phy_chain_tx_polarity_flip_physical{39.0}=0x1
phy_chain_tx_polarity_flip_physical{40.0}=0x1
#PHY3 U55 11x, MDC/MDIO0, PHYADDR:0x12-0x19, 0x1A
port_phy_addr_41=0x16
port_phy_addr_42=0x17
port_phy_addr_43=0x18
port_phy_addr_44=0x19
port_phy_addr_45=0x12
port_phy_addr_46=0x13
port_phy_addr_47=0x14
port_phy_addr_48=0x15
phy_port_primary_and_offset_41=0x2D00
phy_port_primary_and_offset_42=0x2D01
phy_port_primary_and_offset_43=0x2D02
phy_port_primary_and_offset_44=0x2D03
phy_port_primary_and_offset_45=0x2D04
phy_port_primary_and_offset_46=0x2D05
phy_port_primary_and_offset_47=0x2D06
phy_port_primary_and_offset_48=0x2D07
dport_map_port_41=22
dport_map_port_42=21
dport_map_port_43=24
dport_map_port_44=23
dport_map_port_45=18
dport_map_port_46=17
dport_map_port_47=20
dport_map_port_48=19
portmap_41=41:1
portmap_42=42:1
portmap_43=43:1
portmap_44=44:1
portmap_45=45:1
portmap_46=46:1
portmap_47=47:1
portmap_48=48:1
phy_chain_rx_lane_map_physical{41.0}=0x3210
phy_chain_rx_lane_map_physical{42.0}=0x3210
phy_chain_rx_lane_map_physical{43.0}=0x3210
phy_chain_rx_lane_map_physical{44.0}=0x3210
phy_chain_rx_lane_map_physical{45.0}=0x3210
phy_chain_rx_lane_map_physical{46.0}=0x3210
phy_chain_rx_lane_map_physical{47.0}=0x3210
phy_chain_rx_lane_map_physical{48.0}=0x3210
phy_chain_tx_lane_map_physical{41.0}=0x3210
phy_chain_tx_lane_map_physical{42.0}=0x3210
phy_chain_tx_lane_map_physical{43.0}=0x3210
phy_chain_tx_lane_map_physical{44.0}=0x3210
phy_chain_tx_lane_map_physical{45.0}=0x3210
phy_chain_tx_lane_map_physical{46.0}=0x3210
phy_chain_tx_lane_map_physical{47.0}=0x3210
phy_chain_tx_lane_map_physical{48.0}=0x3210
phy_chain_rx_polarity_flip_physical{41.0}=0x1
phy_chain_rx_polarity_flip_physical{42.0}=0x1
phy_chain_rx_polarity_flip_physical{43.0}=0x1
phy_chain_rx_polarity_flip_physical{44.0}=0x1
phy_chain_rx_polarity_flip_physical{45.0}=0x1
phy_chain_rx_polarity_flip_physical{46.0}=0x1
phy_chain_rx_polarity_flip_physical{47.0}=0x1
phy_chain_rx_polarity_flip_physical{48.0}=0x1
phy_chain_tx_polarity_flip_physical{41.0}=0x1
phy_chain_tx_polarity_flip_physical{42.0}=0x1
phy_chain_tx_polarity_flip_physical{43.0}=0x1
phy_chain_tx_polarity_flip_physical{44.0}=0x1
phy_chain_tx_polarity_flip_physical{45.0}=0x1
phy_chain_tx_polarity_flip_physical{46.0}=0x1
phy_chain_tx_polarity_flip_physical{47.0}=0x1
phy_chain_tx_polarity_flip_physical{48.0}=0x1
#3x PM4x25 (3 * 4 = 12 physical ports)
#FC0
dport_map_port_49=51
dport_map_port_50=50
dport_map_port_51=49
dport_map_port_52=52
portmap_49=65:25
portmap_50=66:25
portmap_51=67:25
portmap_52=68:25
#FC1
dport_map_port_53=57
dport_map_port_54=58
dport_map_port_55=59
dport_map_port_56=60
portmap_53=69:100:4
#portmap_55=71:50
#portmap_54=70:25
#portmap_55=71:25
#portmap_56=72:25
#FC2
dport_map_port_57=53
dport_map_port_58=54
dport_map_port_59=55
dport_map_port_60=56
portmap_57=73:100:4
#portmap_59=75:50
#portmap_58=74:25
#portmap_59=75:25
#portmap_60=76:25
#4x PM4x10 (4 * 4 = 16 physical ports)
#MC0 No connection
#MC1 No connection
#MC2 No connection
#MC3 No connection
#portmap_=49:10
#portmap_=50:10
#portmap_=51:10
#portmap_=52:10
#portmap_=53:10
#portmap_=54:10
#portmap_=55:10
#portmap_=56:10
#portmap_=57:10
#portmap_=58:10
#portmap_=59:10
#portmap_=60:10
#portmap_=61:10
#portmap_=62:10
#portmap_=63:10
#portmap_=64:10

55
device/accton/x86_64-accton_as4630_54pe-r0/Accton-AS4630-54PE/port_config.ini Executable file
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# name lanes alias index
Ethernet0 26 thousandE1 0
Ethernet1 25 thousandE2 1
Ethernet2 28 thousandE3 2
Ethernet3 27 thousandE4 3
Ethernet4 30 thousandE5 4
Ethernet5 29 thousandE6 5
Ethernet6 32 thousandE7 6
Ethernet7 31 thousandE8 7
Ethernet8 38 thousandE9 8
Ethernet9 37 thousandE10 9
Ethernet10 40 thousandE11 10
Ethernet11 39 thousandE12 11
Ethernet12 34 thousandE13 12
Ethernet13 33 thousandE14 13
Ethernet14 36 thousandE15 14
Ethernet15 35 thousandE16 15
Ethernet16 46 thousandE17 16
Ethernet17 45 thousandE18 17
Ethernet18 48 thousandE19 18
Ethernet19 47 thousandE20 19
Ethernet20 42 thousandE21 20
Ethernet21 41 thousandE22 21
Ethernet22 44 thousandE23 22
Ethernet23 43 thousandE24 23
Ethernet24 2 thousandE25 24
Ethernet25 1 thousandE26 25
Ethernet26 4 thousandE27 26
Ethernet27 3 thousandE28 27
Ethernet28 6 thousandE29 28
Ethernet29 5 thousandE30 29
Ethernet30 8 thousandE31 30
Ethernet31 7 thousandE32 31
Ethernet32 10 thousandE33 32
Ethernet33 9 thousandE34 33
Ethernet34 12 thousandE35 34
Ethernet35 11 thousandE36 35
Ethernet36 14 thousandE37 36
Ethernet37 13 thousandE38 37
Ethernet38 16 thousandE39 38
Ethernet39 15 thousandE40 39
Ethernet40 18 thousandE41 40
Ethernet41 17 thousandE42 41
Ethernet42 20 thousandE43 42
Ethernet43 19 thousandE44 43
Ethernet44 22 thousandE45 44
Ethernet45 21 thousandE46 45
Ethernet46 24 thousandE47 46
Ethernet47 23 thousandE48 47
Ethernet48 67 twentyfiveGigE49 48
Ethernet49 66 twentyfiveGigE50 49
Ethernet50 65 twentyfiveGigE51 50
Ethernet51 68 twentyfiveGigE52 51
Ethernet52 73,74,75,76 hundredGigE53 52
Ethernet56 69,70,71,72 hundredGigE54 56

1
device/accton/x86_64-accton_as4630_54pe-r0/Accton-AS4630-54PE/sai.profile Executable file
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/hx5-as4630-48x1G+4x25G+2x100G.bcm

1
device/accton/x86_64-accton_as4630_54pe-r0/default_sku Executable file
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Accton-AS4630-54PE t1

3
device/accton/x86_64-accton_as4630_54pe-r0/installer.conf Executable file
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CONSOLE_PORT=0x3f8
CONSOLE_DEV=0
CONSOLE_SPEED=115200

2
device/accton/x86_64-accton_as4630_54pe-r0/led_proc_init.soc Executable file
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led start
led auto on

21
device/accton/x86_64-accton_as4630_54pe-r0/plugins/eeprom.py Executable file
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#!/usr/bin/env python
try:
import exceptions
import binascii
import time
import optparse
import warnings
import os
import sys
from sonic_eeprom import eeprom_base
from sonic_eeprom import eeprom_tlvinfo
import subprocess
except ImportError, e:
raise ImportError (str(e) + "- required module not found")
class board(eeprom_tlvinfo.TlvInfoDecoder):
_TLV_INFO_MAX_LEN = 256
def __init__(self, name, path, cpld_root, ro):
self.eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
super(board, self).__init__(self.eeprom_path, 0, '', True)

61
device/accton/x86_64-accton_as4630_54pe-r0/plugins/psuutil.py Executable file
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#!/usr/bin/env python
#############################################################################
# Accton
#
# Module contains an implementation of SONiC PSU Base API and
# provides the PSUs status which are available in the platform
#
#############################################################################
import os.path
try:
from sonic_psu.psu_base import PsuBase
except ImportError as e:
raise ImportError (str(e) + "- required module not found")
class PsuUtil(PsuBase):
"""Platform-specific PSUutil class"""
def __init__(self):
PsuBase.__init__(self)
self.psu_path = "/sys/bus/i2c/devices/"
self.psu_presence = "/psu_present"
self.psu_oper_status = "/psu_power_good"
self.psu_mapping = {
1: "10-0050",
2: "11-0051",
}
def get_num_psus(self):
return len(self.psu_mapping)
def get_psu_status(self, index):
if index is None:
return False
status = 0
node = self.psu_path + self.psu_mapping[index]+self.psu_oper_status
try:
with open(node, 'r') as power_status:
status = int(power_status.read())
except IOError:
return False
return status == 1
def get_psu_presence(self, index):
if index is None:
return False
status = 0
node = self.psu_path + self.psu_mapping[index] + self.psu_presence
try:
with open(node, 'r') as presence_status:
status = int(presence_status.read())
except IOError:
return False
return status == 1

103
device/accton/x86_64-accton_as4630_54pe-r0/plugins/sfputil.py Executable file
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# sfputil.py
#
# Platform-specific SFP transceiver interface for SONiC
#
try:
import time
from sonic_sfp.sfputilbase import SfpUtilBase
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
class SfpUtil(SfpUtilBase):
"""Platform-specific SfpUtil class"""
PORT_START = 48
PORT_END = 53
PORTS_IN_BLOCK = 54
BASE_OOM_PATH = "/sys/bus/i2c/devices/{0}-0050/"
BASE_CPLD_PATH = "/sys/bus/i2c/devices/3-0060/"
_port_to_is_present = {}
_port_to_lp_mode = {}
_port_to_eeprom_mapping = {}
_port_to_i2c_mapping = {
48: [18],
49: [19],
50: [20],
51: [21],
52: [22],
53: [23],
}
@property
def port_start(self):
return self.PORT_START
@property
def port_end(self):
return self.PORT_END
@property
def qsfp_ports(self):
return range(self.PORT_START, self.PORTS_IN_BLOCK + 1)
@property
def port_to_eeprom_mapping(self):
return self._port_to_eeprom_mapping
def __init__(self):
eeprom_path = self.BASE_OOM_PATH + "eeprom"
for x in range(0, self.port_end+1):
if x < 48:
self.port_to_eeprom_mapping[x] = eeprom_path.format(0)
else:
self.port_to_eeprom_mapping[x] = eeprom_path.format(
self._port_to_i2c_mapping[x][0])
SfpUtilBase.__init__(self)
def get_presence(self, port_num):
# Check for invalid port_num
if port_num < self.port_start or port_num > self.port_end:
return False
present_path = self.BASE_CPLD_PATH + "module_present_" + str(port_num+1)
self.__port_to_is_present = present_path
try:
val_file = open(self.__port_to_is_present)
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
content = val_file.readline().rstrip()
val_file.close()
# content is a string, either "0" or "1"
if content == "1":
return True
return False
def get_low_power_mode(self, port_num):
raise NotImplementedError
def set_low_power_mode(self, port_num, lpmode):
raise NotImplementedError
def reset(self, port_num):
raise NotImplementedError
def get_transceiver_change_event(self):
"""
TODO: This function need to be implemented
when decide to support monitoring SFP(Xcvrd)
on this platform.
"""
raise NotImplementedError

73
device/accton/x86_64-accton_as5812_54x-r0/Accton-AS5812-54X/port_config.ini Executable file
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# name lanes alias index
Ethernet0 13 tenGigE0 1
Ethernet1 14 tenGigE1 2
Ethernet2 15 tenGigE2 3
Ethernet3 16 tenGigE3 4
Ethernet4 21 tenGigE4 5
Ethernet5 22 tenGigE5 6
Ethernet6 23 tenGigE6 7
Ethernet7 24 tenGigE7 8
Ethernet8 25 tenGigE8 9
Ethernet9 26 tenGigE9 10
Ethernet10 27 tenGigE10 11
Ethernet11 28 tenGigE11 12
Ethernet12 29 tenGigE12 13
Ethernet13 30 tenGigE13 14
Ethernet14 31 tenGigE14 15
Ethernet15 32 tenGigE15 16
Ethernet16 45 tenGigE16 17
Ethernet17 46 tenGigE17 18
Ethernet18 47 tenGigE18 19
Ethernet19 48 tenGigE19 20
Ethernet20 49 tenGigE20 21
Ethernet21 50 tenGigE21 22
Ethernet22 51 tenGigE22 23
Ethernet23 52 tenGigE23 24
Ethernet24 53 tenGigE24 25
Ethernet25 54 tenGigE25 26
Ethernet26 55 tenGigE26 27
Ethernet27 56 tenGigE27 28
Ethernet28 57 tenGigE28 29
Ethernet29 58 tenGigE29 30
Ethernet30 59 tenGigE30 31
Ethernet31 60 tenGigE31 32
Ethernet32 61 tenGigE32 33
Ethernet33 62 tenGigE33 34
Ethernet34 63 tenGigE34 35
Ethernet35 64 tenGigE35 36
Ethernet36 65 tenGigE36 37
Ethernet37 66 tenGigE37 38
Ethernet38 67 tenGigE38 39
Ethernet39 68 tenGigE39 40
Ethernet40 69 tenGigE40 41
Ethernet41 70 tenGigE41 42
Ethernet42 71 tenGigE42 43
Ethernet43 72 tenGigE43 44
Ethernet44 73 tenGigE44 45
Ethernet45 74 tenGigE45 46
Ethernet46 75 tenGigE46 47
Ethernet47 76 tenGigE47 48
Ethernet48 97 tenGigE48 49
Ethernet49 98 tenGigE49 50
Ethernet50 99 tenGigE50 51
Ethernet51 100 tenGigE51 52
Ethernet52 101 tenGigE52 53
Ethernet53 102 tenGigE53 54
Ethernet54 103 tenGigE54 55
Ethernet55 104 tenGigE55 56
Ethernet56 81 tenGigE56 57
Ethernet57 82 tenGigE57 58
Ethernet58 83 tenGigE58 59
Ethernet59 84 tenGigE59 60
Ethernet60 105 tenGigE60 61
Ethernet61 106 tenGigE61 62
Ethernet62 107 tenGigE62 63
Ethernet63 108 tenGigE63 64
Ethernet64 109 tenGigE64 65
Ethernet65 110 tenGigE65 66
Ethernet66 111 tenGigE66 67
Ethernet67 112 tenGigE67 68
Ethernet68 77 tenGigE68 69
Ethernet69 78 tenGigE69 70
Ethernet70 79 tenGigE70 71
EthernEt71 80 tenGigE71 72

1
device/accton/x86_64-accton_as5812_54x-r0/Accton-AS5812-54X/sai.profile Executable file
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/td2-as5812-72x10G.config.bcm

148
device/accton/x86_64-accton_as5812_54x-r0/Accton-AS5812-54X/td2-as5812-72x10G.config.bcm Normal file
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os=unix
bcm_stat_flags=0
parity_enable=0
parity_correction=0
bcm_num_cos=8
l2_mem_entries=32768
l3_mem_entries=16384
l3_alpm_enable=2
ipv6_lpm_128b_enable=1
mmu_lossless=0
lls_num_l2uc=12
module_64ports=0
#SFI
serdes_if_type=9
port_init_cl72=0
phy_an_c73=5 # TSCMOD_CL73_CL37
#sdk6.5.5 only supports 156(default) or 125
#xgxs_lcpll_xtal_refclk=1
tslam_dma_enable=1
table_dma_enable=1
#for 72 ports with 48 10G ports and 6 40G ports for breakout mode
pbmp_oversubscribe=0x1fffffffffffffffffe
pbmp_xport_xe=0x1fffffffffffffffffe
rate_ext_mdio_divisor=96
#SFP+ 1-4 from WC3
portmap_1=13:10
portmap_2=14:10
portmap_3=15:10
portmap_4=16:10
#SFP+ 5-8 from WC5
portmap_5=21:10
portmap_6=22:10
portmap_7=23:10
portmap_8=24:10
#SFP+ 9-12 from WC6
portmap_9=25:10
portmap_10=26:10
portmap_11=27:10
portmap_12=28:10
#SFP+ 13-16 from WC7
portmap_13=29:10
portmap_14=30:10
portmap_15=31:10
portmap_16=32:10
#SFP+ 17-20 from WC11
portmap_17=45:10
portmap_18=46:10
portmap_19=47:10
portmap_20=48:10
#SFP+ 21-24 from WC12
portmap_21=49:10
portmap_22=50:10
portmap_23=51:10
portmap_24=52:10
#SFP+ 25-28 from WC13
portmap_25=53:10
portmap_26=54:10
portmap_27=55:10
portmap_28=56:10
#SFP+ 29-32 from WC14
portmap_29=57:10
portmap_30=58:10
portmap_31=59:10
portmap_32=60:10
#SFP+ 33-36 from WC15
portmap_33=61:10
portmap_34=62:10
portmap_35=63:10
portmap_36=64:10
#SFP+ 37-40 from WC16
portmap_37=65:10
portmap_38=66:10
portmap_39=67:10
portmap_40=68:10
#SFP+ 41-44 from WC17
portmap_41=69:10
portmap_42=70:10
portmap_43=71:10
portmap_44=72:10
#SFP+ 45-48 from WC18
portmap_45=73:10
portmap_46=74:10
portmap_47=75:10
portmap_48=76:10
# QSFP+ 49/WC24/port 49
portmap_49=97:10
portmap_50=98:10
portmap_51=99:10
portmap_52=100:10
# QSFP+ 51/WC25/port 50
portmap_53=101:10
portmap_54=102:10
portmap_55=103:10
portmap_56=104:10
# QSFP+ 53/WC20/port 51
portmap_57=81:10
portmap_58=82:10
portmap_59=83:10
portmap_60=84:10
# QSFP+ 50/WC26/port 52
portmap_61=105:10
portmap_62=106:10
portmap_63=107:10
portmap_64=108:10
# QSFP+ 52/WC27/port 53
portmap_65=109:10
portmap_66=110:10
portmap_67=111:10
portmap_68=112:10
# QSFP+ 54/WC19/port 54
portmap_69=77:10
portmap_70=78:10
portmap_71=79:10
portmap_72=80:10
# L3 ECMP
# - In Trident2, VP LAGs share the same table as ECMP group table.
# The first N entries are reserved for VP LAGs, where N is the value of the
# config property "max_vp_lags". By default this was set to 256
l3_max_ecmp_mode=1
max_vp_lags=0
stable_size=0x2000000

1
device/accton/x86_64-accton_as5812_54x-r0/default_sku Normal file
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Accton-AS5812-54X t1

3
device/accton/x86_64-accton_as5812_54x-r0/installer.conf Normal file
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CONSOLE_PORT=0x2f8
CONSOLE_DEV=1
CONSOLE_SPEED=115200

162
device/accton/x86_64-accton_as5812_54x-r0/led_proc_init.soc Normal file
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# LED setting for active
# -----------------------------------------------------------------------------
# for as5812_54x (48xg+6qxg)
#
# on green - if link up
# off - if link down
# blink - if active
# -----------------------------------------------------------------------------
m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_63=0
m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_62=1
m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_61=2
m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=3
m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_59=4
m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_58=5
m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_57=6
m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=7
m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_55=8
m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_54=9
m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_53=10
m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=11
m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_51=12
m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_50=13
m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_49=14
m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=15
m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_35=16
m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_34=17
m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_33=18
m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=19
m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_39=20
m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_38=21
m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_37=22
m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=23
m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_43=24
m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_42=25
m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_41=26
m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=27
m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_47=28
m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_46=29
m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_45=30
m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=31
m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_31=32
m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_30=33
m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_29=34
m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=35
m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_27=36
m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_26=37
m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_25=38
m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=39
m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_23=40
m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_22=41
m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_21=42
m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=43
m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_19=44
m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_18=45
m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_17=46
m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=47
m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_3=48
m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_2=49
m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_1=50
m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=51
m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_7=52
m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_6=53
m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_5=54
m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=55
m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_11=56
m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_10=57
m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_9=58
m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=59
m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_15=60
m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_14=61
m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_13=62
m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=63
m CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_63=0
m CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_62=1
m CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_61=2
m CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=3
m CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_59=4
m CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_58=5
m CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_57=6
m CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=7
m CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_55=8
m CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_54=9
m CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_53=10
m CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=11
m CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_51=12
m CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_50=13
m CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_49=14
m CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=15
m CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_35=16
m CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_34=17
m CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_33=18
m CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=19
m CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_39=20
m CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_38=21
m CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_37=22
m CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=23
m CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_43=24
m CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_42=25
m CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_41=26
m CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=27
m CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_47=28
m CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_46=29
m CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_45=30
m CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=31
m CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_31=32
m CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_30=33
m CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_29=34
m CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=35
m CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_27=36
m CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_26=37
m CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_25=38
m CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=39
m CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_23=40
m CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_22=41
m CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_21=42
m CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=43
m CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_19=44
m CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_18=45
m CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_17=46
m CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=47
m CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_3=48
m CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_2=49
m CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_1=50
m CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=51
m CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_7=52
m CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_6=53
m CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_5=54
m CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=55
m CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_11=56
m CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_10=57
m CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_9=58
m CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=59
m CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_15=60
m CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_14=61
m CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_13=62
m CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=63
led 0 stop
led 0 prog \
06 FE 80 D2 19 71 08 E0 60 FE E9 D2 0F 75 10 81 \
61 FD 02 3F 60 FF 28 32 0F 87 67 4A 96 FF 06 FF \
D2 2B 74 16 02 1F 60 FF 28 32 0F 87 67 4A 96 FF \
06 FF D2 13 74 28 02 0F 60 FF 28 32 0F 87 67 4A \
96 FF 06 FF D2 0B 74 3A 3A 48 32 07 32 08 C7 32 \
04 C7 97 71 57 77 69 32 00 32 01 B7 97 71 63 32 \
0E 77 6B 26 FD 97 27 77 6B 32 0F 87 57 00 00 00
led 0 start
led 1 stop
led 1 prog \
06 FE 80 D2 19 71 08 E0 60 FE E9 D2 0F 75 10 81 \
61 FD 02 20 67 89 02 24 67 89 02 10 67 89 02 28 \
67 89 02 2C 67 89 02 0C 67 89 02 2C 67 79 02 28 \
67 79 02 24 67 79 02 20 67 79 02 10 67 79 02 0C \
67 79 02 0B 60 FF 28 32 0F 87 67 56 96 FF 06 FF \
D2 FF 74 46 3A 36 32 07 32 08 C7 32 04 C7 97 71 \
63 77 75 32 00 32 01 B7 97 71 6F 32 0E 77 77 26 \
FD 97 27 77 77 32 0F 87 57 12 A0 F8 15 1A 01 75 \
85 28 67 56 57 32 0F 87 57 12 A0 F8 15 1A 01 71 \
A1 28 67 56 80 28 67 56 80 28 67 56 80 28 67 56 \
57 32 0F 87 32 0F 87 32 0F 87 32 0F 87 57 00 00
led 1 start

24
device/accton/x86_64-accton_as5812_54x-r0/plugins/eeprom.py Normal file
View File

@ -0,0 +1,24 @@
#!/usr/bin/env python
try:
import exceptions
import binascii
import time
import optparse
import warnings
import os
import sys
from sonic_eeprom import eeprom_base
from sonic_eeprom import eeprom_tlvinfo
import subprocess
except ImportError, e:
raise ImportError (str(e) + "- required module not found")
class board(eeprom_tlvinfo.TlvInfoDecoder):
_TLV_INFO_MAX_LEN = 256
def __init__(self, name, path, cpld_root, ro):
self.eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
#Two i2c buses might get flipped order, check them both.
if not os.path.exists(self.eeprom_path):
self.eeprom_path = "/sys/bus/i2c/devices/0-0057/eeprom"
super(board, self).__init__(self.eeprom_path, 0, '', True)

61
device/accton/x86_64-accton_as5812_54x-r0/plugins/psuutil.py Executable file
View File

@ -0,0 +1,61 @@
#!/usr/bin/env python
#############################################################################
# Accton
#
# Module contains an implementation of SONiC PSU Base API and
# provides the PSUs status which are available in the platform
#
#############################################################################
import os.path
try:
from sonic_psu.psu_base import PsuBase
except ImportError as e:
raise ImportError (str(e) + "- required module not found")
class PsuUtil(PsuBase):
"""Platform-specific PSUutil class"""
def __init__(self):
PsuBase.__init__(self)
self.psu_path = "/sys/bus/i2c/devices/"
self.psu_presence = "/psu_present"
self.psu_oper_status = "/psu_power_good"
self.psu_mapping = {
1: "57-0038",
2: "58-003b",
}
def get_num_psus(self):
return len(self.psu_mapping)
def get_psu_status(self, index):
if index is None:
return False
status = 0
node = self.psu_path + self.psu_mapping[index]+self.psu_oper_status
try:
with open(node, 'r') as power_status:
status = int(power_status.read())
except IOError:
return False
return status == 1
def get_psu_presence(self, index):
if index is None:
return False
status = 0
node = self.psu_path + self.psu_mapping[index] + self.psu_presence
try:
with open(node, 'r') as presence_status:
status = int(presence_status.read())
except IOError:
return False
return status == 1

311
device/accton/x86_64-accton_as5812_54x-r0/plugins/sfputil.py Executable file
View File

@ -0,0 +1,311 @@
# sfputil.py
#
# Platform-specific SFP transceiver interface for SONiC
#
try:
import time
import os
import pickle
from ctypes import create_string_buffer
from sonic_sfp.sfputilbase import SfpUtilBase
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
class SfpUtil(SfpUtilBase):
"""Platform-specific SfpUtil class"""
PORT_START = 1
PORT_END = 72
PORTS_IN_BLOCK = 72
QSFP_PORT_START = 48
QSFP_PORT_END = 72
BASE_VAL_PATH = "/sys/class/i2c-adapter/i2c-{0}/{1}-0050/"
BASE_OOM_PATH = "/sys/bus/i2c/devices/{0}-0050/"
BASE_CPLD2_PATH = "/sys/bus/i2c/devices/{0}-0061/"
BASE_CPLD3_PATH = "/sys/bus/i2c/devices/{0}-0062/"
I2C_BUS_ORDER = -1
#The sidebands of QSFP is different.
#present is in-order.
#But lp_mode and reset are not.
qsfp_sb_map = [1, 3, 5, 2, 4, 6]
_port_to_is_present = {}
_port_to_lp_mode = {}
_port_to_eeprom_mapping = {}
_port_to_i2c_mapping = {
1: [1, 2],
2: [2, 3],
3: [3, 4],
4: [4, 5],
5: [5, 6],
6: [6, 7],
7: [7, 8],
8: [8, 9],
9: [9, 10],
10: [10, 11],
11: [11, 12],
12: [12, 13],
13: [13, 14],
14: [14, 15],
15: [15, 16],
16: [16, 17],
17: [17, 18],
18: [18, 19],
19: [19, 20],
20: [20, 21],
21: [21, 22],
22: [22, 23],
23: [23, 24],
24: [24, 25],
25: [25, 26],
26: [26, 27],
27: [27, 28],
28: [28, 29],
29: [29, 30],
30: [30, 31],
31: [31, 32],
32: [32, 33],
33: [33, 34],
34: [34, 35],
35: [35, 36],
36: [36, 37],
37: [37, 38],
38: [38, 39],
39: [39, 40],
40: [40, 41],
41: [41, 42],
42: [42, 43],
43: [43, 44],
44: [44, 45],
45: [45, 46],
46: [46, 47],
47: [47, 48],
48: [48, 49],
49: [49, 50],#QSFP49
50: [49, 50],
51: [49, 50],
52: [49, 50],
53: [50, 52],#QSFP50
54: [50, 52],
55: [50, 52],
56: [50, 52],
57: [51, 54],#QSFP51
58: [51, 54],
59: [51, 54],
60: [51, 54],
61: [52, 51],#QSFP52
62: [52, 51],
63: [52, 51],
64: [52, 51],
65: [53, 53],#QSFP53
66: [53, 53],
67: [53, 53],
68: [53, 53],
69: [54, 55],#QSFP54
70: [54, 55],
71: [54, 55],
72: [54, 55],
}
@property
def port_start(self):
return self.PORT_START
@property
def port_end(self):
return self.PORT_END
@property
def qsfp_port_start(self):
return self.QSFP_PORT_START
@property
def qsfp_port_end(self):
return self.QSFP_PORT_END
@property
def qsfp_ports(self):
return range(self.QSFP_PORT_START, self.PORTS_IN_BLOCK + 1)
@property
def port_to_eeprom_mapping(self):
return self._port_to_eeprom_mapping
def __init__(self):
eeprom_path = self.BASE_OOM_PATH + "eeprom"
for x in range(self.port_start, self.port_end+1):
self.port_to_eeprom_mapping[x] = eeprom_path.format(
self._port_to_i2c_mapping[x][1]
)
SfpUtilBase.__init__(self)
#Two i2c buses might get flipped order, check them both.
def update_i2c_order(self):
if os.path.exists("/tmp/accton_util.p"):
self.I2C_BUS_ORDER = pickle.load(open("/tmp/accton_util.p", "rb"))
else:
if self.I2C_BUS_ORDER < 0:
eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
if os.path.exists(eeprom_path):
self.I2C_BUS_ORDER = 0
eeprom_path = "/sys/bus/i2c/devices/0-0057/eeprom"
if os.path.exists(eeprom_path):
self.I2C_BUS_ORDER = 1
return self.I2C_BUS_ORDER
def get_presence(self, port_num):
# Check for invalid port_num
if port_num < self.port_start or port_num > self.port_end:
return False
order = self.update_i2c_order()
if port_num <= 24:
present_path = self.BASE_CPLD2_PATH.format(order)
else:
present_path = self.BASE_CPLD3_PATH.format(order)
present_path = present_path + "module_present_" + str(self._port_to_i2c_mapping[port_num][0])
self.__port_to_is_present = present_path
try:
val_file = open(self.__port_to_is_present)
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
content = val_file.readline().rstrip()
val_file.close()
# content is a string, either "0" or "1"
if content == "1":
return True
return False
def qsfp_sb_remap(self, port_num):
qsfp_start = self.qsfp_port_start
qsfp_index = self._port_to_i2c_mapping[port_num][0] - qsfp_start
qsfp_index = self.qsfp_sb_map[qsfp_index-1]
return qsfp_start+qsfp_index
def get_low_power_mode_cpld(self, port_num):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False
order = self.update_i2c_order()
lp_mode_path = self.BASE_CPLD3_PATH.format(order)
lp_mode_path = lp_mode_path + "module_lp_mode_"
q = self.qsfp_sb_remap(port_num)
lp_mode_path = lp_mode_path + str(q)
try:
val_file = open(lp_mode_path)
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
content = val_file.readline().rstrip()
val_file.close()
# content is a string, either "0" or "1"
if content == "1":
return True
return False
def get_low_power_mode(self, port_num):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False
if not self.get_presence(port_num):
return self.get_low_power_mode_cpld(port_num)
try:
eeprom = None
eeprom = open(self.port_to_eeprom_mapping[port_num], "rb")
eeprom.seek(93)
lpmode = ord(eeprom.read(1))
if not (lpmode & 0x1): # 'Power override' bit is 0
return self.get_low_power_mode_cpld(port_num)
else:
if ((lpmode & 0x2) == 0x2):
return True # Low Power Mode if "Power set" bit is 1
else:
return False # High Power Mode if "Power set" bit is 0
except IOError as err:
print "Error: unable to open file: %s" % str(err)
return False
finally:
if eeprom is not None:
eeprom.close()
time.sleep(0.01)
def set_low_power_mode(self, port_num, lpmode):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False
try:
eeprom = None
if not self.get_presence(port_num):
return False # Port is not present, unable to set the eeprom
# Fill in write buffer
regval = 0x3 if lpmode else 0x1 # 0x3:Low Power Mode, 0x1:High Power Mode
buffer = create_string_buffer(1)
buffer[0] = chr(regval)
# Write to eeprom
eeprom = open(self.port_to_eeprom_mapping[port_num], "r+b")
eeprom.seek(93)
eeprom.write(buffer[0])
return True
except IOError as err:
print "Error: unable to open file: %s" % str(err)
return False
finally:
if eeprom is not None:
eeprom.close()
time.sleep(0.01)
def reset(self, port_num):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False
order = self.update_i2c_order()
lp_mode_path = self.BASE_CPLD3_PATH.format(order)
mod_rst_path = lp_mode_path + "module_reset_"
q = self.qsfp_sb_remap(port_num)
mod_rst_path = mod_rst_path + str(q)
try:
reg_file = open(mod_rst_path, 'r+')
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
#toggle reset
reg_file.seek(0)
reg_file.write('0')
time.sleep(1)
reg_file.seek(0)
reg_file.write('1')
reg_file.close()
return True
def get_transceiver_change_event(self):
"""
TODO: This function need to be implemented
when decide to support monitoring SFP(Xcvrd)
on this platform.
"""
raise NotImplementedError

62
device/accton/x86_64-accton_as7326_56x-r0/plugins/sfputil.py
View File

@ -5,6 +5,8 @@
try:
import time
import string
from ctypes import create_string_buffer
from sonic_sfp.sfputilbase import SfpUtilBase
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
@ -193,11 +195,63 @@ class SfpUtil(SfpUtilBase):
return False
def get_low_power_mode(self, port_num):
raise NotImplementedError
def get_low_power_mode(self, port_num):
# Check for invalid port_num
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False
def set_low_power_mode(self, port_num, lpmode):
raise NotImplementedError
try:
eeprom = None
if not self.get_presence(port_num):
return False
eeprom = open(self.port_to_eeprom_mapping[port_num], "rb")
eeprom.seek(93)
lpmode = ord(eeprom.read(1))
if ((lpmode & 0x3) == 0x1):
return False # High Power Mode if "Power override" bit is 1 and "Power set" bit is 0
else:
return True # Low Power Mode if one of the following conditions is matched:
# 1. Power override" bit is 0
# 2. Power override" bit is 1 and "Power set" bit is 1
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
finally:
if eeprom is not None:
eeprom.close()
time.sleep(0.01)
def set_low_power_mode(self, port_num, lpmode):
# Check for invalid port_num
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False
try:
eeprom = None
if not self.get_presence(port_num):
return False # Port is not present, unable to set the eeprom
# Fill in write buffer
regval = 0x3 if lpmode else 0x1 # 0x3:Low Power Mode, 0x1:High Power Mode
buffer = create_string_buffer(1)
buffer[0] = chr(regval)
# Write to eeprom
eeprom = open(self.port_to_eeprom_mapping[port_num], "r+b")
eeprom.seek(93)
eeprom.write(buffer[0])
return True
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
finally:
if eeprom is not None:
eeprom.close()
time.sleep(0.01)
def reset(self, port_num):
raise NotImplementedError

66
device/accton/x86_64-accton_as7712_32x-r0/plugins/sfputil.py
View File

@ -2,6 +2,8 @@
try:
import time
import string
from ctypes import create_string_buffer
from sonic_sfp.sfputilbase import SfpUtilBase
except ImportError, e:
raise ImportError (str(e) + "- required module not found")
@ -81,12 +83,6 @@ class SfpUtil(SfpUtilBase):
reg_file.write('0')
reg_file.close()
return True
def set_low_power_mode(self, port_nuM, lpmode):
raise NotImplementedError
def get_low_power_mode(self, port_num):
raise NotImplementedError
def get_presence(self, port_num):
# Check for invalid port_num
@ -132,3 +128,61 @@ class SfpUtil(SfpUtilBase):
on this platform.
"""
raise NotImplementedError
def get_low_power_mode(self, port_num):
# Check for invalid port_num
if port_num < self._port_start or port_num > self._port_end:
return False
try:
eeprom = None
if not self.get_presence(port_num):
return False
eeprom = open(self.port_to_eeprom_mapping[port_num], "rb")
eeprom.seek(93)
lpmode = ord(eeprom.read(1))
if ((lpmode & 0x3) == 0x3):
return True # Low Power Mode if "Power override" bit is 1 and "Power set" bit is 1
else:
return False # High Power Mode if one of the following conditions is matched:
# 1. "Power override" bit is 0
# 2. "Power override" bit is 1 and "Power set" bit is 0
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
finally:
if eeprom is not None:
eeprom.close()
time.sleep(0.01)
def set_low_power_mode(self, port_num, lpmode):
# Check for invalid port_num
if port_num < self._port_start or port_num > self._port_end:
return False
try:
eeprom = None
if not self.get_presence(port_num):
return False # Port is not present, unable to set the eeprom
# Fill in write buffer
regval = 0x3 if lpmode else 0x1 # 0x3:Low Power Mode, 0x1:High Power Mode
buffer = create_string_buffer(1)
buffer[0] = chr(regval)
# Write to eeprom
eeprom = open(self.port_to_eeprom_mapping[port_num], "r+b")
eeprom.seek(93)
eeprom.write(buffer[0])
return True
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
finally:
if eeprom is not None:
eeprom.close()
time.sleep(0.01)

87
device/arista/x86_64-arista_7050_qx32/platform_reboot
View File

@ -1,87 +0,0 @@
#!/usr/bin/env python
# Copyright (c) 2018 Arista Networks, Inc. All rights reserved.
# Arista Networks, Inc. Confidential and Proprietary.
# Reboot script for 7050QX-32
from __future__ import print_function
import sys
import mmap, os
import subprocess
from struct import pack, unpack
class MmapResource( object ):
"""Resource implementation for a directly-mapped memory region."""
def __init__( self, path ):
try:
fd = os.open( path, os.O_RDWR )
except EnvironmentError:
print( "FAIL can not open scd memory-map resource file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
try:
size = os.fstat( fd ).st_size
except EnvironmentError:
print( "FAIL can not fstat scd memory-map resource file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
try:
self.mmap_ = mmap.mmap( fd, size, mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE )
except EnvironmentError:
print( "FAIL can not map scd memory-map file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
finally:
try:
# Note that closing the file descriptor has no effect on the memory map
os.close( fd )
except EnvironmentError:
print( "FAIL failed to close scd memory-map file" )
sys.exit( 1 )
def read32( self, addr ):
return unpack( '<L', self.mmap_[ addr : addr + 4 ] )[ 0 ]
def write32( self, addr, value ):
self.mmap_[ addr: addr + 4 ] = pack( '<L', value )
def scdRegTest( scd, offset, val1, count ):
scd.write32( offset, val1 )
val2 = scd.read32( offset )
if val1 != val2:
print( "FAIL: scd write 0x%08x but read back 0x%08x in iter %d" %
( val1, val2, count ) )
sys.exit( 17 )
def scdScrRegTest( scd ):
scrOffset = 0x0130
for i in range( 0, 3 ):
scdRegTest( scd, scrOffset, 0xdeadbeef, i )
scdRegTest( scd, scrOffset, 0xa5a5a5a5, i )
scdRegTest( scd, scrOffset, 0x00000000, i )
def reboot( scd ):
# reboot the system by writing to register 0x7000
print( "Rebooting" )
scd.write32( 0x7000, 0xDEAD )
print( "REBOOTED" )
def main():
busName = "/sys/bus/pci/devices/0000:04:00.0/resource0"
subprocess.call( [ 'modprobe', 'scd' ] )
scd = MmapResource( busName )
#
# verify that we can read/write scd scratch register
#
scdScrRegTest( scd )
# reboot the system
reboot( scd )
if __name__ == "__main__":
main()

1
device/arista/x86_64-arista_7050_qx32/platform_reboot Symbolic link
View File

@ -0,0 +1 @@
../x86_64-arista_common/platform_reboot

87
device/arista/x86_64-arista_7050_qx32s/platform_reboot
View File

@ -1,87 +0,0 @@
#!/usr/bin/env python
# Copyright (c) 2018 Arista Networks, Inc. All rights reserved.
# Arista Networks, Inc. Confidential and Proprietary.
# Reboot script for 7050QX-32S
from __future__ import print_function
import sys
import mmap, os
import subprocess
from struct import pack, unpack
class MmapResource( object ):
"""Resource implementation for a directly-mapped memory region."""
def __init__( self, path ):
try:
fd = os.open( path, os.O_RDWR )
except EnvironmentError:
print( "FAIL can not open scd memory-map resource file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
try:
size = os.fstat( fd ).st_size
except EnvironmentError:
print( "FAIL can not fstat scd memory-map resource file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
try:
self.mmap_ = mmap.mmap( fd, size, mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE )
except EnvironmentError:
print( "FAIL can not map scd memory-map file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
finally:
try:
# Note that closing the file descriptor has no effect on the memory map
os.close( fd )
except EnvironmentError:
print( "FAIL failed to close scd memory-map file" )
sys.exit( 1 )
def read32( self, addr ):
return unpack( '<L', self.mmap_[ addr : addr + 4 ] )[ 0 ]
def write32( self, addr, value ):
self.mmap_[ addr: addr + 4 ] = pack( '<L', value )
def scdRegTest( scd, offset, val1, count ):
scd.write32( offset, val1 )
val2 = scd.read32( offset )
if val1 != val2:
print( "FAIL: scd write 0x%08x but read back 0x%08x in iter %d" %
( val1, val2, count ) )
sys.exit( 17 )
def scdScrRegTest( scd ):
scrOffset = 0x0130
for i in range( 0, 3 ):
scdRegTest( scd, scrOffset, 0xdeadbeef, i )
scdRegTest( scd, scrOffset, 0xa5a5a5a5, i )
scdRegTest( scd, scrOffset, 0x00000000, i )
def reboot( scd ):
# reboot the system by writing to register 0x7000
print( "Rebooting" )
scd.write32( 0x7000, 0xDEAD )
print( "REBOOTED" )
def main():
busName = "/sys/bus/pci/devices/0000:02:00.0/resource0"
subprocess.call( [ 'modprobe', 'scd' ] )
scd = MmapResource( busName )
#
# verify that we can read/write scd scratch register
#
scdScrRegTest( scd )
# reboot the system
reboot( scd )
if __name__ == "__main__":
main()

1
device/arista/x86_64-arista_7050_qx32s/platform_reboot Symbolic link
View File

@ -0,0 +1 @@
../x86_64-arista_common/platform_reboot

18
device/arista/x86_64-arista_7060_cx32s/platform_reboot
View File

@ -1,18 +0,0 @@
#!/usr/bin/env python
# Copyright (c) 2018 Arista Networks, Inc. All rights reserved.
# Arista Networks, Inc. Confidential and Proprietary.
# Reboot script for 7060CX-32
from __future__ import print_function
import smbus
def main():
print( "Rebooting" )
bus = smbus.SMBus( 1 )
bus.write_byte_data( 0x23, 0x04, 0xde )
print( "REBOOTED" )
if __name__ == "__main__":
main()

1
device/arista/x86_64-arista_7060_cx32s/platform_reboot Symbolic link
View File

@ -0,0 +1 @@
../x86_64-arista_common/platform_reboot

11
device/arista/x86_64-arista_7060px4_32/platform_reboot
View File

@ -1,11 +0,0 @@
#!/usr/bin/env python
from arista import platforms
from arista.utils.sonic_reboot import reboot
def main():
# reboot the system
reboot()
if __name__ == "__main__":
main()

1
device/arista/x86_64-arista_7060px4_32/platform_reboot Symbolic link
View File

@ -0,0 +1 @@
../x86_64-arista_common/platform_reboot

3
device/arista/x86_64-arista_7170_64c/Arista-7170-64C/buffers.json.j2 Normal file
View File

@ -0,0 +1,3 @@
{%- set default_topo = 't0' %}
{%- include 'buffers_config.j2' %}

46
device/arista/x86_64-arista_7170_64c/Arista-7170-64C/buffers_defaults_t0.j2 Normal file
View File

@ -0,0 +1,46 @@
{%- set default_cable = '5m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "33329088",
"type": "ingress",
"mode": "dynamic",
"xoff": "7827456"
},
"egress_lossy_pool": {
"size": "26663272",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "42349632",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"size":"0",
"static_th":"11075584"
},
"egress_lossless_profile": {
"pool":"[BUFFER_POOL|egress_lossless_pool]",
"size":"0",
"static_th":"10587408"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"1664",
"dynamic_th":"-1"
}
},
{%- endmacro %}

1
device/arista/x86_64-arista_7170_64c/Arista-7170-64C/qos.json.j2 Normal file
View File

@ -0,0 +1 @@
{%- include 'qos_config.j2' %}

3
device/arista/x86_64-arista_7170_64c/Arista-7170-64C/switch-sai.conf
View File

@ -26,7 +26,8 @@
"tofino-bin": "share/tofinopd/switch/tofino.bin",
"switchapi": "lib/libswitchapi.so",
"switchsai": "lib/libswitchsai.so",
"switchapi_port_add": false
"switchapi_port_add": false,
"non_default_port_ppgs": 5
}
]
}

3
device/arista/x86_64-arista_7170_64c/Arista-7170-Q59S20/buffers.json.j2 Normal file
View File

@ -0,0 +1,3 @@
{%- set default_topo = 't0' %}
{%- include 'buffers_config.j2' %}

58
device/arista/x86_64-arista_7170_64c/Arista-7170-Q59S20/buffers_defaults_t0.j2 Normal file
View File

@ -0,0 +1,58 @@
{%- set default_cable = '5m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,20) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- for port_idx in range(80,88) %}
{%- if PORT_ALL.append("Ethernet%d" % port_idx) %}{%- endif %}
{%- endfor %}
{%- for port_idx in range(22,32) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- for port_idx in range(128,140) %}
{%- if PORT_ALL.append("Ethernet%d" % port_idx) %}{%- endif %}
{%- endfor %}
{%- for port_idx in range(35,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "33329088",
"type": "ingress",
"mode": "dynamic",
"xoff": "7827456"
},
"egress_lossy_pool": {
"size": "26663272",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "42349632",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"size":"0",
"static_th":"11075584"
},
"egress_lossless_profile": {
"pool":"[BUFFER_POOL|egress_lossless_pool]",
"size":"0",
"static_th":"10587408"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"1664",
"dynamic_th":"-1"
}
},
{%- endmacro %}

1
device/arista/x86_64-arista_7170_64c/Arista-7170-Q59S20/qos.json.j2 Normal file
View File

@ -0,0 +1 @@
{%- include 'qos_config.j2' %}

3
device/arista/x86_64-arista_7170_64c/Arista-7170-Q59S20/switch-sai.conf
View File

@ -26,7 +26,8 @@
"tofino-bin": "share/tofinopd/switch/tofino.bin",
"switchapi": "lib/libswitchapi.so",
"switchsai": "lib/libswitchsai.so",
"switchapi_port_add": false
"switchapi_port_add": false,
"non_default_port_ppgs": 5
}
]
}

11
device/arista/x86_64-arista_7170_64c/platform_reboot
View File

@ -1,11 +0,0 @@
#!/usr/bin/env python
import arista.platforms
from arista.utils.sonic_reboot import reboot
def main():
# reboot the system
reboot()
if __name__ == "__main__":
main()

1
device/arista/x86_64-arista_7170_64c/platform_reboot Symbolic link
View File

@ -0,0 +1 @@
../x86_64-arista_common/platform_reboot

87
device/arista/x86_64-arista_7260cx3_64/platform_reboot
View File

@ -1,87 +0,0 @@
#!/usr/bin/env python
# Copyright (c) 2018 Arista Networks, Inc. All rights reserved.
# Arista Networks, Inc. Confidential and Proprietary.
# Reboot script for 7260CX3
from __future__ import print_function
import sys
import mmap, os
import subprocess
from struct import pack, unpack
class MmapResource( object ):
"""Resource implementation for a directly-mapped memory region."""
def __init__( self, path ):
try:
fd = os.open( path, os.O_RDWR )
except EnvironmentError:
print( "FAIL can not open scd memory-map resource file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
try:
size = os.fstat( fd ).st_size
except EnvironmentError:
print( "FAIL can not fstat scd memory-map resource file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
try:
self.mmap_ = mmap.mmap( fd, size, mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE )
except EnvironmentError:
print( "FAIL can not map scd memory-map file" )
print( "FAIL are you running on the proper platform?" )
sys.exit( 1 )
finally:
try:
# Note that closing the file descriptor has no effect on the memory map
os.close( fd )
except EnvironmentError:
print( "FAIL failed to close scd memory-map file" )
sys.exit( 1 )
def read32( self, addr ):
return unpack( '<L', self.mmap_[ addr : addr + 4 ] )[ 0 ]
def write32( self, addr, value ):
self.mmap_[ addr: addr + 4 ] = pack( '<L', value )
def scdRegTest( scd, offset, val1, count ):
scd.write32( offset, val1 )
val2 = scd.read32( offset )
if val1 != val2:
print( "FAIL: scd write 0x%08x but read back 0x%08x in iter %d" %
( val1, val2, count ) )
sys.exit( 17 )
def scdScrRegTest( scd ):
scrOffset = 0x0130
for i in range( 0, 3 ):
scdRegTest( scd, scrOffset, 0xdeadbeef, i )
scdRegTest( scd, scrOffset, 0xa5a5a5a5, i )
scdRegTest( scd, scrOffset, 0x00000000, i )
def reboot( scd ):
# reboot the system by writing to register 0x7000
print( "Rebooting" )
scd.write32( 0x7000, 0xDEAD )
print( "REBOOTED" )
def main():
busName = "/sys/bus/pci/devices/0000:ff:0b.3/resource0"
subprocess.call( [ 'modprobe', 'scd' ] )
scd = MmapResource( busName )
#
# verify that we can read/write scd scratch register
#
scdScrRegTest( scd )
# reboot the system
reboot( scd )
if __name__ == "__main__":
main()

1
device/arista/x86_64-arista_7260cx3_64/platform_reboot Symbolic link
View File

@ -0,0 +1 @@
../x86_64-arista_common/platform_reboot

1
device/arista/x86_64-arista_7280cr3_32d4 Symbolic link
View File

@ -0,0 +1 @@
x86_64-arista_7280cr3_32p4

1
device/arista/x86_64-arista_7280cr3_32p4/Arista-7280CR3-C32D4 Symbolic link
View File

@ -0,0 +1 @@
Arista-7280CR3-C32P4

37
device/arista/x86_64-arista_7280cr3_32p4/Arista-7280CR3-C32P4/port_config.ini Normal file
View File

@ -0,0 +1,37 @@
# name lanes alias index speed
Ethernet0 1,2 Ethernet1/1 1 100000
Ethernet4 3,4 Ethernet2/1 2 100000
Ethernet8 5,6 Ethernet3/1 3 100000
Ethernet12 7,8 Ethernet4/1 4 100000
Ethernet16 9,10 Ethernet5/1 5 100000
Ethernet20 11,12 Ethernet6/1 6 100000
Ethernet24 13,14 Ethernet7/1 7 100000
Ethernet28 15,16 Ethernet8/1 8 100000
Ethernet32 17,18 Ethernet9/1 9 100000
Ethernet36 19,20 Ethernet10/1 10 100000
Ethernet40 21,22 Ethernet11/1 11 100000
Ethernet44 23,24 Ethernet12/1 12 100000
Ethernet48 25,26 Ethernet13/1 13 100000
Ethernet52 27,28 Ethernet14/1 14 100000
Ethernet56 29,30 Ethernet15/1 15 100000
Ethernet60 31,32 Ethernet16/1 16 100000
Ethernet64 73,74 Ethernet17/1 17 100000
Ethernet68 75,76 Ethernet18/1 18 100000
Ethernet72 77,78 Ethernet19/1 19 100000
Ethernet76 79,80 Ethernet20/1 20 100000
Ethernet80 65,66 Ethernet21/1 21 100000
Ethernet84 67,68 Ethernet22/1 22 100000
Ethernet88 69,70 Ethernet23/1 23 100000
Ethernet92 71,72 Ethernet24/1 24 100000
Ethernet96 57,58 Ethernet25/1 25 100000
Ethernet100 59,60 Ethernet26/1 26 100000
Ethernet104 61,62 Ethernet27/1 27 100000
Ethernet108 63,64 Ethernet28/1 28 100000
Ethernet112 49,50 Ethernet29/1 29 100000
Ethernet116 51,52 Ethernet30/1 30 100000
Ethernet120 53,54 Ethernet31/1 31 100000
Ethernet124 55,56 Ethernet32/1 32 100000
Ethernet128 33,34,35,36,37,38,39,40 Ethernet33/1 33 400000
Ethernet132 41,42,43,44,45,46,47,48 Ethernet34/1 34 400000
Ethernet136 89,90,91,92,93,94,95,96 Ethernet35/1 35 400000
Ethernet140 81,82,83,84,85,86,87,88 Ethernet36/1 36 400000

1
device/arista/x86_64-arista_7280cr3_32p4/default_sku Normal file
View File

@ -0,0 +1 @@
Arista-7280CR3-C32P4 t1

10
device/arista/x86_64-arista_7280cr3_32p4/fancontrol Normal file
View File

@ -0,0 +1,10 @@
INTERVAL=5
DEVPATH=hwmon2=devices/pci0000:00/0000:00:09.0 hwmon4=devices/pci0000:00/0000:00:09.0/i2c-56/56-004c
DEVNAME=hwmon2=scd_fan_p3 hwmon4=max6658
FCTEMPS=hwmon2/pwm6=hwmon4/temp1_input hwmon2/pwm5=hwmon4/temp1_input hwmon2/pwm4=hwmon4/temp1_input hwmon2/pwm4=hwmon4/temp1_input hwmon2/pwm2=hwmon4/temp1_input hwmon2/pwm1=hwmon4/temp1_input
FCFANS=hwmon2/pwm6=hwmon2/fan6_input hwmon2/pwm5=hwmon2/fan5_input hwmon2/pwm4=hwmon2/fan4_input hwmon2/pwm3=hwmon2/fan3_input hwmon2/pwm2=hwmon2/fan2_input hwmon2/pwm1=hwmon2/fan1_input
MINTEMP=hwmon2/pwm6=50 hwmon2/pwm5=50 hwmon2/pwm4=50 hwmon2/pwm3=50 hwmon2/pwm2=50 hwmon2/pwm1=50
MINPWM=hwmon2/pwm6=128 hwmon2/pwm5=128 hwmon2/pwm4=128 hwmon2/pwm3=128 hwmon2/pwm2=128 hwmon2/pwm1=128
MAXTEMP=hwmon2/pwm6=60 hwmon2/pwm5=60 hwmon2/pwm4=60 hwmon2/pwm3=60 hwmon2/pwm2=60 hwmon2/pwm1=60
MINSTART=hwmon2/pwm6=128 hwmon2/pwm5=128 hwmon2/pwm4=128 hwmon2/pwm3=128 hwmon2/pwm2=128 hwmon2/pwm1=128
MINSTOP=hwmon2/pwm6=128 hwmon2/pwm5=128 hwmon2/pwm4=128 hwmon2/pwm3=128 hwmon2/pwm2=128 hwmon2/pwm1=128

1
device/arista/x86_64-arista_7280cr3_32p4/platform_reboot Symbolic link
View File

@ -0,0 +1 @@
../x86_64-arista_common/platform_reboot

8
device/arista/x86_64-arista_7280cr3_32p4/plugins/eeprom.py Normal file
View File

@ -0,0 +1,8 @@
#!/usr/bin/env python
try:
import arista.utils.sonic_eeprom as arista_eeprom
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
board = arista_eeprom.getTlvInfoDecoder()

8
device/arista/x86_64-arista_7280cr3_32p4/plugins/led_control.py Normal file
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#!/usr/bin/env python
try:
import arista.utils.sonic_leds as arista_leds
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
LedControl = arista_leds.getLedControl()

8
device/arista/x86_64-arista_7280cr3_32p4/plugins/psuutil.py Normal file
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# psuutil.py
try:
import arista.utils.sonic_psu as arista_psuutil
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
PsuUtil = arista_psuutil.getPsuUtil()

8
device/arista/x86_64-arista_7280cr3_32p4/plugins/sfputil.py Normal file
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#!/usr/bin/env python
try:
import arista.utils.sonic_sfputil as arista_sfputil
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
SfpUtil = arista_sfputil.getSfpUtil()

66
device/arista/x86_64-arista_7280cr3_32p4/sensors.conf Normal file
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# libsensors configuration file for DCS-7280CR3-32P4
# ------------------------------------------------#
bus "i2c-8" "SCD 0000:02:00.0 SMBus master 0 bus 0"
bus "i2c-14" "SCD 0000:02:00.0 SMBus master 0 bus 6"
bus "i2c-15" "SCD 0000:02:00.0 SMBus master 0 bus 7"
bus "i2c-56" "SCD 0000:00:09.0 SMBus master 0 bus 0"
chip "tmp468-i2c-8-48"
label temp1 "Board sensor"
label temp2 "Front air (inlet) sensor"
label temp3 "Rear air sensor"
label temp4 "Front left sensor"
label temp5 "Front right sensor"
label temp6 "Rear left sensor"
label temp7 "Rear right sensor"
label temp8 "Asic temp sensor 1"
label temp9 "Asic temp sensor 2"
set temp1_max 75
set temp1_crit 80
set temp2_max 65
set temp2_crit 75
set temp3_max 65
set temp3_crit 75
ignore temp4
ignore temp5
ignore temp6
ignore temp7
set temp8_max 100
set temp8_crit 110
set temp9_max 100
set temp9_crit 110
chip "pmbus-i2c-14-58"
label temp1 "Power supply 1 hotspot sensor"
label temp2 "Power supply 1 inlet temp sensor"
label temp3 "Power supply 1 exhaust temp sensor"
# setting maximum and critical thresholds is not supported for this psu
# fault and warning limits defined internally by hardware
ignore fan2
ignore fan3
ignore fan4
chip "pmbus-i2c-15-58"
label temp1 "Power supply 2 hotspot sensor"
label temp2 "Power supply 2 inlet temp sensor"
label temp3 "Power supply 2 exhaust temp sensor"
# setting maximum and critical thresholds is not supported for this psu
# fault and warning limits defined internally by hardware
ignore fan2
ignore fan3
ignore fan4
chip "max6658-i2c-56-4c"
label temp1 "Back panel temp sensor 1"
label temp2 "Back panel temp sensor 2"
set temp1_max 75
set temp1_crit 85
set temp2_max 75
set temp2_crit 85

11
device/arista/x86_64-arista_common/platform_reboot Executable file
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#!/usr/bin/env python
import arista.platforms
from arista.utils.sonic_reboot import reboot
def main():
# reboot the system
reboot()
if __name__ == "__main__":
main()

0
device/celestica/x86_64-cel_e1031-r0/sonic_platform/__init__.py Normal file
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108
device/celestica/x86_64-cel_e1031-r0/sonic_platform/chassis.py Normal file
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#!/usr/bin/env python
#############################################################################
# Celestica
#
# Module contains an implementation of SONiC Platform Base API and
# provides the Chassis information which are available in the platform
#
#############################################################################
import sys
import re
import os
import subprocess
import json
try:
from sonic_platform_base.chassis_base import ChassisBase
from sonic_platform.fan import Fan
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
MMC_CPLD_ADDR = '0x100'
BIOS_VERSION_PATH = "/sys/class/dmi/id/bios_version"
CONFIG_DB_PATH = "/etc/sonic/config_db.json"
SMC_CPLD_PATH = "/sys/devices/platform/e1031.smc/version"
MMC_CPLD_PATH = "/sys/devices/platform/e1031.smc/getreg"
NUM_FAN = 3
class Chassis(ChassisBase):
"""Platform-specific Chassis class"""
def __init__(self):
self.config_data = {}
for index in range(0, NUM_FAN):
fan = Fan(index)
self._fan_list.append(fan)
ChassisBase.__init__(self)
def __get_register_value(self, path, register):
cmd = "echo {1} > {0}; cat {0}".format(path, register)
p = subprocess.Popen(
cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
raw_data, err = p.communicate()
if err is not '':
return 'None'
else:
return raw_data.strip()
def __read_config_db(self):
try:
with open(CONFIG_DB_PATH, 'r') as fd:
data = json.load(fd)
return data
except IOError:
raise IOError("Unable to open config_db file !")
def get_base_mac(self):
"""
Retrieves the base MAC address for the chassis
Returns:
A string containing the MAC address in the format
'XX:XX:XX:XX:XX:XX'
"""
try:
self.config_data = self.__read_config_db()
base_mac = self.config_data["DEVICE_METADATA"]["localhost"]["mac"]
return str(base_mac)
except KeyError:
raise KeyError("Base MAC not found")
def get_component_versions(self):
"""
Retrieves platform-specific hardware/firmware versions for chassis
componenets such as BIOS, CPLD, FPGA, etc.
Returns:
A string containing platform-specific component versions
"""
component_versions = dict()
# Get BIOS version
try:
with open(BIOS_VERSION_PATH, 'r') as fd:
bios_version = fd.read()
except IOError:
raise IOError("Unable to open version file !")
# Get CPLD version
cpld_version = dict()
with open(SMC_CPLD_PATH, 'r') as fd:
smc_cpld_version = fd.read()
smc_cpld_version = 'None' if smc_cpld_version is 'None' else "{}.{}".format(
int(smc_cpld_version[2], 16), int(smc_cpld_version[3], 16))
mmc_cpld_version = self.__get_register_value(
MMC_CPLD_PATH, MMC_CPLD_ADDR)
mmc_cpld_version = 'None' if mmc_cpld_version is 'None' else "{}.{}".format(
int(mmc_cpld_version[2], 16), int(mmc_cpld_version[3], 16))
cpld_version["SMC"] = smc_cpld_version
cpld_version["MMC"] = mmc_cpld_version
component_versions["CPLD"] = cpld_version
component_versions["BIOS"] = bios_version.strip()
return str(component_versions)

183
device/celestica/x86_64-cel_e1031-r0/sonic_platform/fan.py Normal file
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#!/usr/bin/env python
#############################################################################
# Celestica
#
# Module contains an implementation of SONiC Platform Base API and
# provides the fan status which are available in the platform
#
#############################################################################
import json
import math
import os.path
try:
from sonic_platform_base.fan_base import FanBase
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
EMC2305_FAN_PATH = "/sys/bus/i2c/drivers/emc2305/"
FAN_PATH = "/sys/devices/platform/e1031.smc/"
SYS_GPIO_DIR = "/sys/class/gpio"
EMC2305_MAX_PWM = 255
EMC2305_FAN_PWM = "pwm{}"
EMC2305_FAN_TARGET = "fan{}_target"
EMC2305_FAN_INPUT = "pwm{}"
class Fan(FanBase):
"""Platform-specific Fan class"""
def __init__(self, fan_index):
self.index = fan_index
self.config_data = {}
self.fan_speed = 0
# e1031 fan attributes
# Single emc2305 chip located at i2c-23-4d
# to control a fan module
self.e1031_emc2305_chip = [
{
'device': "23-004d",
'index_map': [1, 2, 4]
}
]
# TODO: Add fan presence status in sysfs
self.fan_e1031_presence = "fan{}_prs"
self.fan_e1031_direction = "fan{}_dir"
self.fan_e1031_led = "fan{}_led"
self.fan_e1031_led_col_map = {
self.STATUS_LED_COLOR_GREEN: "green",
self.STATUS_LED_COLOR_RED: "amber",
self.STATUS_LED_COLOR_OFF: "off"
}
FanBase.__init__(self)
def get_direction(self):
direction = self.FAN_DIRECTION_INTAKE
try:
fan_direction_file = (FAN_PATH +
self.fan_e1031_direction.format(self.index+1))
with open(fan_direction_file, 'r') as file:
raw = file.read().strip('\r\n')
if str(raw).upper() == "F2B":
direction = self.FAN_DIRECTION_INTAKE
else:
direction = self.FAN_DIRECTION_EXHAUST
except IOError:
return False
return direction
def get_speed(self):
"""
E1031 platform specific data:
speed = pwm_in/255*100
"""
# TODO: Seperate PSU's fan and main fan class
if self.fan_speed != 0:
return self.fan_speed
else:
speed = 0
pwm = []
emc2305_chips = self.e1031_emc2305_chip
for chip in emc2305_chips:
device = chip['device']
fan_index = chip['index_map']
sysfs_path = "%s%s/%s" % (
EMC2305_FAN_PATH, device, EMC2305_FAN_INPUT)
sysfs_path = sysfs_path.format(fan_index[self.index])
try:
with open(sysfs_path, 'r') as file:
raw = file.read().strip('\r\n')
pwm.append(int(raw, 10))
except IOError:
raise IOError("Unable to open " + sysfs_path)
speed = math.ceil(
float(pwm[0]) * 100 / EMC2305_MAX_PWM)
return int(speed)
def get_target_speed(self):
"""
E1031 platform specific data:
speed_pc = pwm_target/255*100
0 : when PWM mode is use
pwm : when pwm mode is not use
"""
target = 0
pwm = []
emc2305_chips = self.e1031_emc2305_chip
for chip in emc2305_chips:
device = chip['device']
fan_index = chip['index_map']
sysfs_path = "%s%s/%s" % (
EMC2305_FAN_PATH, device, EMC2305_FAN_TARGET)
sysfs_path = sysfs_path.format(fan_index[self.index])
try:
with open(sysfs_path, 'r') as file:
raw = file.read().strip('\r\n')
pwm.append(int(raw, 10))
except IOError:
raise IOError("Unable to open " + sysfs_path)
target = pwm[0] * 100 / EMC2305_MAX_PWM
return target
def get_speed_tolerance(self):
"""
Retrieves the speed tolerance of the fan
Returns:
An integer, the percentage of variance from target speed which is
considered tolerable
"""
return 10
def set_speed(self, speed):
"""
Depends on pwm or target mode is selected:
1) pwm = speed_pc * 255 <-- Currently use this mode.
2) target_pwm = speed_pc * 100 / 255
2.1) set pwm{}_enable to 3
"""
pwm = speed * 255 / 100
emc2305_chips = self.e1031_emc2305_chip
for chip in emc2305_chips:
device = chip['device']
fan_index = chip['index_map']
sysfs_path = "%s%s/%s" % (
EMC2305_FAN_PATH, device, EMC2305_FAN_PWM)
sysfs_path = sysfs_path.format(fan_index[self.index])
try:
with open(sysfs_path, 'w') as file:
file.write(str(int(pwm)))
except IOError:
return False
return True
def set_status_led(self, color):
try:
fan_led_file = (FAN_PATH +
self.fan_e1031_led.format(self.index+1))
with open(fan_led_file, 'r') as file:
file.write(self.fan_e1031_led_col_map[color])
except IOError:
return False
return True

23
device/celestica/x86_64-cel_e1031-r0/sonic_platform/platform.py Normal file
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#!/usr/bin/env python
#############################################################################
# Celestica
#
# Module contains an implementation of SONiC Platform Base API and
# provides the platform information
#
#############################################################################
try:
from sonic_platform_base.platform_base import PlatformBase
from sonic_platform.chassis import Chassis
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
class Platform(PlatformBase):
"""Platform-specific Platform class"""
def __init__(self):
PlatformBase.__init__(self)
self._chassis = Chassis()

0
device/celestica/x86_64-cel_seastone-r0/sonic_platform/__init__.py Normal file
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109
device/celestica/x86_64-cel_seastone-r0/sonic_platform/chassis.py Normal file
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#!/usr/bin/env python
#############################################################################
# Celestica
#
# Module contains an implementation of SONiC Platform Base API and
# provides the Chassis information which are available in the platform
#
#############################################################################
import sys
import re
import os
import subprocess
import json
try:
from sonic_platform_base.chassis_base import ChassisBase
from sonic_platform.fan import Fan
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
BIOS_VERSION_PATH = "/sys/class/dmi/id/bios_version"
GETREG_PATH = "/sys/devices/platform/dx010_cpld/getreg"
CONFIG_DB_PATH = "/etc/sonic/config_db.json"
NUM_FAN = 5
CPLD_ADDR_MAPPING = {
"CPLD1": "0x100",
"CPLD2": "0x200",
"CPLD3": "0x280",
"CPLD4": "0x300",
"CPLD5": "0x380"
}
class Chassis(ChassisBase):
"""Platform-specific Chassis class"""
def __init__(self):
self.config_data = {}
for index in range(0, NUM_FAN):
fan = Fan(index)
self._fan_list.append(fan)
ChassisBase.__init__(self)
def __get_register_value(self, path, register):
cmd = "echo {1} > {0}; cat {0}".format(path, register)
p = subprocess.Popen(
cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
raw_data, err = p.communicate()
if err is not '':
return 'None'
else:
return raw_data.strip()
def __read_config_db(self):
try:
with open(CONFIG_DB_PATH, 'r') as fd:
data = json.load(fd)
return data
except IOError:
raise IOError("Unable to open config_db file !")
def get_base_mac(self):
"""
Retrieves the base MAC address for the chassis
Returns:
A string containing the MAC address in the format
'XX:XX:XX:XX:XX:XX'
"""
try:
self.config_data = self.__read_config_db()
base_mac = self.config_data["DEVICE_METADATA"]["localhost"]["mac"]
return str(base_mac)
except KeyError:
raise KeyError("Base MAC not found")
def get_component_versions(self):
"""
Retrieves platform-specific hardware/firmware versions for chassis
componenets such as BIOS, CPLD, FPGA, etc.
Returns:
A string containing platform-specific component versions
"""
component_versions = dict()
# Get BIOS version
try:
with open(BIOS_VERSION_PATH, 'r') as fd:
bios_version = fd.read()
except IOError:
raise IOError("Unable to open version file !")
# Get CPLD version
cpld_version = dict()
for cpld_name in CPLD_ADDR_MAPPING:
try:
cpld_addr = CPLD_ADDR_MAPPING[cpld_name]
cpld_version_raw = self.__get_register_value(
GETREG_PATH, cpld_addr)
cpld_version_str = "{}.{}".format(int(cpld_version_raw[2], 16), int(
cpld_version_raw[3], 16)) if cpld_version_raw is not None else 'None'
cpld_version[cpld_name] = cpld_version_str
except Exception, e:
cpld_version[cpld_name] = 'None'
component_versions["CPLD"] = cpld_version
component_versions["BIOS"] = bios_version.strip()
return str(component_versions)

228
device/celestica/x86_64-cel_seastone-r0/sonic_platform/fan.py Normal file
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#!/usr/bin/env python
#############################################################################
# Celestica
#
# Module contains an implementation of SONiC Platform Base API and
# provides the fan status which are available in the platform
#
#############################################################################
import json
import math
import os.path
try:
from sonic_platform_base.fan_base import FanBase
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
CONFIG_DB_PATH = "/etc/sonic/config_db.json"
EMC2305_PATH = "/sys/bus/i2c/drivers/emc2305/"
SYS_GPIO_DIR = "/sys/class/gpio"
EMC2305_MAX_PWM = 255
EMC2305_FAN_PWM = "pwm{}"
EMC2305_FAN_TARGET = "fan{}_target"
EMC2305_FAN_INPUT = "pwm{}"
class Fan(FanBase):
"""Platform-specific Fan class"""
def __init__(self, fan_index):
self.index = fan_index
self.config_data = {}
self.fan_speed = 0
FanBase.__init__(self)
# dx010 fan attributes
# Two EMC2305s located at i2c-13-4d and i2c-13-2e
# to control a dual-fan module.
self.dx010_emc2305_chip = [
{
'device': "13-002e",
'index_map': [2, 1, 4, 5, 3]
},
{
'device': "13-004d",
'index_map': [2, 4, 5, 3, 1]
}
]
self.dx010_fan_gpio = [
{'base': self.get_gpio_base()},
{'prs': 10, 'dir': 15, 'color': {'red': 31, 'green': 32}},
{'prs': 11, 'dir': 16, 'color': {'red': 29, 'green': 30}},
{'prs': 12, 'dir': 17, 'color': {'red': 35, 'green': 36}},
{'prs': 13, 'dir': 18, 'color': {'red': 37, 'green': 38}},
{'prs': 14, 'dir': 19, 'color': {'red': 33, 'green': 34}},
]
def get_gpio_base(self):
for r in os.listdir(SYS_GPIO_DIR):
if "gpiochip" in r:
return int(r[8:], 10)
return 216 # Reserve
def get_gpio_value(self, pinnum):
gpio_base = self.dx010_fan_gpio[0]['base']
gpio_dir = SYS_GPIO_DIR + '/gpio' + str(gpio_base+pinnum)
gpio_file = gpio_dir + "/value"
try:
with open(gpio_file, 'r') as fd:
retval = fd.read()
except IOError:
raise IOError("Unable to open " + gpio_file + "file !")
retval = retval.rstrip('\r\n')
return retval
def set_gpio_value(self, pinnum, value=0):
gpio_base = self.dx010_fan_gpio[0]['base']
gpio_dir = SYS_GPIO_DIR + '/gpio' + str(gpio_base+pinnum)
gpio_file = gpio_dir + "/value"
try:
with open(gpio_file, 'w') as fd:
retval = fd.write(str(value))
except IOError:
raise IOError("Unable to open " + gpio_file + "file !")
def get_direction(self):
direction = self.FAN_DIRECTION_INTAKE
raw = self.get_gpio_value(self.dx010_fan_gpio[self.index+1]['dir'])
if int(raw, 10) == 0:
direction = self.FAN_DIRECTION_INTAKE
else:
direction = self.FAN_DIRECTION_EXHAUST
return direction
def get_speed(self):
"""
DX010 platform specific data:
speed = pwm_in/255*100
"""
# TODO: Seperate PSU's fan and main fan class
if self.fan_speed != 0:
return self.fan_speed
else:
speed = 0
pwm = []
emc2305_chips = self.dx010_emc2305_chip
for chip in emc2305_chips:
device = chip['device']
fan_index = chip['index_map']
sysfs_path = "%s%s/%s" % (
EMC2305_PATH, device, EMC2305_FAN_INPUT)
sysfs_path = sysfs_path.format(fan_index[self.index])
try:
with open(sysfs_path, 'r') as file:
raw = file.read().strip('\r\n')
pwm.append(int(raw, 10))
except IOError:
raise IOError("Unable to open " + sysfs_path)
speed = math.ceil(
float(pwm[0]) * 100 / EMC2305_MAX_PWM)
return int(speed)
def get_target_speed(self):
"""
DX010 platform specific data:
speed_pc = pwm_target/255*100
0 : when PWM mode is use
pwm : when pwm mode is not use
"""
target = 0
pwm = []
emc2305_chips = self.dx010_emc2305_chip
for chip in emc2305_chips:
device = chip['device']
fan_index = chip['index_map']
sysfs_path = "%s%s/%s" % (
EMC2305_PATH, device, EMC2305_FAN_TARGET)
sysfs_path = sysfs_path.format(fan_index[self.index])
try:
with open(sysfs_path, 'r') as file:
raw = file.read().strip('\r\n')
pwm.append(int(raw, 10))
except IOError:
raise IOError("Unable to open " + sysfs_path)
target = pwm[0] * 100 / EMC2305_MAX_PWM
return target
def get_speed_tolerance(self):
"""
Retrieves the speed tolerance of the fan
Returns:
An integer, the percentage of variance from target speed which is
considered tolerable
"""
return 10
def set_speed(self, speed):
"""
Depends on pwm or target mode is selected:
1) pwm = speed_pc * 255 <-- Currently use this mode.
2) target_pwm = speed_pc * 100 / 255
2.1) set pwm{}_enable to 3
"""
pwm = speed * 255 / 100
emc2305_chips = self.dx010_emc2305_chip
for chip in emc2305_chips:
device = chip['device']
fan_index = chip['index_map']
sysfs_path = "%s%s/%s" % (
EMC2305_PATH, device, EMC2305_FAN_PWM)
sysfs_path = sysfs_path.format(fan_index[self.index])
try:
with open(sysfs_path, 'w') as file:
file.write(str(int(pwm)))
except IOError:
return False
return True
def set_status_led(self, color):
try:
if color == self.STATUS_LED_COLOR_GREEN:
self.set_gpio_value(
self.dx010_fan_gpio[self.index+1]['color']['red'], 1)
self.set_gpio_value(
self.dx010_fan_gpio[self.index+1]['color']['green'], 0)
elif color == self.STATUS_LED_COLOR_RED:
self.set_gpio_value(
self.dx010_fan_gpio[self.index+1]['color']['red'], 0)
self.set_gpio_value(
self.dx010_fan_gpio[self.index+1]['color']['green'], 1)
elif color == self.STATUS_LED_COLOR_OFF:
self.set_gpio_value(
self.dx010_fan_gpio[self.index+1]['color']['red'], 1)
self.set_gpio_value(
self.dx010_fan_gpio[self.index+1]['color']['green'], 1)
else:
return False
except IOError:
return False
return True

23
device/celestica/x86_64-cel_seastone-r0/sonic_platform/platform.py Normal file
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@ -0,0 +1,23 @@
#!/usr/bin/env python
#############################################################################
# Celestica
#
# Module contains an implementation of SONiC Platform Base API and
# provides the platform information
#
#############################################################################
try:
from sonic_platform_base.platform_base import PlatformBase
from sonic_platform.chassis import Chassis
except ImportError as e:
raise ImportError(str(e) + "- required module not found")
class Platform(PlatformBase):
"""Platform-specific Platform class"""
def __init__(self):
PlatformBase.__init__(self)
self._chassis = Chassis()

22
device/dell/x86_64-dell_s6100_c2538-r0/sensors.conf
View File

@ -4,6 +4,26 @@ label power2 "PSU1 Output Power"
label power3 "PSU2 Input Power"
label power4 "PSU2 Output Power"
label temp14 "PSU1 Temp"
label temp15 "PSU1 Temp"
label temp15 "PSU2 Temp"
label curr601 "PSU1 Input Current"
label curr602 "PSU1 Output Current"
label curr701 "PSU2 Input Current"
label curr702 "PSU2 Output Current"
ignore temp12
ignore temp13
ignore in101
ignore in102
ignore in103
ignore in104
ignore in201
ignore in202
ignore in203
ignore in204
ignore in301
ignore in302
ignore in303
ignore in304
ignore in401
ignore in402
ignore in403
ignore in404

51
device/dell/x86_64-dell_z9100_c2538-r0/Force10-Z9100-C32/led_proc_init.soc Normal file
View File

@ -0,0 +1,51 @@
# LED microprocessor initialization for Dell Z9100
#
#
#Led0
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=3 REMAP_PORT_61=2 REMAP_PORT_62=1 REMAP_PORT_63=0
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=7 REMAP_PORT_57=6 REMAP_PORT_58=5 REMAP_PORT_59=4
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=11 REMAP_PORT_53=10 REMAP_PORT_54=9 REMAP_PORT_55=8
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=15 REMAP_PORT_49=14 REMAP_PORT_50=13 REMAP_PORT_51=12
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=19 REMAP_PORT_9=18 REMAP_PORT_10=17 REMAP_PORT_11=16
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=23 REMAP_PORT_13=22 REMAP_PORT_14=21 REMAP_PORT_15=20
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=27 REMAP_PORT_1=26 REMAP_PORT_2=25 REMAP_PORT_3=24
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=31 REMAP_PORT_5=30 REMAP_PORT_6=29 REMAP_PORT_7=28
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=35 REMAP_PORT_41=34 REMAP_PORT_42=33 REMAP_PORT_43=32
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=39 REMAP_PORT_45=38 REMAP_PORT_46=37 REMAP_PORT_47=36
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=43 REMAP_PORT_33=42 REMAP_PORT_34=41 REMAP_PORT_35=40
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=47 REMAP_PORT_37=46 REMAP_PORT_38=45 REMAP_PORT_39=44
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=51 REMAP_PORT_25=50 REMAP_PORT_26=49 REMAP_PORT_27=48
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=55 REMAP_PORT_29=54 REMAP_PORT_30=53 REMAP_PORT_31=52
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=59 REMAP_PORT_17=58 REMAP_PORT_18=57 REMAP_PORT_19=56
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=63 REMAP_PORT_21=62 REMAP_PORT_22=61 REMAP_PORT_23=60
#Led1
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=3 REMAP_PORT_17=2 REMAP_PORT_18=1 REMAP_PORT_19=0
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=7 REMAP_PORT_21=6 REMAP_PORT_22=5 REMAP_PORT_23=4
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=11 REMAP_PORT_25=10 REMAP_PORT_26=9 REMAP_PORT_27=8
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=15 REMAP_PORT_29=14 REMAP_PORT_30=13 REMAP_PORT_31=12
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=19 REMAP_PORT_33=18 REMAP_PORT_34=17 REMAP_PORT_35=16
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=23 REMAP_PORT_37=22 REMAP_PORT_38=21 REMAP_PORT_39=20
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=27 REMAP_PORT_41=26 REMAP_PORT_42=25 REMAP_PORT_43=24
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=31 REMAP_PORT_45=30 REMAP_PORT_46=29 REMAP_PORT_47=28
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=35 REMAP_PORT_5=34 REMAP_PORT_6=33 REMAP_PORT_7=32
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=39 REMAP_PORT_1=38 REMAP_PORT_2=37 REMAP_PORT_3=36
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=43 REMAP_PORT_13=42 REMAP_PORT_14=41 REMAP_PORT_15=40
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=47 REMAP_PORT_9=46 REMAP_PORT_10=45 REMAP_PORT_11=44
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=51 REMAP_PORT_49=50 REMAP_PORT_50=49 REMAP_PORT_51=48
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=55 REMAP_PORT_53=54 REMAP_PORT_54=53 REMAP_PORT_55=52
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=59 REMAP_PORT_57=58 REMAP_PORT_58=57 REMAP_PORT_59=56
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=63 REMAP_PORT_61=62 REMAP_PORT_62=61 REMAP_PORT_63=60
led 0 stop
led 0 prog 02 A8 60 AA 02 00 60 A7 02 00 60 FE 02 00 60 AB 06 A7 D2 08 74 20 02 A9 60 AA 06 A7 E2 08 60 A7 06 FE 28 67 3D 86 FE 06 FE 86 AB 06 AB D2 04 71 10 86 A7 06 FE D2 40 71 0C 86 FF 3A 80 32 08 97 71 7C 77 4C 57 22 0E 87 22 0E 87 57 22 0F 87 22 0F 87 57 22 0F 87 22 0E 87 57 06 AA 61 A6 16 A7 49 27 16 A6 97 71 53 77 45 57 02 0A 50 95 75 74 85 75 5A 57 16 FF CA 05 74 4C 77 5A 06 FE 12 BC F8 32 00 32 01 B7 97 71 6A 77 5A
led 0 auto on
led 0 start
led 1 stop
led 1 prog 02 A8 60 AA 02 00 60 A7 02 00 60 FE 02 00 60 AB 06 A7 D2 08 74 20 02 A9 60 AA 06 A7 E2 08 60 A7 06 FE 28 67 3D 86 FE 06 FE 86 AB 06 AB D2 04 71 10 86 A7 06 FE D2 40 71 0C 86 FF 3A 80 32 08 97 71 7C 77 4C 57 22 0E 87 22 0E 87 57 22 0F 87 22 0F 87 57 22 0F 87 22 0E 87 57 06 AA 61 A6 16 A7 49 27 16 A6 97 71 53 77 45 57 02 0A 50 95 75 74 85 75 5A 57 16 FF CA 05 74 4C 77 5A 06 FE 12 BC F8 32 00 32 01 B7 97 71 6A 77 5A
led 1 auto on
led 1 start
led 2 stop

66
device/dell/x86_64-dell_z9100_c2538-r0/Force10-Z9100-C32/port_config.ini
View File

@ -1,33 +1,33 @@
# name lanes alias
Ethernet0 49,50,51,52 hundredGigE1/1
Ethernet4 53,54,55,56 hundredGigE1/2
Ethernet8 57,58,59,60 hundredGigE1/3
Ethernet12 61,62,63,64 hundredGigE1/4
Ethernet16 65,66,67,68 hundredGigE1/5
Ethernet20 69,70,71,72 hundredGigE1/6
Ethernet24 73,74,75,76 hundredGigE1/7
Ethernet28 77,78,79,80 hundredGigE1/8
Ethernet32 37,38,39,40 hundredGigE1/9
Ethernet36 33,34,35,36 hundredGigE1/10
Ethernet40 45,46,47,48 hundredGigE1/11
Ethernet44 41,42,43,44 hundredGigE1/12
Ethernet48 81,82,83,84 hundredGigE1/13
Ethernet52 85,86,87,88 hundredGigE1/14
Ethernet56 89,90,91,92 hundredGigE1/15
Ethernet60 93,94,95,96 hundredGigE1/16
Ethernet64 97,98,99,100 hundredGigE1/17
Ethernet68 101,102,103,104 hundredGigE1/18
Ethernet72 105,106,107,108 hundredGigE1/19
Ethernet76 109,110,111,112 hundredGigE1/20
Ethernet80 21,22,23,24 hundredGigE1/21
Ethernet84 17,18,19,20 hundredGigE1/22
Ethernet88 29,30,31,32 hundredGigE1/23
Ethernet92 25,26,27,28 hundredGigE1/24
Ethernet96 117,118,119,120 hundredGigE1/25
Ethernet100 113,114,115,116 hundredGigE1/26
Ethernet104 125,126,127,128 hundredGigE1/27
Ethernet108 121,122,123,124 hundredGigE1/28
Ethernet112 5,6,7,8 hundredGigE1/29
Ethernet116 1,2,3,4 hundredGigE1/30
Ethernet120 13,14,15,16 hundredGigE1/31
Ethernet124 9,10,11,12 hundredGigE1/32
# name lanes alias index
Ethernet0 49,50,51,52 hundredGigE1/1 1
Ethernet4 53,54,55,56 hundredGigE1/2 2
Ethernet8 57,58,59,60 hundredGigE1/3 3
Ethernet12 61,62,63,64 hundredGigE1/4 4
Ethernet16 65,66,67,68 hundredGigE1/5 5
Ethernet20 69,70,71,72 hundredGigE1/6 6
Ethernet24 73,74,75,76 hundredGigE1/7 7
Ethernet28 77,78,79,80 hundredGigE1/8 8
Ethernet32 37,38,39,40 hundredGigE1/9 9
Ethernet36 33,34,35,36 hundredGigE1/10 10
Ethernet40 45,46,47,48 hundredGigE1/11 11
Ethernet44 41,42,43,44 hundredGigE1/12 12
Ethernet48 81,82,83,84 hundredGigE1/13 13
Ethernet52 85,86,87,88 hundredGigE1/14 14
Ethernet56 89,90,91,92 hundredGigE1/15 15
Ethernet60 93,94,95,96 hundredGigE1/16 16
Ethernet64 97,98,99,100 hundredGigE1/17 17
Ethernet68 101,102,103,104 hundredGigE1/18 18
Ethernet72 105,106,107,108 hundredGigE1/19 19
Ethernet76 109,110,111,112 hundredGigE1/20 20
Ethernet80 21,22,23,24 hundredGigE1/21 21
Ethernet84 17,18,19,20 hundredGigE1/22 22
Ethernet88 29,30,31,32 hundredGigE1/23 23
Ethernet92 25,26,27,28 hundredGigE1/24 24
Ethernet96 117,118,119,120 hundredGigE1/25 25
Ethernet100 113,114,115,116 hundredGigE1/26 26
Ethernet104 125,126,127,128 hundredGigE1/27 27
Ethernet108 121,122,123,124 hundredGigE1/28 28
Ethernet112 5,6,7,8 hundredGigE1/29 29
Ethernet116 1,2,3,4 hundredGigE1/30 30
Ethernet120 13,14,15,16 hundredGigE1/31 31
Ethernet124 9,10,11,12 hundredGigE1/32 32

58
device/dell/x86_64-dell_z9100_c2538-r0/Force10-Z9100-C8D48/led_proc_init.soc Normal file
View File

@ -0,0 +1,58 @@
# LED microprocessor initialization for Dell Z9100
#
#
#Led0
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=3 REMAP_PORT_61=2 REMAP_PORT_62=1 REMAP_PORT_63=0
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=7 REMAP_PORT_57=6 REMAP_PORT_58=5 REMAP_PORT_59=4
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=11 REMAP_PORT_53=10 REMAP_PORT_54=9 REMAP_PORT_55=8
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=15 REMAP_PORT_49=14 REMAP_PORT_50=13 REMAP_PORT_51=12
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=19 REMAP_PORT_9=18 REMAP_PORT_10=17 REMAP_PORT_11=16
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=23 REMAP_PORT_13=22 REMAP_PORT_14=21 REMAP_PORT_15=20
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=27 REMAP_PORT_1=26 REMAP_PORT_2=25 REMAP_PORT_3=24
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=31 REMAP_PORT_5=30 REMAP_PORT_6=29 REMAP_PORT_7=28
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=35 REMAP_PORT_41=34 REMAP_PORT_42=33 REMAP_PORT_43=32
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=39 REMAP_PORT_45=38 REMAP_PORT_46=37 REMAP_PORT_47=36
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=43 REMAP_PORT_33=42 REMAP_PORT_34=41 REMAP_PORT_35=40
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=47 REMAP_PORT_37=46 REMAP_PORT_38=45 REMAP_PORT_39=44
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=51 REMAP_PORT_25=50 REMAP_PORT_26=49 REMAP_PORT_27=48
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=55 REMAP_PORT_29=54 REMAP_PORT_30=53 REMAP_PORT_31=52
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=59 REMAP_PORT_17=58 REMAP_PORT_18=57 REMAP_PORT_19=56
modreg CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=63 REMAP_PORT_21=62 REMAP_PORT_22=61 REMAP_PORT_23=60
#Led1
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=3 REMAP_PORT_17=2 REMAP_PORT_18=1 REMAP_PORT_19=0
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=7 REMAP_PORT_21=6 REMAP_PORT_22=5 REMAP_PORT_23=4
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=11 REMAP_PORT_25=10 REMAP_PORT_26=9 REMAP_PORT_27=8
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=15 REMAP_PORT_29=14 REMAP_PORT_30=13 REMAP_PORT_31=12
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=19 REMAP_PORT_33=18 REMAP_PORT_34=17 REMAP_PORT_35=16
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=23 REMAP_PORT_37=22 REMAP_PORT_38=21 REMAP_PORT_39=20
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=27 REMAP_PORT_41=26 REMAP_PORT_42=25 REMAP_PORT_43=24
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=31 REMAP_PORT_45=30 REMAP_PORT_46=29 REMAP_PORT_47=28
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=35 REMAP_PORT_5=34 REMAP_PORT_6=33 REMAP_PORT_7=32
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=39 REMAP_PORT_1=38 REMAP_PORT_2=37 REMAP_PORT_3=36
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=43 REMAP_PORT_13=42 REMAP_PORT_14=41 REMAP_PORT_15=40
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=47 REMAP_PORT_9=46 REMAP_PORT_10=45 REMAP_PORT_11=44
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=51 REMAP_PORT_49=50 REMAP_PORT_50=49 REMAP_PORT_51=48
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=55 REMAP_PORT_53=54 REMAP_PORT_54=53 REMAP_PORT_55=52
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=59 REMAP_PORT_57=58 REMAP_PORT_58=57 REMAP_PORT_59=56
modreg CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=63 REMAP_PORT_61=62 REMAP_PORT_62=61 REMAP_PORT_63=60
led 0 stop
led 0 prog 02 A8 60 AA 02 00 60 A7 02 00 60 FE 02 00 60 AB 06 A7 D2 08 74 20 02 A9 60 AA 06 A7 E2 08 60 A7 06 FE 28 67 3D 86 FE 06 FE 86 AB 06 AB D2 04 71 10 86 A7 06 FE D2 40 71 0C 86 FF 3A 80 32 08 97 71 7C 77 4C 57 22 0E 87 22 0E 87 57 22 0F 87 22 0F 87 57 22 0F 87 22 0E 87 57 06 AA 61 A6 16 A7 49 27 16 A6 97 71 53 77 45 57 02 0A 50 95 75 74 85 75 5A 57 16 FF CA 05 74 4C 77 5A 06 FE 12 BC F8 32 00 32 01 B7 97 71 6A 77 5A
led 0 auto on
led 0 start
led 1 stop
led 1 prog 02 A8 60 AA 02 00 60 A7 02 00 60 FE 02 00 60 AB 06 A7 D2 08 74 20 02 A9 60 AA 06 A7 E2 08 60 A7 06 FE 28 67 3D 86 FE 06 FE 86 AB 06 AB D2 04 71 10 86 A7 06 FE D2 40 71 0C 86 FF 3A 80 32 08 97 71 7C 77 4C 57 22 0E 87 22 0E 87 57 22 0F 87 22 0F 87 57 22 0F 87 22 0E 87 57 06 AA 61 A6 16 A7 49 27 16 A6 97 71 53 77 45 57 02 0A 50 95 75 74 85 75 5A 57 16 FF CA 05 74 4C 77 5A 06 FE 12 BC F8 32 00 32 01 B7 97 71 6A 77 5A
led 1 auto on
led 1 start
led 2 stop
setreg CMIC_LEDUP1_DATA_RAM[0xa8] 0x3f
setreg CMIC_LEDUP1_DATA_RAM[0xa9] 0xFC
setreg CMIC_LEDUP0_DATA_RAM[0xa8] 0xff
setreg CMIC_LEDUP0_DATA_RAM[0xa9] 0xC3

2
device/dell/x86_64-dell_z9100_c2538-r0/plugins/sfputil.py
View File

@ -78,7 +78,7 @@ class SfpUtil(SfpUtilBase):
@property
def qsfp_ports(self):
return range(0, self.PORTS_IN_BLOCK + 1)
return range(self.PORT_START, self.PORTS_IN_BLOCK + 1)
@property
def iom1_port_start(self):

22
device/dell/x86_64-dell_z9100_c2538-r0/sensors.conf
View File

@ -4,9 +4,29 @@ label power2 "PSU1 Output Power"
label power3 "PSU2 Input Power"
label power4 "PSU2 Output Power"
label temp14 "PSU1 Temp"
label temp15 "PSU1 Temp"
label temp15 "PSU2 Temp"
label curr601 "PSU1 Input Current"
label curr602 "PSU1 Output Current"
label curr701 "PSU2 Input Current"
label curr702 "PSU2 Output Current"
ignore temp12
ignore temp13
ignore temp5
ignore temp7
ignore temp8
ignore in101
ignore in102
ignore in103
ignore in104
ignore in201
ignore in202
ignore in203
ignore in204
ignore in301
ignore in302
ignore in303
ignore in304
ignore in401
ignore in402
ignore in403
ignore in404

2
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-C64/buffers.json.j2 Normal file
View File

@ -0,0 +1,2 @@
{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}

47
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-C64/buffers_defaults_t1.j2 Normal file
View File

@ -0,0 +1,47 @@
{%- set default_cable = '40m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx*4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "34859968",
"type": "ingress",
"mode": "dynamic",
"xoff": "7847424"
},
"egress_lossy_pool": {
"size": "29631680",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "43481152",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"size":"0",
"dynamic_th":"3"
},
"egress_lossless_profile": {
"pool":"[BUFFER_POOL|egress_lossless_pool]",
"size":"1518",
"static_th":"10870288"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"1518",
"dynamic_th":"3"
}
},
{%- endmacro %}

17
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-C64/pg_profile_lookup.ini Normal file
View File

@ -0,0 +1,17 @@
# PG lossless profiles.
# speed cable size xon xoff threshold xon_offset
10000 5m 1248 2288 35776 -3 2288
25000 5m 1248 2288 53248 -3 2288
40000 5m 1248 2288 66560 -3 2288
50000 5m 1248 2288 90272 -3 2288
100000 5m 1248 2288 165568 -3 2288
10000 40m 1248 2288 37024 -3 2288
25000 40m 1248 2288 53248 -3 2288
40000 40m 1248 2288 71552 -3 2288
50000 40m 1248 2288 96096 -3 2288
100000 40m 1248 2288 177632 -3 2288
10000 300m 1248 2288 46176 -3 2288
25000 300m 1248 2288 79040 -3 2288
40000 300m 1248 2288 108160 -3 2288
50000 300m 1248 2288 141856 -3 2288
100000 300m 1248 2288 268736 -3 2288

65
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-C64/port_config.ini Normal file
View File

@ -0,0 +1,65 @@
# name lanes alias index speed
Ethernet0 49,50,51,52 hundredGigE1/1 1 100000
Ethernet4 53,54,55,56 hundredGigE1/2 2 100000
Ethernet8 65,66,67,68 hundredGigE1/3 3 100000
Ethernet12 69,70,71,72 hundredGigE1/4 4 100000
Ethernet16 81,82,83,84 hundredGigE1/5 5 100000
Ethernet20 85,86,87,88 hundredGigE1/6 6 100000
Ethernet24 97,98,99,100 hundredGigE1/7 7 100000
Ethernet28 101,102,103,104 hundredGigE1/8 8 100000
Ethernet32 1,2,3,4 hundredGigE1/9 9 100000
Ethernet36 5,6,7,8 hundredGigE1/10 10 100000
Ethernet40 17,18,19,20 hundredGigE1/11 11 100000
Ethernet44 21,22,23,24 hundredGigE1/12 12 100000
Ethernet48 33,34,35,36 hundredGigE1/13 13 100000
Ethernet52 37,38,39,40 hundredGigE1/14 14 100000
Ethernet56 113,114,115,116 hundredGigE1/15 15 100000
Ethernet60 117,118,119,120 hundredGigE1/16 16 100000
Ethernet64 133,134,135,136 hundredGigE1/17 17 100000
Ethernet68 129,130,131,132 hundredGigE1/18 18 100000
Ethernet72 213,214,215,216 hundredGigE1/19 19 100000
Ethernet76 209,210,211,212 hundredGigE1/20 20 100000
Ethernet80 229,230,231,232 hundredGigE1/21 21 100000
Ethernet84 225,226,227,228 hundredGigE1/22 22 100000
Ethernet88 245,246,247,248 hundredGigE1/23 23 100000
Ethernet92 241,242,243,244 hundredGigE1/24 24 100000
Ethernet96 149,150,151,152 hundredGigE1/25 25 100000
Ethernet100 145,146,147,148 hundredGigE1/26 26 100000
Ethernet104 165,166,167,168 hundredGigE1/27 27 100000
Ethernet108 161,162,163,164 hundredGigE1/28 28 100000
Ethernet112 181,182,183,184 hundredGigE1/29 29 100000
Ethernet116 177,178,179,180 hundredGigE1/30 30 100000
Ethernet120 197,198,199,200 hundredGigE1/31 31 100000
Ethernet124 193,194,195,196 hundredGigE1/32 32 100000
Ethernet128 61,62,63,64 hundredGigE1/33 33 100000
Ethernet132 57,58,59,60 hundredGigE1/34 34 100000
Ethernet136 77,78,79,80 hundredGigE1/35 35 100000
Ethernet140 73,74,75,76 hundredGigE1/36 36 100000
Ethernet144 93,94,95,96 hundredGigE1/37 37 100000
Ethernet148 89,90,91,92 hundredGigE1/38 38 100000
Ethernet152 109,110,111,112 hundredGigE1/39 39 100000
Ethernet156 105,106,107,108 hundredGigE1/40 40 100000
Ethernet160 13,14,15,16 hundredGigE1/41 41 100000
Ethernet164 9,10,11,12 hundredGigE1/42 42 100000
Ethernet168 29,30,31,32 hundredGigE1/43 43 100000
Ethernet172 25,26,27,28 hundredGigE1/44 44 100000
Ethernet176 45,46,47,48 hundredGigE1/45 45 100000
Ethernet180 41,42,43,44 hundredGigE1/46 46 100000
Ethernet184 125,126,127,128 hundredGigE1/47 47 100000
Ethernet188 121,122,123,124 hundredGigE1/48 48 100000
Ethernet192 137,138,139,140 hundredGigE1/49 49 100000
Ethernet196 141,142,143,144 hundredGigE1/50 50 100000
Ethernet200 217,218,219,220 hundredGigE1/51 51 100000
Ethernet204 221,222,223,224 hundredGigE1/52 52 100000
Ethernet208 233,234,235,236 hundredGigE1/53 53 100000
Ethernet212 237,238,239,240 hundredGigE1/54 54 100000
Ethernet216 249,250,251,252 hundredGigE1/55 55 100000
Ethernet220 253,254,255,256 hundredGigE1/56 56 100000
Ethernet224 153,154,155,156 hundredGigE1/57 57 100000
Ethernet228 157,158,159,160 hundredGigE1/58 58 100000
Ethernet232 169,170,171,172 hundredGigE1/59 59 100000
Ethernet236 173,174,175,176 hundredGigE1/60 60 100000
Ethernet240 185,186,187,188 hundredGigE1/61 61 100000
Ethernet244 189,190,191,192 hundredGigE1/62 62 100000
Ethernet248 201,202,203,204 hundredGigE1/63 63 100000
Ethernet252 205,206,207,208 hundredGigE1/64 64 100000

1
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-C64/qos.json.j2 Normal file
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@ -0,0 +1 @@
{%- include 'qos_config.j2' %}

0
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f/sai.profile → device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-C64/sai.profile
View File

0
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f/th2-z9264f-64x100G.config.bcm → device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-C64/th2-z9264f-64x100G.config.bcm
View File

2
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/buffers.json.j2 Normal file
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@ -0,0 +1,2 @@
{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}

47
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/buffers_defaults_t0.j2 Normal file
View File

@ -0,0 +1,47 @@
{%- set default_cable = '5m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx*4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "38738752",
"type": "ingress",
"mode": "dynamic",
"xoff": "3855488"
},
"egress_lossy_pool": {
"size": "37057280",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "43507776",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"size":"0",
"dynamic_th":"3"
},
"egress_lossless_profile": {
"pool":"[BUFFER_POOL|egress_lossless_pool]",
"size":"1518",
"static_th":"10876944"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"1518",
"dynamic_th":"3"
}
},
{%- endmacro %}

47
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/buffers_defaults_t1.j2 Normal file
View File

@ -0,0 +1,47 @@
{%- set default_cable = '40m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx*4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "37968320",
"type": "ingress",
"mode": "dynamic",
"xoff": "4625920"
},
"egress_lossy_pool": {
"size": "36402496",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "43507776",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"size":"0",
"dynamic_th":"3"
},
"egress_lossless_profile": {
"pool":"[BUFFER_POOL|egress_lossless_pool]",
"size":"1518",
"static_th":"10876944"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"1518",
"dynamic_th":"3"
}
},
{%- endmacro %}

17
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/pg_profile_lookup.ini Normal file
View File

@ -0,0 +1,17 @@
# PG lossless profiles.
# speed cable size xon xoff threshold xon_offset
10000 5m 1248 2288 35776 -3 2288
25000 5m 1248 2288 53248 -3 2288
40000 5m 1248 2288 66560 -3 2288
50000 5m 1248 2288 90272 -3 2288
100000 5m 1248 2288 165568 -3 2288
10000 40m 1248 2288 37024 -3 2288
25000 40m 1248 2288 53248 -3 2288
40000 40m 1248 2288 71552 -3 2288
50000 40m 1248 2288 96096 -3 2288
100000 40m 1248 2288 177632 -3 2288
10000 300m 1248 2288 46176 -3 2288
25000 300m 1248 2288 79040 -3 2288
40000 300m 1248 2288 108160 -3 2288
50000 300m 1248 2288 141856 -3 2288
100000 300m 1248 2288 268736 -3 2288

65
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/port_config.ini Normal file
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@ -0,0 +1,65 @@
# name lanes alias index speed
Ethernet0 49,50,51,52 fortyGigE1/1 1 40000
Ethernet4 53,54,55,56 fortyGigE1/2 2 40000
Ethernet8 65,66,67,68 fortyGigE1/3 3 40000
Ethernet12 69,70,71,72 fortyGigE1/4 4 40000
Ethernet16 81,82,83,84 fortyGigE1/5 5 40000
Ethernet20 85,86,87,88 fortyGigE1/6 6 40000
Ethernet24 97,98,99,100 fortyGigE1/7 7 40000
Ethernet28 101,102,103,104 fortyGigE1/8 8 40000
Ethernet32 1,2,3,4 fortyGigE1/9 9 40000
Ethernet36 5,6,7,8 fortyGigE1/10 10 40000
Ethernet40 17,18,19,20 fortyGigE1/11 11 40000
Ethernet44 21,22,23,24 fortyGigE1/12 12 40000
Ethernet48 33,34,35,36 fortyGigE1/13 13 40000
Ethernet52 37,38,39,40 fortyGigE1/14 14 40000
Ethernet56 113,114,115,116 fortyGigE1/15 15 40000
Ethernet60 117,118,119,120 fortyGigE1/16 16 40000
Ethernet64 133,134,135,136 fortyGigE1/17 17 40000
Ethernet68 129,130,131,132 fortyGigE1/18 18 40000
Ethernet72 213,214,215,216 fortyGigE1/19 19 40000
Ethernet76 209,210,211,212 fortyGigE1/20 20 40000
Ethernet80 229,230,231,232 fortyGigE1/21 21 40000
Ethernet84 225,226,227,228 fortyGigE1/22 22 40000
Ethernet88 245,246,247,248 fortyGigE1/23 23 40000
Ethernet92 241,242,243,244 fortyGigE1/24 24 40000
Ethernet96 149,150,151,152 fortyGigE1/25 25 40000
Ethernet100 145,146,147,148 fortyGigE1/26 26 40000
Ethernet104 165,166,167,168 fortyGigE1/27 27 40000
Ethernet108 161,162,163,164 fortyGigE1/28 28 40000
Ethernet112 181,182,183,184 fortyGigE1/29 29 40000
Ethernet116 177,178,179,180 fortyGigE1/30 30 40000
Ethernet120 197,198,199,200 fortyGigE1/31 31 40000
Ethernet124 193,194,195,196 fortyGigE1/32 32 40000
Ethernet128 61,62,63,64 fortyGigE1/33 33 40000
Ethernet132 57,58,59,60 fortyGigE1/34 34 40000
Ethernet136 77,78,79,80 fortyGigE1/35 35 40000
Ethernet140 73,74,75,76 fortyGigE1/36 36 40000
Ethernet144 93,94,95,96 fortyGigE1/37 37 40000
Ethernet148 89,90,91,92 fortyGigE1/38 38 40000
Ethernet152 109,110,111,112 fortyGigE1/39 39 40000
Ethernet156 105,106,107,108 fortyGigE1/40 40 40000
Ethernet160 13,14,15,16 fortyGigE1/41 41 40000
Ethernet164 9,10,11,12 fortyGigE1/42 42 40000
Ethernet168 29,30,31,32 fortyGigE1/43 43 40000
Ethernet172 25,26,27,28 fortyGigE1/44 44 40000
Ethernet176 45,46,47,48 fortyGigE1/45 45 40000
Ethernet180 41,42,43,44 fortyGigE1/46 46 40000
Ethernet184 125,126,127,128 fortyGigE1/47 47 40000
Ethernet188 121,122,123,124 fortyGigE1/48 48 40000
Ethernet192 137,138,139,140 fortyGigE1/49 49 40000
Ethernet196 141,142,143,144 fortyGigE1/50 50 40000
Ethernet200 217,218,219,220 fortyGigE1/51 51 40000
Ethernet204 221,222,223,224 fortyGigE1/52 52 40000
Ethernet208 233,234,235,236 fortyGigE1/53 53 40000
Ethernet212 237,238,239,240 fortyGigE1/54 54 40000
Ethernet216 249,250,251,252 fortyGigE1/55 55 40000
Ethernet220 253,254,255,256 fortyGigE1/56 56 40000
Ethernet224 153,154,155,156 fortyGigE1/57 57 40000
Ethernet228 157,158,159,160 fortyGigE1/58 58 40000
Ethernet232 169,170,171,172 fortyGigE1/59 59 40000
Ethernet236 173,174,175,176 fortyGigE1/60 60 40000
Ethernet240 185,186,187,188 fortyGigE1/61 61 40000
Ethernet244 189,190,191,192 fortyGigE1/62 62 40000
Ethernet248 201,202,203,204 fortyGigE1/63 63 40000
Ethernet252 205,206,207,208 fortyGigE1/64 64 40000

1
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/qos.json.j2 Normal file
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@ -0,0 +1 @@
{%- include 'qos_config.j2' %}

13
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/sai.profile.j2 Normal file
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@ -0,0 +1,13 @@
{# Get sai.profile based on switch_role #}
{%- if DEVICE_METADATA is defined -%}
{%- set switch_role = DEVICE_METADATA['localhost']['type'] -%}
{%- if switch_role.lower() == 'torrouter' %}
{% set sai_profile_contents = 'SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th2-z9264f-64x40G-t0.config.bcm' -%}
{%- else %}
{%- set sai_profile_contents = 'SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th2-z9264f-64x40G-t1.config.bcm' -%}
{%- endif %}
{%- else %}
{%- set sai_profile_contents = 'SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th2-z9264f-64x40G-t1.config.bcm' -%}
{%- endif %}
{# Write the contents of sai_ profile_filename to sai.profile file #}
{{ sai_profile_contents }}

1007
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/th2-z9264f-64x40G-t0.config.bcm Normal file
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File diff suppressed because it is too large Load Diff

1007
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f-Q64/th2-z9264f-64x40G-t1.config.bcm Normal file
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File diff suppressed because it is too large Load Diff

65
device/dell/x86_64-dellemc_z9264f_c3538-r0/DellEMC-Z9264f/port_config.ini
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@ -1,65 +0,0 @@
# name lanes alias index
Ethernet0 49,50,51,52 hundredGigE1/1 0
Ethernet4 53,54,55,56 hundredGigE1/2 1
Ethernet8 65,66,67,68 hundredGigE1/3 2
Ethernet12 69,70,71,72 hundredGigE1/4 3
Ethernet16 81,82,83,84 hundredGigE1/5 4
Ethernet20 85,86,87,88 hundredGigE1/6 5
Ethernet24 97,98,99,100 hundredGigE1/7 6
Ethernet28 101,102,103,104 hundredGigE1/8 7
Ethernet32 1,2,3,4 hundredGigE1/9 8
Ethernet36 5,6,7,8 hundredGigE1/10 9
Ethernet40 17,18,19,20 hundredGigE1/11 10
Ethernet44 21,22,23,24 hundredGigE1/12 11
Ethernet48 33,34,35,36 hundredGigE1/13 12
Ethernet52 37,38,39,40 hundredGigE1/14 13
Ethernet56 113,114,115,116 hundredGigE1/15 14
Ethernet60 117,118,119,120 hundredGigE1/16 15
Ethernet64 133,134,135,136 hundredGigE1/17 16
Ethernet68 129,130,131,132 hundredGigE1/18 17
Ethernet72 213,214,215,216 hundredGigE1/19 18
Ethernet76 209,210,211,212 hundredGigE1/20 19
Ethernet80 229,230,231,232 hundredGigE1/21 20
Ethernet84 225,226,227,228 hundredGigE1/22 21
Ethernet88 245,246,247,248 hundredGigE1/23 22
Ethernet92 241,242,243,244 hundredGigE1/24 23
Ethernet96 149,150,151,152 hundredGigE1/25 24
Ethernet100 145,146,147,148 hundredGigE1/26 25
Ethernet104 165,166,167,168 hundredGigE1/27 26
Ethernet108 161,162,163,164 hundredGigE1/28 27
Ethernet112 181,182,183,184 hundredGigE1/29 28
Ethernet116 177,178,179,180 hundredGigE1/30 29
Ethernet120 197,198,199,200 hundredGigE1/31 30
Ethernet124 193,194,195,196 hundredGigE1/32 31
Ethernet128 61,62,63,64 hundredGigE1/33 32
Ethernet132 57,58,59,60 hundredGigE1/34 33
Ethernet136 77,78,79,80 hundredGigE1/35 34
Ethernet140 73,74,75,76 hundredGigE1/36 35
Ethernet144 93,94,95,96 hundredGigE1/37 36
Ethernet148 89,90,91,92 hundredGigE1/38 37
Ethernet152 109,110,111,112 hundredGigE1/39 38
Ethernet156 105,106,107,108 hundredGigE1/40 39
Ethernet160 13,14,15,16 hundredGigE1/41 40
Ethernet164 9,10,11,12 hundredGigE1/42 41
Ethernet168 29,30,31,32 hundredGigE1/43 42
Ethernet172 25,26,27,28 hundredGigE1/44 43
Ethernet176 45,46,47,48 hundredGigE1/45 44
Ethernet180 41,42,43,44 hundredGigE1/46 45
Ethernet184 125,126,127,128 hundredGigE1/47 46
Ethernet188 121,122,123,124 hundredGigE1/48 47
Ethernet192 137,138,139,140 hundredGigE1/49 48
Ethernet196 141,142,143,144 hundredGigE1/50 49
Ethernet200 217,218,219,220 hundredGigE1/51 50
Ethernet204 221,222,223,224 hundredGigE1/52 51
Ethernet208 233,234,235,236 hundredGigE1/53 52
Ethernet212 237,238,239,240 hundredGigE1/54 53
Ethernet216 249,250,251,252 hundredGigE1/55 54
Ethernet220 253,254,255,256 hundredGigE1/56 55
Ethernet224 153,154,155,156 hundredGigE1/57 56
Ethernet228 157,158,159,160 hundredGigE1/58 57
Ethernet232 169,170,171,172 hundredGigE1/59 58
Ethernet236 173,174,175,176 hundredGigE1/60 59
Ethernet240 185,186,187,188 hundredGigE1/61 60
Ethernet244 189,190,191,192 hundredGigE1/62 61
Ethernet248 201,202,203,204 hundredGigE1/63 62
Ethernet252 205,206,207,208 hundredGigE1/64 63

2
device/dell/x86_64-dellemc_z9264f_c3538-r0/default_sku
View File

@ -1 +1 @@
DellEMC-Z9264f t1
DellEMC-Z9264f-C64 t1

25
device/dell/x86_64-dellemc_z9264f_c3538-r0/platform_reboot
View File

@ -1,25 +0,0 @@
#!/usr/bin/python
import sys
import os
import struct
PORT_RES = '/dev/port'
def portio_reg_write(resource, offset, val):
fd = os.open(resource, os.O_RDWR)
if(fd < 0):
print 'file open failed %s" % resource'
return
if(os.lseek(fd, offset, os.SEEK_SET) != offset):
print 'lseek failed on %s' % resource
return
ret = os.write(fd, struct.pack('B', val))
if(ret != 1):
print 'write failed %d' % ret
return
os.close(fd)
if __name__ == "__main__":
portio_reg_write(PORT_RES, 0xcf9, 0xe)

172
device/dell/x86_64-dellemc_z9264f_c3538-r0/plugins/sfputil.py
View File

@ -8,6 +8,7 @@ try:
import sys
import getopt
import time
import select
from sonic_sfp.sfputilbase import SfpUtilBase
from os import *
from mmap import *
@ -19,11 +20,15 @@ except ImportError as e:
class SfpUtil(SfpUtilBase):
"""Platform-specific SfpUtil class"""
PORT_START = 0
PORT_END = 63
PORTS_IN_BLOCK = 32
PORT_START = 1
PORT_END = 64
PORTS_IN_BLOCK = 64
BASE_RES_PATH = "/sys/bus/pci/devices/0000:04:00.0/resource0"
OIR_FD_PATH = "/sys/bus/pci/devices/0000:04:00.0/port_msi"
oir_fd = -1
epoll = -1
_port_to_eeprom_mapping = {}
@ -39,7 +44,7 @@ class SfpUtil(SfpUtilBase):
@property
def qsfp_ports(self):
return range(0, self.PORTS_IN_BLOCK + 1)
return range(self.PORT_START, self.PORTS_IN_BLOCK + 1)
@property
def port_to_eeprom_mapping(self):
@ -47,8 +52,8 @@ class SfpUtil(SfpUtilBase):
def pci_mem_read(self, mm, offset):
mm.seek(offset)
read_data_stream=mm.read(4)
reg_val=struct.unpack('I',read_data_stream)
read_data_stream = mm.read(4)
reg_val = struct.unpack('I', read_data_stream)
mem_val = str(reg_val)[1:-2]
# print "reg_val read:%x"%reg_val
return mem_val
@ -56,7 +61,7 @@ class SfpUtil(SfpUtilBase):
def pci_mem_write(self, mm, offset, data):
mm.seek(offset)
# print "data to write:%x"%data
mm.write(struct.pack('I',data))
mm.write(struct.pack('I', data))
def pci_set_value(self, resource, val, offset):
fd = open(resource, O_RDWR)
@ -73,7 +78,7 @@ class SfpUtil(SfpUtilBase):
mm.close()
close(fd)
return val
def init_global_port_presence(self):
for port_num in range(self.port_start, (self.port_end + 1)):
presence = self.get_presence(port_num)
@ -81,17 +86,15 @@ class SfpUtil(SfpUtilBase):
self._global_port_pres_dict[port_num] = '1'
else:
self._global_port_pres_dict[port_num] = '0'
def __init__(self):
eeprom_path = "/sys/class/i2c-adapter/i2c-{0}/{0}-0050/eeprom"
for x in range(0, self.port_end + 1):
port_num = x + 2
self.port_to_eeprom_mapping[x] = eeprom_path.format(
port_num)
for x in range(self.port_start, self.port_end + 1):
port_num = x + 1
self.port_to_eeprom_mapping[x] = eeprom_path.format(port_num)
port_num = 0
self.init_global_port_presence()
SfpUtilBase.__init__(self)
def get_presence(self, port_num):
@ -100,13 +103,13 @@ class SfpUtil(SfpUtilBase):
return False
# Port offset starts with 0x4004
port_offset = 16388 + ((port_num) * 16)
port_offset = 16388 + ((port_num-1) * 16)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
# Absence of status throws error
if (reg_value == "" ):
if (reg_value == ""):
return False
# Mask off 4th bit for presence
@ -124,14 +127,14 @@ class SfpUtil(SfpUtilBase):
if port_num < self.port_start or port_num > self.port_end:
return False
# Port offset starts with 0x4000
port_offset = 16384 + ((port_num) * 16)
# Port offset starts with 0x4000
port_offset = 16384 + ((port_num-1) * 16)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
# Absence of status throws error
if (reg_value == "" ):
if (reg_value == ""):
return False
# Mask off 4th bit for presence
@ -149,44 +152,44 @@ class SfpUtil(SfpUtilBase):
if port_num < self.port_start or port_num > self.port_end:
return False
# Port offset starts with 0x4000
port_offset = 16384 + ((port_num) * 16)
# Port offset starts with 0x4000
port_offset = 16384 + ((port_num-1) * 16)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
# Absence of status throws error
if (reg_value == "" ):
if (reg_value == ""):
return False
# Mask off 4th bit for presence
mask = (1 << 6)
# LPMode is active high; set or clear the bit accordingly
# LPMode is active high; set or clear the bit accordingly
if lpmode is True:
reg_value = reg_value | mask
else:
reg_value = reg_value & ~mask
# Convert our register value back to a hex string and write back
status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
return True
def reset(self, port_num):
# Check for invalid port_num
# Check for invalid port_num
if port_num < self.port_start or port_num > self.port_end:
return False
# Port offset starts with 0x4000
port_offset = 16384 + ((port_num) * 16)
# Port offset starts with 0x4000
port_offset = 16384 + ((port_num-1) * 16)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
status = self.pci_get_value(self.BASE_RES_PATH, port_offset)
reg_value = int(status)
# Absence of status throws error
if (reg_value == "" ):
if (reg_value == ""):
return False
# Mask off 4th bit for presence
@ -195,33 +198,106 @@ class SfpUtil(SfpUtilBase):
# ResetL is active low
reg_value = reg_value & ~mask
# Convert our register value back to a hex string and write back
status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
# Convert our register value back to a hex string and write back
status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
# Sleep 1 second to allow it to settle
time.sleep(1)
reg_value = reg_value | mask
# Convert our register value back to a hex string and write back
status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
# Convert our register value back to a hex string and write back
status = self.pci_set_value(self.BASE_RES_PATH, reg_value, port_offset)
return True
def get_transceiver_change_event(self):
port_dict = {}
while True:
def get_register(self, reg_file):
retval = 'ERR'
if (not path.isfile(reg_file)):
print reg_file, 'not found !'
return retval
try:
with fdopen(open(reg_file, O_RDONLY)) as fd:
retval = fd.read()
except Exception as error:
logging.error("Unable to open ", reg_file, "file !")
retval = retval.rstrip('\r\n')
retval = retval.lstrip(" ")
return retval
def check_interrupts(self, port_dict):
retval = 0
is_port_dict_updated = False
for port_num in range(self.port_start, (self.port_end + 1)):
presence = self.get_presence(port_num)
if(presence and self._global_port_pres_dict[port_num] == '0'):
is_port_dict_updated = True
self._global_port_pres_dict[port_num] = '1'
port_dict[port_num] = '1'
elif(not presence and
self._global_port_pres_dict[port_num] == '1'):
is_port_dict_updated = True
self._global_port_pres_dict[port_num] = '0'
port_dict[port_num] = '0'
return retval, is_port_dict_updated
if(len(port_dict) > 0):
return True, port_dict
def get_transceiver_change_event(self, timeout=0):
port_dict = {}
try:
# We get notified when there is a MSI interrupt (vector 4/5)CVR
# Open the sysfs file and register the epoll object
self.oir_fd = fdopen(open(self.OIR_FD_PATH, O_RDONLY))
if self.oir_fd != -1:
# Do a dummy read before epoll register
self.oir_fd.read()
self.epoll = select.epoll()
self.epoll.register(
self.oir_fd.fileno(), select.EPOLLIN & select.EPOLLET)
else:
print("get_transceiver_change_event : unable to create fd")
return False, {}
time.sleep(0.5)
# Check for missed interrupts by invoking self.check_interrupts
# which will update the port_dict.
while True:
interrupt_count_start = self.get_register(self.OIR_FD_PATH)
retval, is_port_dict_updated = \
self.check_interrupts(port_dict)
if ((retval == 0) and (is_port_dict_updated is True)):
return True, port_dict
interrupt_count_end = self.get_register(self.OIR_FD_PATH)
if (interrupt_count_start == 'ERR' or
interrupt_count_end == 'ERR'):
print("get_transceiver_change_event : \
unable to retrive interrupt count")
break
# check_interrupts() itself may take upto 100s of msecs.
# We detect a missed interrupt based on the count
if interrupt_count_start == interrupt_count_end:
break
# Block until an xcvr is inserted or removed with timeout = -1
events = self.epoll.poll(
timeout=timeout if timeout != 0 else -1)
if events:
# check interrupts and return the port_dict
retval, is_port_dict_updated = \
self.check_interrupts(port_dict)
if (retval != 0):
return False, {}
return True, port_dict
except:
return False, {}
finally:
if self.oir_fd != -1:
self.epoll.unregister(self.oir_fd.fileno())
self.epoll.close()
self.oir_fd.close()
self.oir_fd = -1
self.epoll = -1
return False, {}

3
device/mellanox/x86_64-mlnx_msn2410-r0/ACS-MSN2410/sai_2410.xml
View File

@ -5,6 +5,9 @@
<!-- Device MAC address -->
<device-mac-address>00:02:03:04:05:00</device-mac-address>
<!-- ISSU enabled -->
<issu-enabled>1</issu-enabled>
<!-- Number of ports in the following port list -->
<number-of-physical-ports>56</number-of-physical-ports>

4
dockers/docker-fpm-frr/Dockerfile.j2
View File

@ -13,7 +13,7 @@ ENV DEBIAN_FRONTEND=noninteractive
RUN apt-get update
# Install required packages
RUN apt-get install -y libdbus-1-3 libdaemon0 libjansson4 libc-ares2 iproute2 libpython2.7 libjson-c3 logrotate
RUN apt-get install -y libdbus-1-3 libdaemon0 libjansson4 libc-ares2 iproute2 libpython2.7 libjson-c3 logrotate libunwind8
{% if docker_fpm_frr_debs.strip() -%}
# Copy locally-built Debian package dependencies
@ -30,6 +30,8 @@ RUN dpkg_apt() { [ -f $1 ] && { dpkg -i $1 || apt-get -y install -f; } || return
{%- endfor %}
{%- endif %}
RUN chown -R ${frr_user_uid}:${frr_user_gid} /etc/frr/
# Clean up
RUN apt-get clean -y
RUN apt-get autoclean -y

1
dockers/docker-fpm-frr/start.sh
View File

@ -32,6 +32,7 @@ supervisorctl start bgpcfgd
# Start Quagga processes
supervisorctl start zebra
supervisorctl start staticd
supervisorctl start bgpd
if [ "$CONFIG_TYPE" == "unified" ]; then

9
dockers/docker-fpm-frr/supervisord.conf
View File

@ -39,6 +39,15 @@ startsecs=0
stdout_logfile=syslog
stderr_logfile=syslog
[program:staticd]
command=/usr/lib/frr/staticd -A 127.0.0.1
priority=4
autostart=false
autorestart=false
startsecs=0
stdout_logfile=syslog
stderr_logfile=syslog
[program:bgpd]
command=/usr/lib/frr/bgpd -A 127.0.0.1
priority=5

13
dockers/docker-lldp-sv2/lldpmgrd
View File

@ -74,11 +74,14 @@ def signal_handler(sig, frame):
# ========================== Helpers ==================================
def is_port_exist(port_name):
filename = "/sys/class/net/%s/ifindex" % port_name
if not os.path.exists(filename):
return False
return True
filename = "/sys/class/net/%s/operstate" % port_name
if os.path.exists(filename):
with open(filename) as fp:
state = fp.read()
return "up" in state
else:
filename = "/sys/class/net/%s/ifindex" % port_name
return os.path.exists(filename)
# ============================== Classes ==============================

2
dockers/docker-platform-monitor/Dockerfile.j2
View File

@ -7,7 +7,7 @@ RUN [ -f /etc/rsyslog.conf ] && sed -ri "s/%syslogtag%/$docker_container_name#%s
ENV DEBIAN_FRONTEND=noninteractive
# Install required packages
RUN apt-get update && apt-get install -y python-pip libpython2.7 ipmitool librrd8 librrd-dev rrdtool
RUN apt-get update && apt-get install -y python-pip libpython2.7 ipmitool librrd8 librrd-dev rrdtool python-smbus ethtool
{% if docker_platform_monitor_debs.strip() -%}
# Copy locally-built Debian package dependencies

60
files/Aboot/boot0.j2
View File

@ -68,6 +68,8 @@ cmdline_base="$target_path/kernel-params-base"
cmdline_image="$image_path/kernel-cmdline"
boot_config="$target_path/boot-config"
swi_tmpfs="/tmp/tmp-swi"
bootconfigvars="KERNEL INITRD CONSOLESPEED PASSWORD NETDEV NETAUTO NETIP NETMASK NETGW NETDOMAIN NETDNS NETHW memtest"
flash_re=" /mnt/flash| /host"
@ -126,9 +128,34 @@ update_next_boot() {
fi
}
move_swi_to_tmpfs() {
local oldswi="$1"
local newswi="$swi_tmpfs/$(basename $oldswi)"
mkdir -p "$swi_tmpfs"
if ! $in_aboot && ! mount | grep -q ' /tmp type tmpfs'; then
# mount a real tmpfs on /tmp/tmp-swi if /tmp is not one already.
mount -t tmpfs tmp-swi "$swi_tmpfs"
fi
mv "$oldswi" "$newswi"
echo "$newswi"
}
cleanup_swi_tmpfs() {
rm -f "$swipath"
if mount | grep -q "$swi_tmpfs"; then
umount "$swi_tmpfs" || :
fi
}
extract_image() {
mkdir -p "$image_path"
info "Moving swi to a tmpfs"
## Avoid problematic flash usage spike on older systems, also improves I/O
swipath="$(move_swi_to_tmpfs $swipath)"
info "Extracting swi content"
## Unzip the image except boot0 and dockerfs archive
unzip -oq "$swipath" -x boot0 "$dockerfs" -d "$image_path"
@ -146,7 +173,6 @@ extract_image() {
fi
## extract docker archive
info "Unpacking $dockerfs"
unzip -oqp "$swipath" "$dockerfs" | tar xzf - -C "$image_path/{{ DOCKERFS_DIR }}" $TAR_EXTRA_OPTION
else
## save dockerfs archive in the image directory
@ -154,14 +180,15 @@ extract_image() {
info "Unpacking $dockerfs delayed to initrd because $target_path is $rootfs_type"
fi
## remove installer since it's not needed anymore
info "Remove installer"
cleanup_swi_tmpfs
## use new reduced-size boot swi
local swi_boot_path="flash:$image_name/{{ ABOOT_BOOT_IMAGE }}"
update_boot_config SWI "$swi_boot_path"
update_boot_config SWI_DEFAULT "$swi_boot_path"
## Remove installer swi as it has lots of redundunt contents
rm -f "$swipath"
## sync disk operations
sync
}
@ -205,7 +232,8 @@ platform_specific() {
flash_size=3700
echo "modprobe.blacklist=radeon,sp5100_tco" >>/tmp/append
fi
if [ "$sid" = "Upperlake" ] || [ "$sid" = "UpperlakeES" ]; then
if [ "$sid" = "Upperlake" ] || [ "$sid" = "UpperlakeES" ] ||
[ "$sid" = "UpperlakeSsd" ]; then
aboot_machine=arista_7060_cx32s
flash_size=3700
echo "amd_iommu=off" >> /tmp/append
@ -227,8 +255,13 @@ platform_specific() {
aboot_machine=arista_7060dx4_32
flash_size=28000
fi
if [ "$platform" = "rook" ]; then
echo "iommu=on intel_iommu=on tsc=reliable pcie_ports=native" >>/tmp/append
if [ "$sid" = "Smartsville" ]; then
aboot_machine=arista_7280cr3_32p4
flash_size=7382
fi
if [ "$platform" = "rook" ] || [ "$platform" = "magpie" ] ||
[ "$platform" = "woodpecker" ]; then
echo "tsc=reliable pcie_ports=native" >>/tmp/append
echo "rhash_entries=1 usb-storage.delay_use=0" >>/tmp/append
if [ -x /bin/readprefdl ]; then
readprefdl -f /tmp/.system-prefdl -d > /mnt/flash/.system-prefdl
@ -238,6 +271,12 @@ platform_specific() {
fi
echo "reassign_prefmem" >> /tmp/append
fi
if [ "$platform" = "rook" ] || [ "$platform" = "magpie" ]; then
echo "iommu=on intel_iommu=on" >>/tmp/append
fi
if [ "$platform" = "woodpecker" ]; then
echo "amd_iommu=off modprobe.blacklist=snd_hda_intel,hdaudio" >> /tmp/append
fi
if [ $flash_size -ge 28000 ]; then
varlog_size=4096
@ -304,7 +343,7 @@ write_boot_configs() {
fi
fi
mv /tmp/append $cmdline_image
cat /tmp/append > $cmdline_image
[ -e ${target_path}/machine.conf ] || write_machine_config
}
@ -313,7 +352,10 @@ run_kexec() {
local kernel="${KERNEL:-$(find $image_path/boot -name 'vmlinuz-*' -type f | head -n 1)}"
local initrd="${INITRD:-$(find $image_path/boot -name 'initrd.img-*' -type f | head -n 1)}"
if ! $verbose; then
if $verbose; then
# show systemd showdown sequence when verbose is set
cmdline="$cmdline systemd.show_status=true"
else
# Start showing systemd information from the first failing unit if any.
# systemd.show_status=false or quiet can be used to silence systemd entierly
cmdline="$cmdline systemd.show_status=auto"

10
files/build_templates/sonic_debian_extension.j2
View File

@ -111,6 +111,8 @@ sudo dpkg --root=$FILESYSTEM_ROOT -i $debs_path/python-click*_all.deb || \
# Install python pexpect used by sonic-utilities consutil
# using pip install instead to get a more recent version than is available through debian
sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip install pexpect
# Install python click-default-group by sonic-utilities
sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip install click-default-group==1.2
# Install tabulate >= 0.8.1 via pip in order to support multi-line row output for sonic-utilities
sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip install tabulate==0.8.2
@ -325,10 +327,10 @@ sudo cp {{src}} $FILESYSTEM_ROOT/{{dst}}
{% if sonic_asic_platform == "mellanox" %}
sudo mkdir -p $FILESYSTEM_ROOT/etc/mlnx/
sudo cp target/files/$MLNX_SPC_FW_FILE $FILESYSTEM_ROOT/etc/mlnx/fw-SPC.mfa
sudo cp target/files/$MLNX_SPC2_FW_FILE $FILESYSTEM_ROOT/etc/mlnx/fw-SPC2.mfa
sudo cp target/files/$ISSU_VERSION_FILE $FILESYSTEM_ROOT/etc/mlnx/issu-version
sudo cp target/files/$MLNX_FFB_SCRIPT $FILESYSTEM_ROOT/usr/bin/mlnx-ffb.sh
sudo cp $files_path/$MLNX_SPC_FW_FILE $FILESYSTEM_ROOT/etc/mlnx/fw-SPC.mfa
sudo cp $files_path/$MLNX_SPC2_FW_FILE $FILESYSTEM_ROOT/etc/mlnx/fw-SPC2.mfa
sudo cp $files_path/$ISSU_VERSION_FILE $FILESYSTEM_ROOT/etc/mlnx/issu-version
sudo cp $files_path/$MLNX_FFB_SCRIPT $FILESYSTEM_ROOT/usr/bin/mlnx-ffb.sh
j2 platform/mellanox/mlnx-fw-upgrade.j2 | sudo tee $FILESYSTEM_ROOT/usr/bin/mlnx-fw-upgrade.sh
sudo chmod 755 $FILESYSTEM_ROOT/usr/bin/mlnx-fw-upgrade.sh
{% endif %}

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