Update DellEMC-Z9332f-M-O16C64 SKU settings (#7908)
This commit is contained in:
Aravind Mani
Guohan Lu
parent
1f1718ace6
commit
8e8a26fd41
@ -1,2 +1,2 @@
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th3-z9332f-32x400G.config.bcm
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th3-z9332f-16x400G-64x100G.config.bcm
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SAI_NUM_ECMP_MEMBERS=64
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@ -3,10 +3,10 @@ link off
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counter off
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#***
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#*** Port CD0 Preemphasis setting ***
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#*** Port CE0-CE3 Preemphasis setting ***
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#***
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local port cd0
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local port ce0
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
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@ -25,6 +25,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce1
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
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@ -43,6 +44,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
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local port ce2
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#*** lane 4 ***
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E4
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@ -61,6 +63,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
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local port ce3
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#*** lane 6 ***
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E4
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@ -82,10 +85,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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#***
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#*** Port CD1 Preemphasis setting ***
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#*** Port CE4-CE7 Preemphasis setting ***
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#***
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local port cd1
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local port ce4
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
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@ -104,6 +107,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce5
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
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@ -122,6 +126,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
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local port ce6
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#*** lane 4 ***
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
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@ -140,6 +145,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
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local port ce7
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#*** lane 6 ***
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E4
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@ -161,10 +167,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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#***
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#*** Port CD2 Preemphasis setting ***
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#*** Port CE8-CE11 Preemphasis setting ***
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#***
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local port cd2
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local port ce8
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
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@ -183,6 +189,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce9
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
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@ -201,6 +208,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
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local port ce10
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#*** lane 4 ***
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
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@ -219,6 +227,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
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local port ce11
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#*** lane 6 ***
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
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@ -240,10 +249,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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#***
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#*** Port CD3 Preemphasis setting ***
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#*** Port CE12-CE15 Preemphasis setting ***
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#***
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local port cd3
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local port ce12
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
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@ -262,6 +271,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce13
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
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@ -280,6 +290,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
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local port ce14
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#*** lane 4 ***
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
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@ -298,6 +309,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
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local port ce15
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#*** lane 6 ***
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
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@ -319,10 +331,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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#***
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#*** Port CD4 Preemphasis setting ***
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#*** Port CE16-CE19 Preemphasis setting ***
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#***
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local port cd4
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local port ce16
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
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@ -341,6 +353,8 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce17
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E4
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@ -368,6 +382,8 @@ phy $port TXFIR_TAP_CTL4r.4 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.4 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP_LOAD=0x1
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local port ce18
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#*** lane 5 ***
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.5 TXFIR_TAP1_COEFF=0x1E8
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@ -386,6 +402,7 @@ phy $port TXFIR_TAP_CTL4r.6 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.6 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP_LOAD=0x1
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local port ce19
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#*** lane 7 ***
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phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.7 TXFIR_TAP1_COEFF=0x1E4
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@ -397,11 +414,12 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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#***
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#*** Port CD5 Preemphasis setting ***
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#*** Port CE20-CE23 Preemphasis setting ***
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#***
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local port cd5
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local port ce20
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
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@ -420,6 +438,8 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce21
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E4
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@ -438,6 +458,8 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
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local port ce22
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#*** lane 4 ***
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
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@ -456,6 +478,8 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
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local port ce23
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#*** lane 6 ***
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
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@ -476,11 +500,12 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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#***
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#*** Port CD6 Preemphasis setting ***
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#*** Port CD24-27 Preemphasis setting ***
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#***
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local port cd6
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local port ce24
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
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@ -499,6 +524,8 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce25
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
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@ -517,6 +544,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
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local port ce26
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#*** lane 4 ***
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E4
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@ -535,6 +563,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
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local port ce27
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#*** lane 6 ***
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E4
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@ -555,11 +584,12 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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local port ce28
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#***
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#*** Port CD7 Preemphasis setting ***
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#*** Port CE28-CE31 Preemphasis setting ***
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#***
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local port cd7
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
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@ -578,6 +608,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
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local port ce29
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#*** lane 2 ***
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phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
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@ -596,6 +627,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
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local port ce30
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#*** lane 4 ***
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phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
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@ -614,6 +646,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
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phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
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local port ce31
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#*** lane 6 ***
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phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
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phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
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@ -635,10 +668,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
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delay 10
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#***
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#*** Port CD8 Preemphasis setting ***
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#*** Port CE32-CE35 Preemphasis setting ***
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#***
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local port cd8
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local port ce32
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#*** lane 0 ***
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phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
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phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
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@ -657,6 +690,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
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phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce33
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -675,6 +709,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce34
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -693,6 +728,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce35
|
||||
#*** lane 6 ***
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -714,10 +750,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD9 Preemphasis setting ***
|
||||
#*** Port CD36-39 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd9
|
||||
local port ce36
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -736,6 +772,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce37
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -754,6 +791,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce38
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -772,6 +810,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce39
|
||||
#*** lane 6 ***
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -793,10 +832,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD10 Preemphasis setting ***
|
||||
#*** Port CE40-CE43 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd10
|
||||
local port ce40
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -815,6 +854,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce41
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -833,6 +873,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce42
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -851,6 +892,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce43
|
||||
#*** lane 6 ***
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -872,10 +914,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD11 Preemphasis setting ***
|
||||
#*** Port CE44-CE47 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd11
|
||||
local port ce44
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -894,6 +936,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce45
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -912,6 +955,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce46
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -939,6 +983,7 @@ phy $port TXFIR_TAP_CTL4r.6 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.6 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce47
|
||||
#*** lane 7 ***
|
||||
phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.7 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -951,10 +996,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD12 Preemphasis setting ***
|
||||
#*** Port CD0 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd12
|
||||
local port cd0
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1030,10 +1075,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD13 Preemphasis setting ***
|
||||
#*** Port CD1 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd13
|
||||
local port cd1
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1108,10 +1153,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD14 Preemphasis setting ***
|
||||
#*** Port CD2 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd14
|
||||
local port cd2
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1187,10 +1232,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD15 Preemphasis setting ***
|
||||
#*** Port CD3 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd15
|
||||
local port cd3
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1266,10 +1311,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD16 Preemphasis setting ***
|
||||
#*** Port CE48-CE51 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd16
|
||||
local port ce48
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1288,6 +1333,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce49
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1306,6 +1352,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce50
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1324,6 +1371,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce51
|
||||
#*** lane 6 ***
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1345,10 +1393,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD17 Preemphasis setting ***
|
||||
#*** Port CE52-CE55 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd17
|
||||
local port ce52
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1367,6 +1415,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce53
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1385,6 +1434,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce54
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1403,6 +1453,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce55
|
||||
#*** lane 6 ***
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1424,10 +1475,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD18 Preemphasis setting ***
|
||||
#*** Port CD56-59 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd18
|
||||
local port ce56
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1446,6 +1497,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce57
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1464,6 +1516,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce58
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1482,6 +1535,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce59
|
||||
#*** lane 6 ***
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1503,10 +1557,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD19 Preemphasis setting ***
|
||||
#*** Port CE60-CE63 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd19
|
||||
local port ce60
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1525,6 +1579,7 @@ phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce61
|
||||
#*** lane 2 ***
|
||||
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -1543,6 +1598,7 @@ phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce62
|
||||
#*** lane 4 ***
|
||||
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1561,6 +1617,7 @@ phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1
|
||||
|
||||
local port ce63
|
||||
#*** lane 6 ***
|
||||
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1582,10 +1639,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD20 Preemphasis setting ***
|
||||
#*** Port CD4 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd20
|
||||
local port cd4
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1661,10 +1718,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD21 Preemphasis setting ***
|
||||
#*** Port CD5 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd21
|
||||
local port cd5
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -1740,10 +1797,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD22 Preemphasis setting ***
|
||||
#*** Port CD6 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd22
|
||||
local port cd6
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1819,10 +1876,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD23 Preemphasis setting ***
|
||||
#*** Port CD7 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd23
|
||||
local port cd7
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -1898,10 +1955,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD24 Preemphasis setting ***
|
||||
#*** Port CD8 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd24
|
||||
local port cd8
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -1977,10 +2034,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD25 Preemphasis setting ***
|
||||
#*** Port CD9 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd25
|
||||
local port cd9
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -2055,10 +2112,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD26 Preemphasis setting ***
|
||||
#*** Port CD10 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd26
|
||||
local port cd10
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -2134,10 +2191,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD27 Preemphasis setting ***
|
||||
#*** Port CD11 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd27
|
||||
local port cd11
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -2213,10 +2270,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD28 Preemphasis setting ***
|
||||
#*** Port CD12 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd28
|
||||
local port cd12
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -2292,10 +2349,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD29 Preemphasis setting ***
|
||||
#*** Port CD13 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd29
|
||||
local port cd13
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
|
||||
@ -2371,10 +2428,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD30 Preemphasis setting ***
|
||||
#*** Port CD14 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd30
|
||||
local port cd14
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
|
||||
@ -2450,10 +2507,10 @@ phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1
|
||||
delay 10
|
||||
|
||||
#***
|
||||
#*** Port CD31 Preemphasis setting ***
|
||||
#*** Port CD15 Preemphasis setting ***
|
||||
#***
|
||||
|
||||
local port cd31
|
||||
local port cd15
|
||||
#*** lane 0 ***
|
||||
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=4
|
||||
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E4
|
||||
|
||||
@ -45,34 +45,94 @@ l2xlrn_thread_interval=50000
|
||||
l2xlrn_intr_en=0
|
||||
|
||||
pbmp_xport_xe=0xffffffFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE
|
||||
|
||||
phy_an_c73=3
|
||||
|
||||
portmap_1.0=1:400
|
||||
portmap_5.0=9:400
|
||||
portmap_10.0=17:400
|
||||
portmap_14.0=25:400
|
||||
portmap_20.0=33:100:2
|
||||
portmap_21.0=35:100:2
|
||||
portmap_22.0=37:100:2
|
||||
portmap_23.0=39:100:2
|
||||
|
||||
portmap_20.0=33:400
|
||||
portmap_24.0=41:400
|
||||
portmap_29.0=49:400
|
||||
portmap_33.0=57:400
|
||||
portmap_24.0=41:100:2
|
||||
portmap_25.0=43:100:2
|
||||
portmap_26.0=45:100:2
|
||||
portmap_27.0=47:100:2
|
||||
|
||||
portmap_28.0=49:100:2
|
||||
portmap_29.0=51:100:2
|
||||
portmap_30.0=53:100:2
|
||||
portmap_31.0=55:100:2
|
||||
|
||||
portmap_33.0=57:100:2
|
||||
portmap_34.0=59:100:2
|
||||
portmap_35.0=61:100:2
|
||||
portmap_36.0=63:100:2
|
||||
|
||||
portmap_40.0=65:100:2
|
||||
portmap_41.0=67:100:2
|
||||
portmap_42.0=69:100:2
|
||||
portmap_43.0=71:100:2
|
||||
|
||||
portmap_44.0=73:100:2
|
||||
portmap_45.0=75:100:2
|
||||
portmap_46.0=77:100:2
|
||||
portmap_47.0=79:100:2
|
||||
|
||||
portmap_49.0=81:100:2
|
||||
portmap_50.0=83:100:2
|
||||
portmap_51.0=85:100:2
|
||||
portmap_52.0=87:100:2
|
||||
|
||||
portmap_53.0=89:100:2
|
||||
portmap_54.0=91:100:2
|
||||
portmap_55.0=93:100:2
|
||||
portmap_56.0=95:100:2
|
||||
|
||||
portmap_1.0=1:100:2
|
||||
portmap_2.0=3:100:2
|
||||
portmap_3.0=5:100:2
|
||||
portmap_4.0=7:100:2
|
||||
|
||||
portmap_5.0=9:100:2
|
||||
portmap_6.0=11:100:2
|
||||
portmap_7.0=13:100:2
|
||||
portmap_8.0=15:100:2
|
||||
|
||||
portmap_10.0=17:100:2
|
||||
portmap_11.0=19:100:2
|
||||
portmap_12.0=21:100:2
|
||||
portmap_13.0=23:100:2
|
||||
|
||||
portmap_14.0=25:100:2
|
||||
portmap_15.0=27:100:2
|
||||
portmap_16.0=29:100:2
|
||||
portmap_17.0=31:100:2
|
||||
|
||||
portmap_80.0=129:100:2
|
||||
portmap_81.0=131:100:2
|
||||
portmap_82.0=133:100:2
|
||||
portmap_83.0=135:100:2
|
||||
|
||||
portmap_84.0=137:100:2
|
||||
portmap_85.0=139:100:2
|
||||
portmap_86.0=141:100:2
|
||||
portmap_87.0=143:100:2
|
||||
|
||||
portmap_89.0=145:100:2
|
||||
portmap_90.0=147:100:2
|
||||
portmap_91.0=149:100:2
|
||||
portmap_92.0=151:100:2
|
||||
|
||||
portmap_93.0=153:100:2
|
||||
portmap_94.0=155:100:2
|
||||
portmap_95.0=157:100:2
|
||||
portmap_96.0=159:100:2
|
||||
|
||||
portmap_40.0=65:400
|
||||
portmap_44.0=73:400
|
||||
portmap_49.0=81:400
|
||||
portmap_53.0=89:400
|
||||
|
||||
portmap_60.0=97:400
|
||||
portmap_64.0=105:400
|
||||
portmap_69.0=113:400
|
||||
portmap_73.0=121:400
|
||||
|
||||
portmap_80.0=129:400
|
||||
portmap_84.0=137:400
|
||||
portmap_89.0=145:400
|
||||
portmap_93.0=153:400
|
||||
|
||||
portmap_100.0=161:400
|
||||
portmap_104.0=169:400
|
||||
portmap_109.0=177:400
|
||||
Loading…
Reference in New Issue
Block a user