[devices]: Support 32x50G+16x40G profile on Seastone-DX010 (#2474)
The sai profile itself can support 32x50G+16x100G/40G while the initial port_config.ini uses 40G speeds for port 17-32. Signed-off-by: Zhenggen Xu <zxu@linkedin.com>
This commit is contained in:
zhenggen-xu
Ying Xie
parent
959a2ce26c
commit
7b33538686
@ -0,0 +1,49 @@
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# name lanes alias index speed
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Ethernet0 65,66 Eth1/1 0 50000
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Ethernet2 67,68 Eth1/2 0 50000
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Ethernet4 69,70 Eth2/1 1 50000
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Ethernet6 71,72 Eth2/2 1 50000
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Ethernet8 73,74 Eth3/1 2 50000
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Ethernet10 75,76 Eth3/2 2 50000
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Ethernet12 77,78 Eth4/1 3 50000
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Ethernet14 79,80 Eth4/2 3 50000
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Ethernet16 33,34 Eth5/1 4 50000
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Ethernet18 35,36 Eth5/2 4 50000
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Ethernet20 37,38 Eth6/1 5 50000
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Ethernet22 39,40 Eth6/2 5 50000
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Ethernet24 41,42 Eth7/1 6 50000
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Ethernet26 43,44 Eth7/2 6 50000
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Ethernet28 45,46 Eth8/1 7 50000
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Ethernet30 47,48 Eth8/2 7 50000
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Ethernet32 49,50 Eth9/1 8 50000
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Ethernet34 51,52 Eth9/2 8 50000
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Ethernet36 53,54 Eth10/1 9 50000
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Ethernet38 55,56 Eth10/2 9 50000
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Ethernet40 57,58 Eth11/1 10 50000
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Ethernet42 59,60 Eth11/2 10 50000
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Ethernet44 61,62 Eth12/1 11 50000
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Ethernet46 63,64 Eth12/2 11 50000
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Ethernet48 81,82 Eth13/1 12 50000
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Ethernet50 83,84 Eth13/2 12 50000
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Ethernet52 85,86 Eth14/1 13 50000
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Ethernet54 87,88 Eth14/2 13 50000
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Ethernet56 89,90 Eth15/1 14 50000
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Ethernet58 91,92 Eth15/2 14 50000
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Ethernet60 93,94 Eth16/1 15 50000
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Ethernet62 95,96 Eth16/2 15 50000
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Ethernet64 97,98,99,100 Eth17 16 40000
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Ethernet68 101,102,103,104 Eth18 17 40000
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Ethernet72 105,106,107,108 Eth19 18 40000
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Ethernet76 109,110,111,112 Eth20 19 40000
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Ethernet80 1,2,3,4 Eth21 20 40000
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Ethernet84 5,6,7,8 Eth22 21 40000
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Ethernet88 9,10,11,12 Eth23 22 40000
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Ethernet92 13,14,15,16 Eth24 23 40000
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Ethernet96 17,18,19,20 Eth25 24 40000
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Ethernet100 21,22,23,24 Eth26 25 40000
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Ethernet104 25,26,27,28 Eth27 26 40000
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Ethernet108 29,30,31,32 Eth28 27 40000
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Ethernet112 113,114,115,116 Eth29 28 40000
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Ethernet116 117,118,119,120 Eth30 29 40000
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Ethernet120 121,122,123,124 Eth31 30 40000
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Ethernet124 125,126,127,128 Eth32 31 40000
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@ -0,0 +1 @@
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-seastone-dx010-32x50G-16x100G.config.bcm
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@ -0,0 +1,499 @@
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# Define default OS / SAL
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os=unix
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# all XPORTs to XE ports
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#pbmp_xport_xe=0x1fffffffe
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pbmp_xport_xe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
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pbmp_oversubscribe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
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# Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or
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# L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification.
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l2xmsg_mode=1
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# Memory table size configs, enable ALPM
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l2_mem_entries=8192
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l3_mem_entries=8192
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l3_alpm_enable=2
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ipv6_lpm_128b_enable=1
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#Use MMU lossy configuration
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mmu_lossless=0
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###################################################################################
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# SeaStone customized configuration
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###################################################################################
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#ext mdio frequency to 495/0x80/2(1.933Mhz) or 415/0x80/2(1.62MHz)
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# default is 40
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# Set external MDIO freq to 6.19MHz (495MHz) or 5.19MHz (415MHz)
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#* target_freq is core_clock_freq * DIVIDEND / DIVISOR / 2
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#
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rate_ext_mdio_divisor=0x80
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# use internal rom boot
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phy_ext_rom_boot=0
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oversubscribe_mode=1
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# Map the physical ports to logical ports
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dport_map_enable=1
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dport_map_port_68=1
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dport_map_port_69=2
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dport_map_port_72=5
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dport_map_port_73=6
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dport_map_port_76=9
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dport_map_port_77=10
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dport_map_port_80=13
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dport_map_port_81=14
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dport_map_port_34=17
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dport_map_port_35=18
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dport_map_port_38=21
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dport_map_port_39=22
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dport_map_port_42=25
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dport_map_port_43=26
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dport_map_port_46=29
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dport_map_port_47=30
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dport_map_port_50=33
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dport_map_port_51=34
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dport_map_port_54=37
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dport_map_port_55=38
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dport_map_port_58=41
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dport_map_port_59=42
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dport_map_port_62=45
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dport_map_port_63=46
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dport_map_port_84=49
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dport_map_port_85=50
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dport_map_port_88=53
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dport_map_port_89=54
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dport_map_port_92=57
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dport_map_port_93=58
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dport_map_port_96=61
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dport_map_port_97=62
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# 100G/40G ports
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dport_map_port_102=65
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dport_map_port_106=69
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dport_map_port_110=73
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dport_map_port_114=77
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dport_map_port_1=81
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dport_map_port_5=85
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dport_map_port_9=89
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dport_map_port_13=93
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dport_map_port_17=97
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dport_map_port_21=101
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dport_map_port_25=105
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dport_map_port_29=109
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dport_map_port_118=113
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dport_map_port_122=117
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dport_map_port_126=121
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dport_map_port_130=125
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# port/lane mapping, 32x50G + 16x100G
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portmap_68=65:50:2
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portmap_69=67:50:2
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portmap_72=69:50:2
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portmap_73=71:50:2
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portmap_76=73:50:2
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portmap_77=75:50:2
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portmap_80=77:50:2
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portmap_81=79:50:2
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portmap_34=33:50:2
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portmap_35=35:50:2
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portmap_38=37:50:2
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portmap_39=39:50:2
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portmap_42=41:50:2
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portmap_43=43:50:2
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portmap_46=45:50:2
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portmap_47=47:50:2
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portmap_50=49:50:2
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portmap_51=51:50:2
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portmap_54=53:50:2
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portmap_55=55:50:2
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portmap_58=57:50:2
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portmap_59=59:50:2
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portmap_62=61:50:2
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portmap_63=63:50:2
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portmap_84=81:50:2
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portmap_85=83:50:2
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portmap_88=85:50:2
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portmap_89=87:50:2
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portmap_92=89:50:2
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portmap_93=91:50:2
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portmap_96=93:50:2
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portmap_97=95:50:2
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portmap_102=97:100:4
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portmap_106=101:100:4
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portmap_110=105:100:4
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portmap_114=109:100:4
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portmap_1=1:100:4
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portmap_5=5:100:4
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portmap_9=9:100:4
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portmap_13=13:100:4
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portmap_17=17:100:4
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portmap_21=21:100:4
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portmap_25=25:100:4
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portmap_29=29:100:4
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portmap_118=113:100:4
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portmap_122=117:100:4
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portmap_126=121:100:4
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portmap_130=125:100:4
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#WC16
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xgxs_tx_lane_map_68=0x3201
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xgxs_rx_lane_map_68=0x2310
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xgxs_tx_lane_map_69=0x3201
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xgxs_rx_lane_map_69=0x2310
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#WC17
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xgxs_tx_lane_map_72=0x3201
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xgxs_rx_lane_map_72=0x2301
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xgxs_tx_lane_map_73=0x3201
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xgxs_rx_lane_map_73=0x2301
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#WC18
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xgxs_tx_lane_map_76=0x0132
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xgxs_rx_lane_map_76=0x0123
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xgxs_tx_lane_map_77=0x0132
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xgxs_rx_lane_map_77=0x0123
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#WC19
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xgxs_tx_lane_map_80=0x2031
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xgxs_rx_lane_map_80=0x1320
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xgxs_tx_lane_map_81=0x2031
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xgxs_rx_lane_map_81=0x1320
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#WC8
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xgxs_tx_lane_map_34=0x3021
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xgxs_rx_lane_map_34=0x0213
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xgxs_tx_lane_map_35=0x3021
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xgxs_rx_lane_map_35=0x0213
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#WC9
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xgxs_tx_lane_map_38=0x3210
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xgxs_rx_lane_map_38=0x1023
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xgxs_tx_lane_map_39=0x3210
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xgxs_rx_lane_map_39=0x1023
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#WC10
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xgxs_tx_lane_map_42=0x2310
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xgxs_rx_lane_map_42=0x3210
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xgxs_tx_lane_map_43=0x2310
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xgxs_rx_lane_map_43=0x3210
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#WC11
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xgxs_tx_lane_map_46=0x1032
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xgxs_rx_lane_map_46=0x1302
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xgxs_tx_lane_map_47=0x1032
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xgxs_rx_lane_map_47=0x1302
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#WC12
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xgxs_tx_lane_map_50=0x3201
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xgxs_rx_lane_map_50=0x0213
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xgxs_tx_lane_map_51=0x3201
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xgxs_rx_lane_map_51=0x0213
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#WC13
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xgxs_tx_lane_map_54=0x2301
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xgxs_rx_lane_map_54=0x2310
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xgxs_tx_lane_map_55=0x2301
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xgxs_rx_lane_map_55=0x2310
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#WC14
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xgxs_tx_lane_map_58=0x3201
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xgxs_rx_lane_map_58=0x0213
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xgxs_tx_lane_map_59=0x3201
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xgxs_rx_lane_map_59=0x0213
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#WC15
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xgxs_tx_lane_map_62=0x1302
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xgxs_rx_lane_map_62=0x2310
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xgxs_tx_lane_map_63=0x1302
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xgxs_rx_lane_map_63=0x2310
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#WC20
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xgxs_tx_lane_map_84=0x0213
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xgxs_rx_lane_map_84=0x2301
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xgxs_tx_lane_map_85=0x0213
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xgxs_rx_lane_map_85=0x2301
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#WC21
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xgxs_tx_lane_map_88=0x0132
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xgxs_rx_lane_map_88=0x3210
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xgxs_tx_lane_map_89=0x0132
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xgxs_rx_lane_map_89=0x3210
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#WC22
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xgxs_tx_lane_map_92=0x0132
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xgxs_rx_lane_map_92=0x2031
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xgxs_tx_lane_map_93=0x0132
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xgxs_rx_lane_map_93=0x2031
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#WC23
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xgxs_tx_lane_map_96=0x2031
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xgxs_rx_lane_map_96=0x3201
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xgxs_tx_lane_map_97=0x2031
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xgxs_rx_lane_map_97=0x3201
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#WC24
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xgxs_tx_lane_map_102=0x0132
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xgxs_rx_lane_map_102=0x2301
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#WC25
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xgxs_tx_lane_map_106=0x0132
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xgxs_rx_lane_map_106=0x3201
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#WC26
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xgxs_tx_lane_map_110=0x0132
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xgxs_rx_lane_map_110=0x2031
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#WC27
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xgxs_tx_lane_map_114=0x2031
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xgxs_rx_lane_map_114=0x2301
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#WC0
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xgxs_tx_lane_map_1=0x3210
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xgxs_rx_lane_map_1=0x3120
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#WC1
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xgxs_tx_lane_map_5=0x0132
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xgxs_rx_lane_map_5=0x1023
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#WC2
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xgxs_tx_lane_map_9=0x3201
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xgxs_rx_lane_map_9=0x3120
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#WC3
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xgxs_tx_lane_map_13=0x2031
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xgxs_rx_lane_map_13=0x1032
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#WC4
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xgxs_tx_lane_map_17=0x2310
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xgxs_rx_lane_map_17=0x3210
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#WC5
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xgxs_tx_lane_map_21=0x2301
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xgxs_rx_lane_map_21=0x3120
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#WC6
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xgxs_tx_lane_map_25=0x3201
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xgxs_rx_lane_map_25=0x0213
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#WC7
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xgxs_tx_lane_map_29=0x1302
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xgxs_rx_lane_map_29=0x1023
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#WC28
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xgxs_tx_lane_map_118=0x1320
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xgxs_rx_lane_map_118=0x1302
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#WC29
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xgxs_tx_lane_map_122=0x1032
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xgxs_rx_lane_map_122=0x1023
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#WC30
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xgxs_tx_lane_map_126=0x3120
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xgxs_rx_lane_map_126=0x3120
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#WC31
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xgxs_tx_lane_map_130=0x1302
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xgxs_rx_lane_map_130=0x2310
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#Polarity flip settings
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#WC16
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phy_xaui_tx_polarity_flip_68=0x0000
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phy_xaui_rx_polarity_flip_68=0x0000
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phy_xaui_tx_polarity_flip_69=0x0000
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phy_xaui_rx_polarity_flip_69=0x0000
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#WC17
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phy_xaui_tx_polarity_flip_72=0x0001
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phy_xaui_rx_polarity_flip_72=0x0002
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phy_xaui_tx_polarity_flip_73=0x0003
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phy_xaui_rx_polarity_flip_73=0x0000
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#WC18
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phy_xaui_tx_polarity_flip_76=0x0003
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phy_xaui_rx_polarity_flip_76=0x0000
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phy_xaui_tx_polarity_flip_77=0x0003
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phy_xaui_rx_polarity_flip_77=0x0000
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#WC19
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phy_xaui_tx_polarity_flip_80=0x0003
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phy_xaui_rx_polarity_flip_80=0x0003
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phy_xaui_tx_polarity_flip_81=0x0003
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phy_xaui_rx_polarity_flip_81=0x0003
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#WC8
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phy_xaui_tx_polarity_flip_34=0x0002
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phy_xaui_rx_polarity_flip_34=0x0000
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phy_xaui_tx_polarity_flip_35=0x0003
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phy_xaui_rx_polarity_flip_35=0x0000
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#WC9
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phy_xaui_tx_polarity_flip_38=0x0000
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phy_xaui_rx_polarity_flip_38=0x0000
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phy_xaui_tx_polarity_flip_39=0x0002
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phy_xaui_rx_polarity_flip_39=0x0000
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#WC10
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phy_xaui_tx_polarity_flip_42=0x0001
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phy_xaui_rx_polarity_flip_42=0x0000
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phy_xaui_tx_polarity_flip_43=0x0003
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phy_xaui_rx_polarity_flip_43=0x0000
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#WC11
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phy_xaui_tx_polarity_flip_46=0x0000
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phy_xaui_rx_polarity_flip_46=0x0000
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phy_xaui_tx_polarity_flip_47=0x0000
|
||||
phy_xaui_rx_polarity_flip_47=0x0000
|
||||
|
||||
#WC12
|
||||
phy_xaui_tx_polarity_flip_50=0x0002
|
||||
phy_xaui_rx_polarity_flip_50=0x0000
|
||||
phy_xaui_tx_polarity_flip_51=0x0000
|
||||
phy_xaui_rx_polarity_flip_51=0x0000
|
||||
|
||||
#WC13
|
||||
phy_xaui_tx_polarity_flip_54=0x0002
|
||||
phy_xaui_rx_polarity_flip_54=0x0000
|
||||
phy_xaui_tx_polarity_flip_55=0x0000
|
||||
phy_xaui_rx_polarity_flip_55=0x0000
|
||||
|
||||
#WC14
|
||||
phy_xaui_tx_polarity_flip_58=0x0000
|
||||
phy_xaui_rx_polarity_flip_58=0x0000
|
||||
phy_xaui_tx_polarity_flip_59=0x0000
|
||||
phy_xaui_rx_polarity_flip_59=0x0000
|
||||
|
||||
#WC15
|
||||
phy_xaui_tx_polarity_flip_62=0x0002
|
||||
phy_xaui_rx_polarity_flip_62=0x0003
|
||||
phy_xaui_tx_polarity_flip_63=0x0002
|
||||
phy_xaui_rx_polarity_flip_63=0x0003
|
||||
|
||||
#WC20
|
||||
phy_xaui_tx_polarity_flip_84=0x0003
|
||||
phy_xaui_rx_polarity_flip_84=0x0002
|
||||
phy_xaui_tx_polarity_flip_85=0x0001
|
||||
phy_xaui_rx_polarity_flip_85=0x0003
|
||||
|
||||
#WC21
|
||||
phy_xaui_tx_polarity_flip_88=0x0001
|
||||
phy_xaui_rx_polarity_flip_88=0x0001
|
||||
phy_xaui_tx_polarity_flip_89=0x0003
|
||||
phy_xaui_rx_polarity_flip_89=0x0003
|
||||
|
||||
#WC22
|
||||
phy_xaui_tx_polarity_flip_92=0x0003
|
||||
phy_xaui_rx_polarity_flip_92=0x0000
|
||||
phy_xaui_tx_polarity_flip_93=0x0003
|
||||
phy_xaui_rx_polarity_flip_93=0x0002
|
||||
|
||||
#WC23
|
||||
phy_xaui_tx_polarity_flip_96=0x0001
|
||||
phy_xaui_rx_polarity_flip_96=0x0000
|
||||
phy_xaui_tx_polarity_flip_97=0x0001
|
||||
phy_xaui_rx_polarity_flip_97=0x0000
|
||||
|
||||
#WC24
|
||||
phy_xaui_tx_polarity_flip_102=0x0000
|
||||
phy_xaui_rx_polarity_flip_102=0x000F
|
||||
|
||||
#WC25
|
||||
phy_xaui_tx_polarity_flip_106=0x000F
|
||||
phy_xaui_rx_polarity_flip_106=0x0000
|
||||
|
||||
#WC26
|
||||
phy_xaui_tx_polarity_flip_110=0x000F
|
||||
phy_xaui_rx_polarity_flip_110=0x000F
|
||||
|
||||
#WC27
|
||||
phy_xaui_tx_polarity_flip_114=0x000F
|
||||
phy_xaui_rx_polarity_flip_114=0x0007
|
||||
|
||||
#WC0
|
||||
phy_xaui_tx_polarity_flip_1=0x0003
|
||||
phy_xaui_rx_polarity_flip_1=0x000F
|
||||
|
||||
#WC1
|
||||
phy_xaui_tx_polarity_flip_5=0x0007
|
||||
phy_xaui_rx_polarity_flip_5=0x0000
|
||||
|
||||
#WC2
|
||||
phy_xaui_tx_polarity_flip_9=0x0002
|
||||
phy_xaui_rx_polarity_flip_9=0x0008
|
||||
|
||||
#WC3
|
||||
phy_xaui_tx_polarity_flip_13=0x000F
|
||||
phy_xaui_rx_polarity_flip_13=0x0000
|
||||
|
||||
#WC4
|
||||
phy_xaui_tx_polarity_flip_17=0x0007
|
||||
phy_xaui_rx_polarity_flip_17=0x0000
|
||||
|
||||
#WC5
|
||||
phy_xaui_tx_polarity_flip_21=0x0000
|
||||
phy_xaui_rx_polarity_flip_21=0x0000
|
||||
|
||||
#WC6
|
||||
phy_xaui_tx_polarity_flip_25=0x0002
|
||||
phy_xaui_rx_polarity_flip_25=0x0005
|
||||
|
||||
#WC7
|
||||
phy_xaui_tx_polarity_flip_29=0x0002
|
||||
phy_xaui_rx_polarity_flip_29=0x0000
|
||||
|
||||
#WC28
|
||||
phy_xaui_tx_polarity_flip_118=0x000F
|
||||
phy_xaui_rx_polarity_flip_118=0x000F
|
||||
|
||||
#WC29
|
||||
phy_xaui_tx_polarity_flip_122=0x0004
|
||||
phy_xaui_rx_polarity_flip_122=0x0000
|
||||
|
||||
#WC30
|
||||
phy_xaui_tx_polarity_flip_126=0x000F
|
||||
phy_xaui_rx_polarity_flip_126=0x0000
|
||||
|
||||
#WC31
|
||||
phy_xaui_tx_polarity_flip_130=0x0006
|
||||
phy_xaui_rx_polarity_flip_130=0x0000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user